| PART |
Description |
Maker |
| LH28F160S5HT-L70 LHF16KA3 |
Flash Memory 16M (2MB 8/1MB 16)
Flash Memory 16M (2MB × 8/1MB × 16)
|
Sharp Corporation
Sharp Electrionic Components
|
| LHF16KA9 LH28F160S5T-L70 LH28F160S5T-L70A |
Flash Memory 16M (2MB × 8/1MB × 16)
|
Sharp Electrionic Components
|
| LH28F160S5NS-L70 LHF16KA4 |
Flash Memory 16M (2MB 】 8/1MB 】 16)
Flash Memory 16M (2MB 8/1MB 16)
|
SHARP[Sharp Electrionic Components]
|
| M295V160BB70N1T M29F160 M295V160BB55N1T M295V160BT |
16 Mbit 2Mb x8 or 1Mb x16, Boot Block Single Supply Flash Memory
16 Mbit 2Mb x8 or 1Mb x16 / Boot Block Single Supply Flash Memory
8-Bit, 0.1 us Dual MDAC, Parallel Input, Fast Control Signalling for DSP, Easy Micro I/F 20-PLCC -25 to 85
16-Bit Bus Transceiver with 3-State Outputs 56-BGA MICROSTAR JUNIOR -40 to 85 16兆位Mb x81兆x16插槽，启动座单电源闪
16 Mbit 2Mb x8 or 1Mb x16, Boot Block Single Supply Flash Memory 16兆位Mb x81兆x16插槽，启动座单电源闪
8-Bit, 0.1 us Dual MDAC, Parallel Input, Fast Control Signalling for DSP, Easy Micro I/F 20-PDIP -40 to 85 16兆位Mb x81兆x16插槽，启动座单电源闪
16-Bit Transparent D-Type Latch With 3-State Outputs 48-TVSOP -40 to 85 16兆位Mb x8兆x16插槽，启动座单电源闪
16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 48-TVSOP -40 to 85 16兆位Mb x8兆x16插槽，启动座单电源闪
|
ST Microelectronics
意法半导
STMicroelectronics N.V.
|
| MCM36F9DG10 MCM36F8 MCM36F8DG10 MCM36F9 |
1MB and 2MB Synchronous Fast Static RAM Module
|
MOTOROLA[Motorola, Inc]
|
| M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
| M29F160BT70N6T M295V160BB55N1T M295V160BB55N3T M29 |
16 MBIT (2MB X8 OR 1MB X16, BOOT BLOCK) SINGLE SUPPLY FLASH MEMORY
16 Mbit 2Mb x8 or 1Mb x16, Boot Block Single Supply Flash Memory
|
ST Microelectronics
STMICROELECTRONICS[STMicroelectronics]
|
| M27C160-50B1 M27C160-120S1TR -M27C160-150M6 |
16 Mbit 2Mb x8 or 1Mb x16 UV EPROM and OTP EPROM
|
意法半导
|
| HYB3165405ATL-60 HYB3165405ATL-50 HYB3165405ATL-40 |
16M x 4 Bit 4k EDO DRAM
16M x 4 Bit 8k EDO DRAM
16M x 4-Bit Dynamic RAM (4k & 8k Refresh, EDO-Version)
From old datasheet system
|
Infineon
SIEMENS[Siemens Semiconductor Group]
|
| K9F2808U0C-VIB0 K9F2808Q0C-DCB0 K9F2808U0C-DCB0 K9 |
16M x 8 Bit / 8M x 16 Bit NAND Flash Memory
16M x 8 Bit , 8M x 16 Bit NAND Flash Memory 1,600 × 8位，8米16位NAND闪存
16M X 8 FLASH 2.7V PROM, 30 ns, PBGA63
|
SAMSUNG SEMICONDUCTOR CO. LTD.
Samsung Semiconductor Co., Ltd.
|
| HYM72V1600GS-50 HYM72V1610GS-50 HYM72V1600GS-50- H |
16M x 72-Bit Dynamic RAM Module 16米x 72位动态随机存储器模块
16M x 72-Bit Dynamic RAM Module 16M X 72 FAST PAGE DRAM MODULE, 60 ns, DMA168
|
SIEMENS AG
Siemens Semiconductor Group
|
| MBM29F016A-90PFTN MBM29F016A-90PFTR MBM29F016A-12 |
FLASH MEMORY 16M (2M x 8) BIT
CMOS 16M (2M x 8) bit
|
Fujitsu Microelectronics
|
