| PART |
Description |
Maker |
| AS5SP512K18DQ AS5SP512K18DQ-30ET AS5SP512K18DQ-30I |
512K X 18 CACHE SRAM, 4 ns, PQFP100
Plastic Encapsulated Microcircuit 9Mb, 512K x 18, Synchronous SRAM Pipeline Burst, Single Cycle Deselect
|
MICROSS COMPONENTS
Austin Semiconductor
|
| IS61NVVP51236-200BI IS61NVVP51236-250B IS61NVVP512 |
256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM 512K X 36 ZBT SRAM, 3 ns, PBGA119
256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM 512K X 36 ZBT SRAM, 2.6 ns, PBGA119
|
Integrated Silicon Solution, Inc.
|
| IS61NVVP25672-250B IS61NVVP25672-250BI IS61NVVP256 |
256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM
|
ISSI[Integrated Silicon Solution, Inc]
|
| IS61VPS10018-166TQ IS61VPS10018-200B IS61VPS51232- |
1024K x 18 synchronous pipeline, single-cycle deselect static RAM
512K x 32 synchronous pipeline, single-cycle deselect static RAM
512K x 36 synchronous pipeline, single-cycle deselect static RAM
|
Integrated Silicon Solution Inc
|
| M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
| AS7C33128PFD36A-166TQI AS7C33128PFD32A AS7C33128PF |
3.3V 128K x 36 pipeline synchronous SRAM, clock speed - 150MHz
3.3V 128K x 36 pipeline synchronous SRAM, clock speed - 133MHz
3.3V 128K x 36 pipeline synchronous SRAM, clock speed - 100MHz
3.3V 128K x 32 pipeline synchronous SRAM, clock speed - 166MHz
3.3V 128K x 32 pipeline synchronous SRAM, clock speed - 150MHz
3.3V 128K x 32 pipeline synchronous SRAM, clock speed - 133MHz
3.3V 128K x 32 pipeline synchronous SRAM, clock speed - 100MHz
3.3V 128K X 32/36 pipeline burst synchronous SRAM 128K X 32 STANDARD SRAM, 10 ns, PQFP100
|
Alliance Semiconductor, Corp.
ALSC[Alliance Semiconductor Corporation]
Alliance Semiconductor Corp...
|
| AS7C3256PFS18A-4TQC AS7C3256PFS16A-4TQC AS7C3256PF |
3.3V 256K x 18 pipeline burst synchronous SRAM, 166 MHz
3.3V 256K x 16 pipeline burst synchronous SRAM, 133 MHz
3.3V 256K x 16 pipeline burst synchronous SRAM, 166 MHz
256K X 18 STANDARD SRAM, 4 ns, PQFP100 14 X 20 MM, TQFP-100
256K X 16 STANDARD SRAM, 4 ns, PQFP100 14 X 20 MM, TQFP-100
256K X 16 STANDARD SRAM, 3.8 ns, PQFP100
3.3V 256K x 16/18 pipeline burst synchronous SRAM
3.3V 256K x 16 pipeline burst synchronous SRAM, 150 MHz
3.3V 256K x 16 pipeline burst synchronous SRAM, 100 MHz
|
Alliance Semiconductor, Corp.
ALLIANCE SEMICONDUCTOR CORP
|
| TDC1011B2A TDC1011B2C TDC1011C3C TDC1011B7C TDC101 |
8-BIT, DSP-PIPELINE REGISTER, CDIP24
8-BIT, DSP-PIPELINE REGISTER, CQCC28
|
TRW INC
|
| AS7C33256PFD16A AS7C33256PFD18A AS7C33256PFD18A-10 |
3.3V 256K x 16/18 pipeline burst synchronous SRAM
3.3V 256K x 18 pipeline burst synchronous SRAM, clock speed - 100 MHz
3.3V 256K x 18 pipeline burst synchronous SRAM, clock speed - 133 MHz
3.3V 256K x 18 pipeline burst synchronous SRAM, clock speed - 150 MHz
3.3V 256K x 18 pipeline burst synchronous SRAM, clock speed - 166 MHz
3.3V 256K x 16 pipeline burst synchronous SRAM, clock speed - 133 MHz
3.3V 256K x 16 pipeline burst synchronous SRAM, clock speed - 100 MHz
3.3V 256K x 16 pipeline burst synchronous SRAM, clock speed - 150 MHz
3.3V 256K x 16 pipeline burst synchronous SRAM, clock speed - 166 MHz
|
Alliance Semiconductor
|
| CY7C1049CV33 CY7C1049CV33-15ZXC CY7C1049CV33-10VC |
4-Mbit (512K x 8) Static RAM
512K x 8 Static RAM 512K X 8 STANDARD SRAM, 15 ns, PDSO36
512K x 8 Static RAM 512K X 8 STANDARD SRAM, 15 ns, PDSO44
512K x 8 Static RAM 12k × 8静态RAM
512K x 8 Static RAM 512K X 8 STANDARD SRAM, 12 ns, PDSO44
|
CYPRESS[Cypress Semiconductor]
Cypress Semiconductor, Corp.
Cypress Semiconductor Corp.
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