| PART |
Description |
Maker |
| CY7C1423AV18-250BZC |
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture 2M X 18 DDR SRAM, 0.45 ns, PBGA165
|
Analog Integrations, Corp.
|
| CY7C1423KV18 CY7C1429KV18 |
36-Mbit DDR II SIO SRAM 2-Word Burst Architecture
|
Cypress Semiconductor
|
| CY7C1394JV18-300BZC CY7C1394JV18-300BZI CY7C1394JV |
18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
|
Cypress Semiconductor
|
| CY7C1529AV18 CY7C1529AV18-167BZC CY7C1522AV18 CY7C |
72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
|
Cypress Semiconductor
|
| CY7C1423BV18 CY7C1423BV18-167BZC CY7C1422BV18 CY7C |
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
|
Cypress Semiconductor
|
| CY7C1393KV18-333BZI CY7C1393KV18-300BZXC |
18-Mbit DDR II SIO SRAM Two-Word Burst Architecture
|
Cypress
|
| CY7C1623KV18 CY7C1623KV18-333BZXC |
144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture
|
Cypress Semiconductor
|
| CAT64LC10ZJ CAT64LC10ZP CAT64LC10J-TE7 CAT64LC10J- |
18-Mbit QDR™-II SRAM 4-Word Burst Architecture
18-Mbit DDR-II SRAM 2-Word Burst Architecture
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
4-Mbit (256K x 18) Flow-Through Sync SRAM SPI串行EEPROM
SPI Serial EEPROM SPI串行EEPROM
|
Analog Devices, Inc.
|
| CY7C1518JV18-250BZC CY7C1518JV18-300BZXC |
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| CY7C1250V18-300BZI CY7C1246V18-333BZI CY7C1246V18- |
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 36兆位的DDR - II SRAM2字突发架构（2.0周期读写延迟
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 1M X 36 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
|
| CY7C1568KV18-500BZXC CY7C1568KV18-500BZC CY7C1570K |
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 DDR SRAM, 0.45 ns, PBGA165
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 2M X 36 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
|
| CY7C1277V18-300BZC CY7C1266V18-300BZXC CY7C1266V18 |
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 4M X 9 DDR SRAM, 0.45 ns, PBGA165
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 4M X 8 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
