| PART |
Description |
Maker |
| ICS831721I 831721AGILFT |
Differential Clock/Data Multiplexer
|
http://
Integrated Device Technology
|
| ICS831742I |
Differential Clock/Data Multiplexer
|
Integrated Device Technology, Inc.
|
| 2795R 2795AB 2795B 2795C 2795D 2795P |
Fault-Protected Analog Multiplexer with Latch
622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier
622Mbps, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier
Signal Line Circuit Protector with Three Independent Protectors
HIGH FREQUENCY MAGNETICS T1/E1 Miniature Surface Mount Tranformers
|
BEL[Bel Fuse Inc.]
|
| MC100EP16VA MC100EP17 MC100EP29 MC100EP35 MC100EP4 |
3.3V / 5V ECL Differential Receiver/Driver with High Gain
3.3V / 5V ECL Quad Differential Driver/Receiver
3.3V / 5V ECL Dual Differential Data and Clock D Flip?Flop With Set and Reset
3.3V / 5V ECL JK Flip?Flop
3.3V/5V ECL 8?Bit Serial/Parallel Converter
3.3V / 5V ECL Differential Data and Clock D Flip?Flop
3.3V / 5V ECL 4:1 Differential Multiplexer
3.3V / 5V ECL 2:1 Multiplexer
9?Bit TTL to ECL Translator
3.3V / 5V ECL 8?Bit Synchronous Binary Up Counter
3.3V / 5V ECL 2?Input Differential AND/NAND
3.3V / 5V ECL Quad 4?Input OR/NOR
3.3V / 5V ECL Quad 2?Input Differential AND/NAND
3.3 V / 5 V Hex Differential Line Receiver/Driver
3.3V / 5V ECL 1:2 Differential Fanout Buffer
3.3V / 5V ECL 卤2/4, 卤4/5/6 Clock Generation Chip
3.3V / 5V ECL Differential Receiver/Driver with Internal Termination
3.3V ECL Programmable Delay Chip
3.3V / 5V ECL D Flip?Flop with Set and Reset
3.3V / 5V ECL 卤2 Divider
3.3V / 5V ECL 卤4 Divider
3.3 V/5 V 8-Bit CMOS/ECL/TTL Data Input Parallel/Serial Converter
3.3V / 5V ECL 6?Bit Differential Register with Master Reset
3.3V / 5V ECL D Flip?Flop with Reset and Differential Clock
3.3V / 5V ECL Dual Differential 2:1 Multiplexer
3.3V / 5V ECL Coaxial Cable Driver
?3.3V / ?5V Triple ECL Input to LVPECL/PECL Output Translator
3.3V LVTTL/LVCMOS to Differential LVPECL Translator
|
ONSEMI[ON Semiconductor]
|
| DM74AS157 DM74AS157M DM74AS157N DM74AS157SJX DM74A |
Quad 1 of 2 Line Data Selector/Multiplexer AS SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16
Quad 2-Line to 1-Line Data Selector/Multiplexer
|
FAIRCHILD SEMICONDUCTOR CORP
Fairchild Semiconductor, Corp.
FAIRCHILD[Fairchild Semiconductor]
|
| AD802 AD800 AD800-52BR AD800-45BQ AD802-155BR AD80 |
Clock Recovery and Data Retiming Phase-Locked Loop
Clock Recovery and Data Retiming Phase-Locked Loop PHASE LOCKED LOOP, PDSO20
Clock Recovery and Data Retiming Phase-Locked Loop(时钟恢复和重定时PLL)
AD800/AD802: Clock Recovery and Data Retiming Phase-Locked Loop Data Sheet (Rev. B. 12/93)
45 or 52 Mbps Clock and Data Recovery IC
|
Analog Devices, Inc.
|
| DM74ALS253 DM74ALS253M DM74ALS253N DM74ALS253MX |
3-STATE Dual 1 of 4 Line Data Selector/Multiplexer
From old datasheet system
3-STATE Dual 1-of-4 Line Data Selector/Multiplexer(1线数据选择多路复用器（三态输出）) 三态的1 - 4线数据选择多路（双41线数据选择多路复用器（三态输出）
|
FAIRCHILD[Fairchild Semiconductor]
Fairchild Semiconductor Corporation
Fairchild Semiconductor, Corp.
|
| MAX9320EUA-T MAX9320AEKA-T |
2.25 V to 3.8 V, 1:2 differential LVPECL/LVECL/HSTL clock and data driver
1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers 9320 SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
|
MAXIM - Dallas Semiconductor
Maxim Integrated Products, Inc.
|
| M13S2561616A-2S |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| M13L2561616A-2A |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| W9725G6JB25I |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
