| PART |
Description |
Maker |
| CY7C1163V18-400BZC |
18-Mbit QDR™-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 1M X 18 QDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| CY7C1543V18-300BZI CY7C1545V18-375BZI |
72-Mbit QDRII SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 4M X 18 QDR SRAM, 0.45 ns, PBGA165
72-Mbit QDRII SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 2M X 36 QDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| CY7C1543V18 CY7C1543V18-300BZC CY7C1543V18-300BZI |
72-Mbit QDR垄芒-II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
72-Mbit QDR?II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
|
Cypress Semiconductor
|
| CY7C1561V18-333BZC CY7C1561V18-333BZI CY7C1563V18 |
72-Mbit QDR垄芒-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
72-Mbit QDR?II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
|
Cypress Semiconductor
|
| CY7C1548V18-300BZC CY7C1548V18-300BZI CY7C1548V18- |
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 4M X 18 DDR SRAM, 0.45 ns, PBGA165
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) 8M X 8 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| HSDL-7001 |
IR 3/16 Encode/Decode IC
|
Agilent(Hewlett-Packard)
|
| HSDL-7000 |
IR 3/16 Encode/Decode IC
|
Agilent (Hewlett-Packard)
HP[Agilent(Hewlett-Packard)]
|
| AS7C513 AS7C513-12 AS7C513-12JC AS7C513-12TC AS7C3 |
Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85 32K X 16 STANDARD SRAM, 20 ns, PDSO44
Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85 5V/3.3V 32Kx6 CMOS SRAM
High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer with Address Latches 16-TSSOP -55 to 125
High Speed CMOS Logic 3-to-8 Line Decoder Demultiplexer with Address Latches 16-PDIP -55 to 125
|
Alliance Semiconductor ...
Alliance Semiconductor, Corp.
ALSC[Alliance Semiconductor Corporation]
|
| CAT64LC10ZJ CAT64LC10ZP CAT64LC10J-TE7 CAT64LC10J- |
18-Mbit QDR™-II SRAM 4-Word Burst Architecture
18-Mbit DDR-II SRAM 2-Word Burst Architecture
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
4-Mbit (256K x 18) Flow-Through Sync SRAM SPI串行EEPROM
SPI Serial EEPROM SPI串行EEPROM
|
Analog Devices, Inc.
|
| MCM69D618 MCM69D618TQ6 MCM69D618TQ6R MCM69D618TQ8 |
64K x 18 Bit Synchronous Dual I/O, Dual Address SRAM
From old datasheet system
|
Motorola, Inc.
|
| CY7C1170KV18-400BZXC |
18-Mbit DDR II SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency)
|
Cypress
|
| CY7C1143KV18-450BZC CY7C1145KV18-400BZXI CY7C1145K |
18-Mbit QDRII SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)
|
Cypress
|
