| PART |
Description |
Maker |
| K4D623238B-GQC |
512K x 32Bit x 4 Banks Double Data Rate Synchronous RAM wi Extended Data Out Data Sheet
|
Samsung Electronic
|
| HI-8684PST-10 HI-8683 HI-8683PJI HI-8683PJT HI-868 |
ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 8-BIT PARALLEL DATA
384 MCELL 3 VOLT ZERO POWER ISP CPLD - NOT RECOMMENDED for NEW DESIGN
(HI-8683 / HI-8684) ARINC INTERFACE DEVICE ARINC 429 & 561 SERIAL DATA TO 8-BIT PARALLEL DATA
ARINC INTERFACE DEVICE ARINC 429& 561 SERIAL DATA TO 8-BIT PARALLEL DATA
System component for interfacing incoming ARINC 429 signals to 8-bit parallel data
|
http://
HOLTIC[Holt Integrated Circuits]
HOLT INTEGRATED CIRCUITS INC
Holt Integrated Circuit...
|
| RC336DPEL RCV336DPEL RCV336DPELSP RCV336DPFL |
V.34 Data V.17 Fax, AudioSpan, Voice, Speakerphone, Modem Data Pump
|
ETC
|
| R2705E |
27.195MHz FSK Radio Data Receiver for Manchester Data Format
|
List of Unclassifed Manufacturers
|
| HI-8787 |
(HI-8787 / HI-8788) 16-BIT PARALLEL DATA CONVERTED 429&561 SERIAL DATA OUT
|
Holt Integrated Circuits
|
| HI-8783 |
(HI-8783 - HI-8785) 8 bit parallel data converted to 429 & 561 serial data out
|
Holt Integrated Circuits
|
| NT5DS4M32EG-5 NT5DS4M32EG-5G NT5DS4M32EG-6 |
1M × 32 Bits × 4 Banks Double Data Rate Synchronous RAM With Bi-Directional Data Strobe and DLL
|
NanoAmp Solutions, Inc.
|
| MX929BDS MX929B MX929BP MX929BDW |
DATA BULLETIN 4-Level FSK Modem Data Pump
|
CMLMICRO[CML Microcircuits]
|
| MC68HC908JB12 MC68HC908JB12DW MC68HC908JB12JDW MC6 |
Addendum to MC68HC908JB16 Technical Data
This section updates data sheet information and introduces the 20-pin SOIC
|
FREESCALE[Freescale Semiconductor, Inc]
|
| W9412G6JH W9412G6JH-5 |
2M ?4 BANKS ?16 BITS DDR SDRAM
Double Data Rate architecture; two data transfers per clock cycle
|
Winbond
|
| SDA006 SDA006-7 |
Data Line Protection
DATA BUS TRANSIENT SUPPRESSOR/3-PHASE FULL WAVE BRIDGE RECTIFIER
|
Dionics Inc.
DIODES[Diodes Incorporated]
|
| W9412G2IB W9412G2IB4 W9412G2IB-6I |
1M × 4 BANKS × 32 BITS GDDR SDRAM
Double Data Rate architecture; two data transfers per clock cycle
4M X 32 DDR DRAM, 0.7 ns, PBGA144
|
Winbond
WINBOND ELECTRONICS CORP
|
