| PART |
Description |
Maker |
| AAT3562IGY-320-T1 AAT3562IGY-420-T1 AAT3564IGY-420 |
Triple 3-input positive-AND gates 14-PDIP 0 to 70
CONNECTOR ACCESSORY
Triple 3-input positive-AND gates 14-SOIC 0 to 70
Triple 3-input positive-NAND gates 14-SOIC 0 to 70
Triple 3-input positive-NAND gates 14-PDIP 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC 0 to 70
Triple 3-input positive-NAND gates 14-SO 0 to 70
Triple 3-input positive-AND gates 14-SO 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset 16-PDIP 0 to 70
Dual J-K Flip-Flops With Clear 14-SO 0 to 70
NanoPower Voltage Detector NanoPower电压检测器
Dual J-K Flip-Flops With Clear 14-SOIC 0 to 70 NanoPower电压检测器
Dual J-K Flip-Flops With Clear 14-PDIP 0 to 70 NanoPower电压检测器
|
Advanced Analogic Technologies, Inc.
|
| HD74HC76 HD74HC76P |
FLIP-FLOP|DUAL|J/K TYPE|HC-CMOS|DIP|16PIN|PLASTIC
Dual J-K Flip-Flops (with Preset and Clear)
|
HITACHI[Hitachi Semiconductor]
|
| HCTS109HMSR HCTS109KMSR HCTS109K HCTS109D HCTS109D |
Dual Positive-Edge-Triggered D-Type- Flip-Flops With Clear And Preset 14-CDIP -55 to 125 辐射加固双JK触发器拖
Radiation Hardened Dual JK Flip Flop
From old datasheet system
|
Intersil, Corp.
INTERSIL[Intersil Corporation]
|
| 74LVX112M 74LVX112MTC 74LVX112 74LVX112SJX |
J-K-Type Flip-Flop
Low Voltage Dual J-K Flip-Flops with Preset and Clear
From old datasheet system
|
FAIRCHILD[Fairchild Semiconductor]
|
| HD74HC107 |
Dual J-K Flip-Flops (with Clear)
|
Hitachi Semiconductor
|
| HD74LS76 HD74LS76A 74LS76 |
Dual J-K Flip-Flop(with Preset and Clear)
Dual J-K Flip-Flops with Preset and Clear
|
Hitachi,Ltd.
HITACHI[Hitachi Semiconductor]
|
| HD74HC112 HD74HC112FPEL HD74HC112P |
Dual J-K Flip-Flops (with Preset and Clear)
|
Renesas Electronics Corporation
|
| HD74LV74A LV74 |
Dual D-type Flip Flops with Preset and Clear
|
Hitachi,Ltd.
Hitachi Semiconductor
|
| M27W201-80K6TR M27W201-200NZ6TR M27W201-80NZ6TR M2 |
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
Test Spring Probe; Current Rating:3A; Leaded Process Compatible:Yes; Length:0.060"; Peak Reflow Compatible (260 C):No; Tip/Nozzle Style:90 Concave RoHS Compliant: Yes 2兆位56Kb × 8低压紫外线可擦写可编程只读存储器和OTP存储
Triple 3-Input Positive-AND Gates 14-SO 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SO 0 to 70
Triple 3-Input Positive-AND Gates 14-PDIP 0 to 70
Triple 3-Input Positive-AND Gates 14-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-PDIP 0 to 70
2 Mbit 256Kb x 8 Low Voltage UV EPROM and OTP EPROM
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
|
STMicroelectronics N.V.
意法半导
STMICROELECTRONICS[STMicroelectronics]
ST Microelectronics
|
| DM7476 |
Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs
|
Fairchild Semiconductor
|
| HD74LV2G74A |
Single D-ype Flip Flops with Preset and Clear
Single D-type Flip Flops with Preset and Clear
|
HITACHI[Hitachi Semiconductor]
|
| 74ACT11112 |
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 具有清零和预设功能的双路 J-K 下降沿触发器
|
Linear Technology, Corp.
|
