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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16520
VERTICAL DRIVER FOR CCD SENSORS
The PD16520 is a vertical driver for CCD image sensors that has a level conversion circuit and a 3-level output function. Since it incorporates a CCD vertical register driver equivalent to the PD16510 (10 channels, consisting of six 3-level channels and four 2-level channels) and a VOD shutter driver (1 channel), it is ideal as a vertical driver for multiple-electrode high-pixel CCD transfer type area image sensors employed in digital still cameras. The PD16520 uses a CMOS process to achieve optimum transmission delay characteristics for vertical driving of CCD image sensors, as well as output on-state resistance characteristics. The PD16520 also supports low-voltage logic (logic supply voltage: 2.0 to 5.5 V).
FEATURES
* CCD vertical register driver: 10 channels (3-level: 6 channels, 2-level: 4 channels) * VOD shutter driver: 1 channel * High withstand voltage: 33 V Max. * Low-output on-state resistance: 30 TYP. * Low-voltage input supported (Logic supply voltage: 2.0 to 5.5 V) * Latch-up free * Same drive capacity as PD16510 * Small package: 38-pin plastic shrink SOP (300 mil)
APPLICATIONS
Digital still cameras, digital video cameras, etc.
ORDERING INFORMATION
Part Number Package 38-pin plastic shrink SOP (300 mil)
PD16520GS-BGG
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S14201EJ1V0DS00 (1st edition) Date Published May 1999 N CP(K) Printed in Japan
(c)
1999
PD16520
PIN CONFIGURATION (TOP VIEW)
* 38-pin plastic shrink SOP (300 mil)
PD16520GS-BGG
GND Vcc TI1 TI2 TI3 TI4 TI5 TI6 PG1 PG2 PG3 PG4 PG5 PG6 BI1 BI2 BI3 BI4 SUBI
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20
VSS VDD1
TO1 VDD2a TO2 TO3 VDD2a TO4 TO5 VDD2a TO6 BO1 BO2 VDD2b BO3 BO4 SUBO Vsb Vss
PIN NAMES
BI1 to BI4: BO1 to BO4: GND: PG1 to PG6: SUBI: SUBO: TI1 to TI6: 2 Level Driver Input 2 Level Pulse Output Ground 3 Level Driver Input VOD Shutter Drive Pulse Input VOD Shutter Drive Pulse Output 3 Level Driver Input TO1 to TO6: VDD1: VDD2a: VDD2b: VCC: Vsb: VSS: 3 Level Pulse Output Power Supply (VH) Power Supply (VMa) Power Supply (VMb) Power Supply (Logic) Power Supply (VHH) Power Supply (VL)
2
Data Sheet S14201EJ1V0DS00
PD16520
BLOCK DIAGRAM
GND 1
38 37
Vss VDD1
Vcc TI1 TI2 TI3 TI4 TI5 TI6
2 3 4 5 6 7
+ - + - + - + - + -
3 level
36 TO1
35 VDD2a
3 level
34
TO2
8
3 level
33 TO3 32 VDD2a
+ - + - + - + - + - + - + - + -
PG1 9 PG2 10 PG3 11 PG4 12 PG5 13 PG6 14
3 level
31 TO4
3 level
30 TO5 29
VDD2a
3 level
28 TO6
BI1
15
2 level
27 BO1
BI2
16
+ -
2 level
26 BO2
25
VDD2b
BI3
17
+ -
2 level
24 BO3
BI4 18
+ -
2 level
23 BO4
22 SUBO
SUBI 19
+ -
2 level
21 Vsb
20 Vss
Data Sheet S14201EJ1V0DS00
3
PD16520
1. PIN FUNCTIONS
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Pin Name GND VCC TI1 TI2 TI3 TI4 TI5 TI6 PG1 PG2 PG3 PG4 PG5 PG6 BI1 BI2 BI3 BI4 SUBI VSS Vsb SUBO BO4 BO3 VDD2b BO2 BO1 TO6 VDD2a TO5 TO4 VDD2a TO3 TO2 VDD2a TO1 VDD1 VSS I/O - - I I I I I I I I I I I I I I I I I - - O O O - O O O - O O - O O - O - - VMa power supply (for 3-level driver) 3-level pulse output VH power supply VL power supply VMa power supply (for 3-level driver) 3-level pulse output 3-level pulse output VMa power supply (for 3-level driver) 3-level pulse output VMb power supply (for 2-level driver) 2-level pulse output VOD shutter drive pulse input VL power supply VHH power supply (for SUB drive) VOD shutter drive pulse output 2-level pulse output 2-level driver input (for charge transfer) (See Function Tables.) 3-level driver input (for charge read) (See Function Tables.) Ground Logic power supply 3-level driver input (for charge transfer) (See Function Tables.) Function
4
Data Sheet S14201EJ1V0DS00
PD16520
Function Tables VL = VSS, VMa = VDD2a, VMb = VDD2b, VH = VDD1, VHH = Vsb Pins TO1 to TO6
Input Pin Name Pin No. TI1 3 TI2 4 TI3 5 L L H H TI4 6 TI5 7 TI6 8 PG1 9 PG2 10 PG3 11 L H L H PG4 12 PG5 13 PG6 14 36 34 Output TO1 TO2 TO3 TO4 TO5 TO6 33 VH VMa VL VL 31 30 28
Pins BO1 to BO4
Input Pin Name Pin No. BI1 15 BI2 16 L H BI3 17 BI4 18 BO1 27 26 VMb VL Output BO2 BO3 24 BO4 23
Pin SUBO
Input Pin Name Pin No. SUBI 19 L H Output SUBO 22 VHH VL
Data Sheet S14201EJ1V0DS00
5
PD16520
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C, GND = 0 V)
Parameter Supply voltage Symbol VSS VCC VDD1 VDD2 Vsb Input pin voltage Operating ambient temperature Storage temperature Allowable dissipation VI TA Tstg Pd Conditions Ratings 0.0 to -10 VSS - 0.3 to VSS + 20.0 VSS - 0.3 to VSS + 33.0 VSS - 0.3 to VSS + 33.0 VSS - 0.3 to VSS + 33.0 VSS - 0.3 to VCC + 0.3 -25 to +85 -40 to +125 500 Unit V V V V V V C C mW
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = 25C, GND = 0 V)
Parameter Supply voltage Symbol VCC VDD1 VDD1-VSS VDD2a VDD2b VSS Vsb-VSS Input voltage, high Input voltage, low Operating ambient temperature VIH VIL TA Note 0.8VCC 0 -20 Note Note Conditions MIN. 2.0 10.5 16.5 -1.0 -1.0 -10.0 15.0 TYP. MAX. 5.5 21.0 31.0 +4.0 +4.0 -6.0 31.0 VCC 0.3VCC +70 Unit V V V V V V V V V C
Note Set VDD1 and VSS to values that satisfy VDD1-VSS rating.
6
Data Sheet S14201EJ1V0DS00
PD16520
Electrical Specifications
(Unless otherwise specified, VDD1 = +15 V, VDD2a = 0 V, VDD2b = +1.0 V, Vsb = +21.5 V, VCC = +2.5 V, VSS =
-7.0 V, TA = 25C, GND = 0 V)
Parameter Output voltage, high Output voltage, middle Output voltage, low Output voltage, sub-high Output voltage, sub-low Output on-state resistance Symbol VH VMa VMb VL VsubH VsubL RL RM RH Rsub Transmission delay time 1 Transmission delay time 2 Transmission delay time 3 Rise/fall time 1 Rise/fall time 2 Rise/fall time 3 TD1 TD2 TD3 TP1 TP2 TP3 See Figure 2-1 Output Load Equivalence Circuit. See Figure 2-2 Timing Charts. No load See Figure 2-2 Timing Charts. Conditions IO = -20 A IO = -20 A IO = 20 A IO = 20 A IO = -20 A IO = 20 A IO = 10 mA IO = 10 mA IO = -10 mA MIN. VDD1 - 0.1 VDD2a - 0.1 VDD2b VSS Vsb - 0.1 VSS 20 30 30 30 TYP. MAX. VDD1 VDD2a VDD2b + 0.1 VSS + 0.1 Vsb VSS + 0.1 30 45 40 40 200 200 200 500 500 200 Unit V V V V V V ns ns ns ns ns ns
Data Sheet S14201EJ1V0DS00
7
PD16520
Figure 2-1. Output Load Equivalence Circuit (a) Between output pins
TO1
(b) Between output pin and GND
BO4 TO1
BO4
BO3
R10 BO4' R9 BO3'
R1 TO1' R2 TO2'
BO3
R10 BO4' R9 BO3' C9 C10
R1 TO2 TO1' R2 C1 C2 C3 TO3' R3 TO3 TO2'
TO2
BO2
BO2' R8 BO1' R7 TO6' TO5' R6 R5 TO4'
R3 TO3'
TO3
BO2 R8 BO2' C8 C7 BO1' C6 TO6' R6 RGND R7 BO1 C5
C4 TO4' R4
R4
TO5' R5 TO4
BO1
TO4
TO6 TO5
TO6
TO5
SUB0 C11
Output Load Capacitance Symbol
TO1' TO1' TO2' TO3' TO4' TO5' TO6' BO1' BO2' BO3' BO4' SUBO - C_33 C_33 C_33 C_33 C_33 C_32 C_23 C_32 C_23 - TO2' C_33 - C_33 C_33 C_33 C_33 C_23 C_32 C_23 C_32 - TO3' C_33 C_33 - C_33 C_33 C_33 C_32 C_23 C_32 C_23 - TO4' C_33 C_33 C_33 - C_33 C_33 C_23 C_32 C_23 C_32 - TO5' C_33 C_33 C_33 C_33 - C_33 C_32 C_23 C_32 C_23 - TO6' C_33 C_33 C_33 C_33 C_33 - C_23 C_32 C_23 C_32 - BO1' C_32 C_23 C_32 C_23 C_32 C_23 - C_22 C_22 C_22 - BO2' C_23 C_32 C_23 C_32 C_23 C_32 C_22 - C_22 C_22 - BO3' C_32 C_23 C_32 C_23 C_32 C_23 C_22 C_22 - C_22 - BO4' C_23 C_32 C_23 C_32 C_23 C_32 C_22 C_22 C_22 - - GND C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11
8
Data Sheet S14201EJ1V0DS00
PD16520
Output Load Equivalence Circuit Constants
Parameter Vertical register serial resistor Vertical register ground resistor Capacitance 1 between vertical register clocks (3 level-3 level) Capacitance 2 between vertical register clocks (2 level-2 level) Capacitance 3 between vertical register clocks (3 level-2 level) Capacitance 4 between vertical register clocks (2 level-3 level) Vertical register ground capacitance 1 (3 level) Vertical register ground capacitance 2 (2 level) Substrate ground capacitance Symbol R1 to R10 RGND C_33 C_22 C_32 C_23 C1 to C6 C7 to C10 C11 0 0 0 pF 0 pF 1000 pF 500 pF 3000 pF 1500 pF 1600 pF Constant
Figure 2-2. Timing Charts
BI1 to BI4 TI1 to TI6 TD1 TD1 VMb VMa BO1 to BO4 TO1 to TO6 VL TP1 TP1
PG1 to PG6
TD2
TD2 VH
TO1 to TO6 VMa TP2 TP2
SUBI
TD3
TD3 VHH
SUBO VL TP3 TP3
Data Sheet S14201EJ1V0DS00
9
PD16520
3. CAUTIONS
3.1 Power ON/OFF Sequence In the PD16520, a PN junction (diode) exists between VDD2 VDD1, input pin (TI1 to TI6, PG1 to PG6, BI1 to BI4, SUBI) VCC, so that in the case of voltage conditions: VDD2 > VDD1, input pin voltage (TI1 to TI6, PG1 to PG6, BI1 to BI4, SUBI) > VCC, an abnormal current flows. Therefore, when turning the power ON/OFF, make sure that the following voltage conditions are satisfied: VDD2 VDD1, input pin voltage (TI1 to TI6, PG1 to PG6, BI1 to BI4, SUBI) VCC. Also, to minimize the negative potential applied to the SUB pin of the CCD image sensor, following the power ON/OFF sequence described below. (1) Power ON <1> Powering ON VCC Make sure that input pin voltage (TI1 to TI6, PG1 to PG6, BI1 to BI4, SUBI) VCC. Also, when Vsb = 2 V, make sure that VCC reaches the rated voltage. <2> Powering ON Vsb, VDD1, VDD2a, VDD2b, VSS At this time, make SUBI high level (0.8VCC or higher).
Vsb VDD1
2V <1> <2>
Vcc VDD2a, VDD2b 0V
Vss Time
10
Data Sheet S14201EJ1V0DS00
PD16520
(2) Power OFF <1> Powering OFF Vsb, VDD1, VDD2a, VDD2b, VSS Until VCC power OFF, keep SUBI high level (0.8VCC or higher). <2> Powering OFF VCC Power OFF VCC when Vsb becomes 2 V or lower. At this time, make sure that the input pin voltage (TI1 to TI6, PG1 to PG6, BI1 to BI4, SUBI) VCC.
<1> Vsb VDD1
<2> Vcc VDD2a, VDD2b 2V 0V
Vss Time
3.2. Recommended Connection of Unused Pins Handle input pins and output pins that are not used as follows. Input pin: High level (connect to VCC)
Output pin: Leave open
Data Sheet S14201EJ1V0DS00
11
12
VSS Vsb VDD2b VSUB (Substrate voltage) VDD1
VCC
PD16520GS-BGG
GND VCC TI1 TI2 TI3 TI4 TI5 TI6 1 2 3 4 5 6 7 8 9
CCD
4. APPLICATION CIRCUIT EXAMPLE
TG/SSG
Data Sheet S14201EJ1V0DS00
+
1F
PG1 10 PG2 11 PG3 12 PG4 13 PG5 14 PG6 15 BI1 16 BI2 17 BI3 18 BI4 19 SUBI
38 VSS 37 VDD1 36 TO1 35 VDD2a 34 TO2 33 TO3 32 VDD2a 31 TO4 30 TO5 29 VDD2a 28 TO6 27 BO1 26 BO2 25 VDD2b 24 BO3 23 BO4 22 SUBO 21 Vsb 20 VSS
1M
0.1F
0.1F
0.1F
0.1F
0.1F
0.1F
PD16520
PD16520
5. PACKAGE DRAWING
38-PIN PLASTIC SSOP (300 mil)
38 20 detail of lead end F G
1 A
19 E
P
L
H I S J
C D M
M
N
S
B K
NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D E F G H I J K L M N P
MILLIMETERS 12.70.3 0.65 MAX. 0.65 (T.P.) 0.37+0.05 -0.1 0.1250.075 1.6750.125 1.55 7.70.2 5.60.2 1.050.2 0.2 +0.1 -0.05 0.60.2 0.10 0.10 3+7 -3 P38GS-65-BGG
Data Sheet S14201EJ1V0DS00
13
PD16520
6. RECOMMENDED SOLDERING CONDITIONS
The PD16520 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 6-1. Surface Mounting Type Soldering Conditions * PD16520GS-BGG: 38-pin plastic shrink SOP (300 mil)
Soldering Method Infrared reflow VPS Wave soldering Partial heating Soldering Conditions Package peak temperature: 235C, Time: 30 sec. Max. (at 210C or higher), Count: Three times or less Package peak temperature: 215C, Time: 40 sec. Max. (at 200C or higher), Count: Three times or less Solder bath temperature: 260C, Time: 10 sec. Max., Count: Once, Preheating temperature: 120C Max. (package surface temperature) Pin temperature: 300C Max., Time: 3 sec. Max. (per pin row) Recommended Condition Symbol IR35-00-3 VP15-00-3 WS60-00-1 -
Caution
Do not use different soldering methods together (except for partial heating).
14
Data Sheet S14201EJ1V0DS00
PD16520
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S14201EJ1V0DS00
15
PD16520
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98. 8

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