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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16634A
300-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64 GRAY SCALE)
DESCRIPTION
The PD16634A is a source driver for TFT-LCDs capable of dealing with displays 64 gray scales. Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values -corrected by an internal D/A converter and 5-by-2 external power modules. Because the 5 output dynamic range is as large as VSS2+0.1 V to VDD2-0.1 V, level inversion operation of the LCD's common electrode is rendered unnecessary. Also to be able to deal with dot-line inversion when mounted on a single side, this source driver equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a maximum clock frequent of 40 MHz when drivng at 3.0 V, this driver is applicable to XGA-standard TFT-LCD panels.
FEATURES
* 300 outputs * CMOS level input * Input of 6 bits (gradation data) by 6 dots * Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter 5 5 5 * Output dynamic range : VSS2+0.1 V to VDD2-0.1 V * Logic part supply voltage (VDD1) : 3.3 V 0.3 V * Driver part supply voltage (VDD2) : 8.0 V 0.5 V * High-speed data transfer: fMAX=40 MHz MIN.(internal data transfer rate when operating at 3.0 V) * Output voltage polarity inversion is possible (POL) * Display data inversion function (POL2) * Single bank arrangement is possible(loaded with slim TCP).
ORDERING INFORMATION
Part Number Package TCP (TAB package)
PD16634AN-xxx
Remark
The TCP's external shape is customized. To order your TCP's external shape, please contact a NEC salesperson.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S12595EJ2V0DS00 (2nd edition) Date Published March 1999 NS CP (K) Printed in Japan
The mark * shows major revised points.
(c)
1998
PD16634A
1. BLOCK DIAGRAM
STHR R,/L CLK STB STHL VDD1 VSS1 C49 C50
50-bit bidirectional shift register C1 C2
D00 - D05 D10 - D15 D20 - D25 D30 - D35 D40 - D45 D50 - D55 POL2
Data register
POL
Latch
VDD2 Level shifter VSS2
V0 - V9
D/A converter
Voltage follower output
S1
S2
S3
S300
Remark
/xxx indicates active low signal.
2
Data Sheet S12595EJ2V0DS00
PD16634A
5
2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S1 S2 S299 S300
V4 V5 V9
*****
V0 Multiplexer
5
6-bit D/A converter 5
*****
POL
Data Sheet S12595EJ2V0DS00
3
PD16634A
3. PIN CONFIGURATION (PD16634AN-xxx)
VSS2 VDD2 VSS1 R,/L POL STB D55 D54 D53 D52 D51 D50 D45 D44 D43 D42 D41 D40 D35 D34 D33 D32 D31 STHL V9 V8 V7 V6 V5 V4 V3 V2 V1 V0 CLK STHR D30 D25 D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 POL2 TEST VDD1 VDD2 VSS2
S300 S299 S298 S297
(Copper Plated Surface)
S4 S3 S2 S1
Caution
This figure does not specify the TCP package. Therefore POL2 pins can be reduced by opening or short-circuiting to VSS2 by TCP wiring. POL2 pin can short to VSS1 on TCP. So when you not use "data inversion function", can reduce input pins.
4
Data Sheet S12595EJ2V0DS00
PD16634A
4. PIN FUNCTIONS
Pin Symbol S1 to S300 D00 to D05 D10 to D15 D20 to D25 D30 to D35 D40 to D45 D50 to D55 R,/L Shift direction switching input These refer to the start pulse input/output pins when cascades are connected. The shift directions of the shift registers are as follows. R,/L = H : STHR input, S1S300, STHL output R,/L = L : STHL input, S300S1, STHR output R,/L = H : Becomes the start pulse input pin. R,/L = L : Becomes the start pulse output pin. R,/L = H : Becomes the start pulse input pin. R,/L = L : Becomes the start pulse output pin. Refers to the shift register's shift clock input. The display data is incorporated into the data register at the rising edge. At the rising edge of the 50th clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. The initiallevel driver's 50th clock becomes valid as the next-level driver's start pulse is input. If 52 clock pulses are input after input of the start pulse, input of display data is halted automatically. The contents of the shift register are cleared at the STB's rising edge. The contents of the data register are transferred to the latch at the rising edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure input of one pulse per horizontal period. POL = L ; The S2n-1 output uses V0 to V4 as the reference supply; and the S2n output uses V5 to V9 as the reference supply. POL = H ; The S2n-1 output uses V5 to V9 as the reference supply; and the S2n output uses V0 to V4 as the reference supply. S2n-1 indicates the odd output; and S2n indicates the even output. Input of the POL signal is allowed the setup time (tPOL-STB) with respect to STB's rising edge. POL2 = H : Display data is inverted. POL2 = L : Display data is not inverted. Input the -corrected power supplies from outside by using operational amplifier. Make sure to maintain the following relationships. During the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. VDD2 > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > V8 > V9 > VSS2 Set it to open. 3.3 V 0.3 V 8.0 V 0.5 V Grounding Grounding Pin Name Driver output Display data input Description The D/A converted 64-gray-scale analog voltage is output The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). DX0 : LSB, DX5 : MSB
STHR STHL CLK
Right shift start pulse input/output Left shift start pulse input/output Shift clock input
STB
Latch input
POL
Polarity input
POL2 V0 to V9
Data inversion input
-corrected power supplies
TEST VDD1 VDD2 VSS1 VSS2
Test pin Logic circuit power supply Driver circuit power supply Logic ground Driver ground
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order. Reverse this sequence to shut down.(Simultaneous power application to VDD2 and V0 to V9 is possible.) 2. To stabilize the supply voltage, please be sure to insert 0.1 F bypass capacitor between VDD1-VSS1 and VDD2-VSS2. Furthermore, for increase precision of the D/A converter, insertion of a bypass capacitor of about 0.01 F is also advised between the -corrected power supply terminals(V0,V1,V2...,V9) and VSS2. 3. We recommend to use Operational Amplifier to lower input impedance of -corrected voltage.
Data Sheet S12595EJ2V0DS00
5
PD16634A
5. RELATIONHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
This product incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the LCD's counter electrode (common electrode) voltage. The D/A converter consists of ladder resistors and switches. The ladder resistors r0 to r62 are so designed that the ratios between the LCD panel's -corrected voltages and V0' to V63', V0" to V63" are roughly equal; and their respective resistance values are as shown in Table 6-1. Among the 5-by 2 -corrected voltages, input gray scale voltages of the same polarity with respect to the common voltage, for the respective five -corrected voltages of V0 to V4 and V5 to V9. If fine gray scale voltage precision is not necessary, the voltage follower circuit supplied to the -corrected power supplies V1 to V3 and V6 to V8 can be deleted. Figure 5-1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and VSS2, common electrode potential VCOM, and -corrected voltages V0 to V9 and the input data. Be sure to maintain the voltage relationships of VDD2 > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > V8 > V9 > VSS2. Figure 6-1 and 6-2 show the relationship between the input data and the output data. This driver IC is designed for single-sided mounting. Therefore, please do not use it for -corrected power supply level inversion in double-sided mounting. 5
VDD2 V0 16 V1 V2 V3 16 16
Figure 5-1. Relationship between Input Data and Output Voltage
Split interval
15 V4 VCOM V5 15 V6 16 V7 16 V8 16 V9 VSS2 00 08 10 18 20 28 30 38 3F Input data (HEX)
6
Data Sheet S12595EJ2V0DS00
PD16634A
6. RESISTOR STRINGS
Figure 6-1. Relationship Between Input Data and Output Voltage : VDD2 > V0 > V1 > V2 > V3 > V4 > V5, POL2 = L
Data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 V0' V1' V2' V3' V4' V5' V6' V7' V8' V9' V10' V11' V12' V13' V14' V15' V16' V17' V18' V19' V20' V21' V22' V23' V24' V25' V26' V27' V28' V29' V30' V31' V32' V33' V34' V35' V36' V37' V38' V39' V40' V41' V42' V43' V44' V45' V46' V47' V48' V49' V50' V51' V52' V53' V54' V55' V56' V57' V58' V59' V60' V61' V62' V63' Output Voltage V0 V1 + (V0 - V1) x V1 + (V0 - V1) x V1 + (V0 - V1) x V1 + (V0 - V1) x V1 + (V0 - V1) x V1 + (V0 - V1) x V1 + (V0 - V1) x V1 + (V0 - V1) x V1 + (V0 - V1) x V1 + (V0 - V1) x V1 + (V0 - V1) x V1 + (V0 - V1) x V1 + (V0 - V1) x V1 + (V0 - V1) x V1 + (V0 - V1) x V1 V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 + (V1 - V2) x V2 V3 + (V2 - V3) x V3 + (V2 - V3) x V3 + (V2 - V3) x V3 + (V2 - V3) x V3 + (V2 - V3) x V3 + (V2 - V3) x V3 + (V2 - V3) x V3 + (V2 - V3) x V3 + (V2 - V3) x V3 + (V2 - V3) x V3 + (V2 - V3) x V3 + (V2 - V3) x V3 + (V2 - V3) x V3 + (V2 - V3) x V3 + (V2 - V3) x V3 V4 + (V3 - V4) x V4 + (V3 - V4) x V4 + (V3 - V4) x V4 + (V3 - V4) x V4 + (V3 - V4) x V4 + (V3 - V4) x V4 + (V3 - V4) x V4 + (V3 - V4) x V4 + (V3 - V4) x V4 + (V3 - V4) x V4 + (V3 - V4) x V4 + (V3 - V4) x V4 + (V3 - V4) x V4 + (V3 - V4) x V4 7250/8050 6500/8050 5800/8050 5150/8050 4550/8050 4000/8050 3450/8050 2950/8050 2450/8050 2050/8050 1650/8050 1300/8050 950/8050 600/8050 300/8050 2450/2750 2200/2750 1950/2750 1700/2750 1500/2750 1300/2750 1100/2750 950/2750 800/2750 650/2750 500/2750 400/2750 300/2750 200/2750 100/2750 1500/1600 1400/1600 1300/1600 1200/1600 1100/1600 1000/1600 900/1600 800/1600 700/1600 600/1600 500/1600 400/1600 300/1600 200/1600 100/1600 3350/3450 3250/3450 3150/3450 3050/3450 2950/3450 2800/3450 2650/3450 2500/3450 2300/3450 2100/3450 1850/3450 1600/3450 1300/3450 800/3450
V0 r0 r1
V0' V1' V2' r2 V3' r3
r14 V15' r15 V1 r16 V17' r17 V16'
r30 V31' r31 V2 r32 V33' r33 V32'
r46 V47' r47 V3 r48 V49' r49 V48'
r60 V61' r61 V62' r62 V4 V63'
V5 r62
V63'' V62''
Data Sheet S12595EJ2V0DS00
7
PD16634A
Figure 6-2. Relationship Between Input Data and Output Voltage : V4 > V5 > V6 > V7 > V8 > V9 > VSS2, POL2 = L
Data r62 V4 V5 r62 V62'' r61 V61'' r60 V62' V63' 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 V0'' V1'' V2'' V3'' V4'' V5'' V6'' V7'' V8'' V9'' V10'' V11'' V12'' V13'' V14'' V15'' V16'' V17'' V18'' V19'' V20'' V21'' V22'' V23'' V24'' V25'' V26'' V27'' V28'' V29'' V30'' V31'' V32'' V33'' V34'' V35'' V36'' V37'' V38'' V39'' V40'' V41'' V42'' V43'' V44'' V45'' V46'' V47'' V48'' V49'' V50'' V51'' V52'' V53'' V54'' V55'' V56'' V57'' V58'' V59'' V60'' V61'' V62'' V63'' Output Voltage V9 V9 + (V8 - V9) V9 + (V8 - V9) V9 + (V8 - V9) V9 + (V8 - V9) V9 + (V8 - V9) V9 + (V8 - V9) V9 + (V8 - V9) V9 + (V8 - V9) V9 + (V8 - V9) V9 + (V8 - V9) V9 + (V8 - V9) V9 + (V8 - V9) V9 + (V8 - V9) V9 + (V8 - V9) V9 + (V8 - V9) V8 V8 + (V7 - V8) V8 + (V7 - V8) V8 + (V7 - V8) V8 + (V7 - V8) V8 + (V7 - V8) V8 + (V7 - V8) V8 + (V7 - V8) V8 + (V7 - V8) V8 + (V7 - V8) V8 + (V7 - V8) V8 + (V7 - V8) V8 + (V7 - V8) V8 + (V7 - V8) V8 + (V7 - V8) V8 + (V7 - V8) V7 V7 + (V6 - V7) V7 + (V6 - V7) V7 + (V6 - V7) V7 + (V6 - V7) V7 + (V6 - V7) V7 + (V6 - V7) V7 + (V6 - V7) V7 + (V6 - V7) V7 + (V6 - V7) V7 + (V6 - V7) V7 + (V6 - V7) V7 + (V6 - V7) V7 + (V6 - V7) V7 + (V6 - V7) V7 + (V6 - V7) V6 V6 + (V5 - V6) V6 + (V5 - V6) V6 + (V5 - V6) V6 + (V5 - V6) V6 + (V5 - V6) V6 + (V5 - V6) V6 + (V5 - V6) V6 + (V5 - V6) V6 + (V5 - V6) V6 + (V5 - V6) V6 + (V5 - V6) V6 + (V5 - V6) V6 + (V5 - V6) V6 + (V5 - V6) V5 x 800/8050 x 1550/8050 x 2250/8050 x 2900/8050 x 3500/8050 x 4050/8050 x 4600/8050 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 5100/8050 5600/8050 6000/8050 6400/8050 6750/8050 7100/8050 7450/8050 7750/8050 300/2750 550/2750 800/2750 1050/2750 1250/2750 1450/2750 1650/2750 1800/2750 1950/2750 2100/2750 2250/2750 2350/2750 2450/2750 2550/2750 2650/2750 100/1600 200/1600 300/1600 400/1600 500/1600 600/1600 700/1600 800/1600 900/1600 1000/1600 1100/1600 1200/1600 1300/1600 1400/1600 1500/1600 100/3450 200/3450 300/3450 400/3450 500/3450 650/3450 800/3450 950/3450 1150/3450 1350/3450 1600/3450 1850/3450 2150/3450 2650/3450
V63''
r49 V49'' r48 V6 r47 V47'' r46 V48''
r33 V33'' r32 V7 r31 V31'' r30 V32''
r17 V17'' r16 V8 r15 V15'' r14 V16''
r3 V3'' r2 V2'' r1 V1'' r0 V9 V0''
8
Data Sheet S12595EJ2V0DS00
PD16634A
Table 6-1. Ladder Resistance Values (r0 to r62) : Reference Value
Resistor Name V0, V9 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 V1, V8 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 V2, V7 r31 Resistance Value () 800 750 700 650 600 550 550 500 500 400 400 350 350 350 300 300 300 250 250 250 200 200 200 150 150 150 150 100 100 100 100 100 Resistor Name r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r47 r48 r49 r50 r51 r52 r53 r54 r55 r56 r57 r58 r59 r60 r61 r62 Total Resistance Value () 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 150 150 150 200 200 250 250 300 500 800 15850 V4, V5 V3, V6 V2, V7
Data Sheet S12595EJ2V0DS00
9
PD16634A
7. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN
Data format : 6 bits x 2 RGBs (6 dots) Input width : 36 bits (2-pixel data) (1) R,/L = H (right shift)
Output Data S1 D00 to D05 S2 D10 to D15 S3 D20 to D25 S4 D30 to D35 S5 D40 to D45 ... ... S299 D40 to D45 S300 D50 to D55
(2) R,/L = L (left shift)
Output Data S1 D00 to D05 S2 D10 to D15 S3 D20 to D25 S4 D30 to D35 S5 D40 to D45 ... ... S299 D40 to D45 S300 D50 to D55
POL L H
S2n-1 V0 to V4 V5 to V9
S2n V5 to V9 V0 to V4
Remark
S2n-1 (Odd output), S2n (Even output)n = 1,2,.......,150
8. RELATIONSHIP BETWEEN STB, POL, AND OUTPUT WAVEFORM
The output voltage is written to the LCD panel synchronized with the STB falling edge.
STB
POL
S2n-1
Selected voltage of V0 to V4
Selected voltage of V5 to V9
Selected voltage of V0 to V4
S2n
Selected voltage of V5 to V9 Hi-Z Hi-Z
Selected voltage of V0 to V4 Hi-Z
Selected voltage of V5 to V9
10
Data Sheet S12595EJ2V0DS00
PD16634A
9. CAUTIONS ABOUT FRAME INVERSION
In the case of dot inversion, n frame last line and (n+1) frame first line is the same polarity. When write the same polarity twice; there are two cases as follows. (1) Last line output in n frame > First line output in (n+1) frame Positive to write (2) Last line output in n frame < First line output in (n+1) frame Not possible to write
PD16634A has charge buffer and discharge buffer, so need to inversion polarity and write in the case of both
ways.
Vertical intervals STB n frame last line (n+1) frame first line (n+1) frame second line Charge buffer POL Discharge buffer
S2N
VCOM
Hi-Z
Hi-Z
Hi-Z
Vertical intervals STB n frame last line (n+1) frame first line (n+1) frame second line
POL
S2N
VCOM
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Data Sheet S12595EJ2V0DS00
11
PD16634A
10. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 C,VSS1 = VSS2 = 0 V)
Parameter Logic part supply voltage Driver part supply voltage Logic part input voltage Driver part input voltage Logic part output voltage Driver part output voltage Operating ambient temperature Storage temperature Symbol VDD1 VDD2 VI1 VI2 VO1 VO2 TA Tstg Ratings -0.5 to +5.0 -0.5 to +10.0 -0.5 to VDD1 + 0.5 -0.5 to VDD2 + 0.5 -0.5 to VDD1 + 0.5 -0.5 to VDD2 + 0.5 -10 to +75 -55 to +125 Unit V V V V V V C C
5
Caution
If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings.
Recommended Operating Range (TA = -10 to +75 C, VSS1 = VSS2 = 0 V)
Parameter Logic part supply voltage Driver part supply voltage High-level input voltage Low-level input voltage -corrected supply voltage Driver part output voltage Maximum clock frequency Symbol VDD1 VDD2 VIH VIL V0 to V9 VO fMAX. MIN. 3.0 7.5 0.7VDD1 0 VSS2 VSS2 + 0.1 40 TYP. 3.3 8.0 MAX. 3.6 8.5 VDD1 0.3VDD1 VDD2 VDD2 - 0.1 Unit V V V V V V MHz
12
Data Sheet S12595EJ2V0DS00
PD16634A
Electrical Characteristics (TA = -10 to +75 C, VDD1 = 3.3 V 0.3 V, VDD2 = 8.0 V 0.5 V, VSS1 = VSS2 = 0 V)
Parameter Input leakage current High-level output voltage Low-level output voltage Symbol IIL VOH VOL I IVOH IVOL Output voltage deviation
Note2 Note3
Condition
MIN.
TYP.
MAX. 1.0
Unit
A
V
STHR(STHL),IO=0 mA STHR(STHL),IO=0 mA V0-V9 = 8 V VX=7 V, VOUT=1 V VX=1 V, VOUT=7 V V0,V9
Note1 Note1
VDD1-0.1 0.1 0.3 0.6 -0.5 0.5 5 10 0.1 0.5 VDD2-0.1 3.5 20
V mA mA mA mV mV V mA
-corrected supply current
Driver output current
VO VAV
VO IDD1
Input data : 00H to 3FH Input data : 00H to 3FH Input data : 00H to 3FH VDD1, when with no load
Average output voltage variation Output voltage range Logic part dynamic current consumptionNotes4,5
5
Driver part dynamic current consumption
Notes4,5
IDD2
VDD2, when with no load
2.2
8.0
mA
Notes 1. VX refers to the output voltage of analog output pins S1 to S300. VOUT refers to the voltage applied to analog output pins S1 to S300. 2. The output voltage deviation refers to the voltage difference between adjoining output pins when the display data is the same (within the chip). 3. The average output voltage variation refers to the average output voltage difference between chips. The average output voltage refers to the average voltage between chips when the display data is the same. 4. The STB cycle is defined to be 20 s at fCLK = 40 MHz. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern. 5. Refers to the current consumption per driver when cascades are connected under the assumption of SVGA single-sided mounting (10 units). Switching Characteristics (TA = -10 to +75 C, VDD1 = 3.3 V 0.3 V, VDD2 = 8.0 V 0.5 V, VSS1 = VSS2 = 0 V)
Parameter Start pulse delay time Driver output delay time Symbol tPLH1 tPHL2 tPHL3 tPLH2 tPLH3 Input capacitance C1 C2 STHR,STHL excluded, TA = 25 C CL = 25 pF CL = 125 pF, RL = 4 k
Note
Condition
MIN.
TYP. 13 3.7 5.3 3.0 5.3 5.4 7.6
MAX. 20 8 14 8 14 15 15
Unit ns
s s s s
pF pF
Note Load condition
RL output CL
RL
RL
RL
RL = 1k CL = 25pF CL
CL
CL
CL
Data Sheet S12595EJ2V0DS00
13
PD16634A
Timing Requirements (TA = -10 to +75 C, VDD1 = 3.3 V 0.3 V, VSS1 = VSS2 = 0 V, tr = tf = 8.0 ns)
Parameter Clock pulse width Clock pulse low period Clock pulse high period Data setup time Data hold time Start pulse setup time Start pulse hold time Start pulse low period POL2 setup time POL2 hold time STB pulse width Data invalid period Final data timing Symbol PWCLK PWCLK (L) PWCLK (H) tSETUP1 tHOLD1 tSETUP2 tHOLD2 tSPL tSETUP3 tHOLD3 PWSTB tINV tLDT tCLK-STB tSTB-CLK CLKSTB STB CLK STB CLK POLor STB STB POL or Condition MIN. 25 6 6 6 6 5 5 6 6 6 1 1 2 6 6 60 -5 6 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns
s
CLK CLK ns ns ns ns ns
5 5
CLK-STB time STB-CLK time
Time between STB and start pulse tSTB-STH POL-STB time STB-POL time tPOL-STB tSTB-POL
14
Data Sheet S12595EJ2V0DS00
5
11. SWITCHING CHARACTERISTIC WAVEFORM(R,/L= H)
Unless otherwise specified, the input level is defined to be 0.5 VDD1.
PWCLK(L)
PWCLK 2
PWCLK(H) 3 90% 50 51 52 1025 1026 tCLK-STB tSTB-CLK tSPL 1 2
tr
tf VDD1
CLK
1 tSETUP2 tHOLD2
10%
VSS1
STHR (1st Dr.) tSETUP1 tHOLD1 D289 to D294 D295 to D300 D301 to D306 D3067 to D3072 tSTB-STH
VDD1 VSS1
VDD1 Dn0 to Dn5 INVALID D1 to D6 D7 to D12 tSETUP3 tHOLD3 VDD1 POL2 INVALID tPLH1 STHL (1st Dr.) tINV PWSTB VDD1 STB tPOL-STB tSTB-POL VDD1 POL VSS1 tPLH3 Hi-Z tPLH2 VSS1 VDD1 VSS1 tLDT INVALID VSS1 INVALID D1 to D6 D7 to D12 VSS1
Data Sheet S12595EJ2V0DS00
Target Voltage 0.1VDD2 VOUT 6-bit accuracy
PD16634A
tPHL2 tPHL3
15
PD16634A
12. RECOMMENDED MOUNTING CONDITIONS
The following conditions must be met for mounting conditions of the PD16634A. For more details, refer to the Semiconductor Device Mounting Technology Manual(C10535E). Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions.
PD16634AN-xxx : TCP(TAB Package)
Mounting Condition Thermocompression Mounting Method Soldering Condition Heating tool 300 to 350 C, heating for 2 to 3 sec ; pressure 100g(per solder) ACF (Adhesive Conductive Film) Temporary bonding 70 to 100 C ; pressure 3 to 8 kg/cm ; time 3 to 5
2
sec. Real bonding 165 to 180 C pressure 25 to 45 kg/cm time 30 to
2
40secs(When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite,Ltd).
Caution
To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more mounting methods at a time.
16
Data Sheet S12595EJ2V0DS00
PD16634A
[MEMO]
Data Sheet S12595EJ2V0DS00
17
PD16634A
[MEMO]
18
Data Sheet S12595EJ2V0DS00
PD16634A
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S12595EJ2V0DS00
19
PD16634A
Reference Documents NEC Semiconductor Device Reliability/Quality Control System(C10983E) Quality Grades to NEC's Semiconductor Devices(C11531E)
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98. 8

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