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DATA SHEET
MOS INTEGRATED CIRCUIT
PD98409
ATM LIGHT SAR CONTROLLER
DESCRIPTION
The PD98409 (NEASCOT-S40CTM) is a high-performance SAR chip for segmentation and reassembly of ATM cells. Provided with a PCI (Peripheral Component Interconnect) bus interface control memory and supporting a MPEG packet transfer engine function to mitigate the workload of the CPU in transferring compressed image data, this chip has ideal specifications for use in a set top box (STB) to interface with an ATM network. The PD98409 conforms to ATM Forum recommendations and has AAL5-SAR sublayer and ATM layer functions.
FEATURES
* Conforms to ATM Forum * PCI bus interface (5/3.3 V, 32/64 bits, 33 MHz) Conforms to PCI Local Bus Specification Revision 2.1 * AAL-5 SAR sublayer and ATM layer functions * Hardware support of AAL-5 processing (non-AAL-5 processing can be supported in software) * Supports up to 64 virtual channels (VC) (64-VC control memory) * Two traffic shapers for transmission scheduling * MPEG packet transfer engine mitigating the workload of compressed image data transfer by CPU * Receive FIFO of 12 cells * PHY device I/F: UTOPIA Level-1 interface (octet/cell level handshake) * JTAG boundary scan test functions * 0.35-m CMOS process, +5/+3.3-V power supply - Bus interface +5 V : +5/+3.3-V power supply - Bus interface +3.3 V : +3.3-V single power supply
ORDERING INFORMATION
Part Number Package 240-pin plastic QFP (0.5-mm fine pitch) (32 x 32 mm)
PD98409GN-LMU
The information in this document is subject to change without notice.
Document No. S12775EJ2V0DS00 (2nd edition) Date Published May 1998 N CP(K) Printed in Japan
The mark
shows major revised points.
(c) 1997, 1998
PD98409
EXAMPLE OF SYSTEM CONFIGURATION
ATM STB
PCI bus
Line interface
PD98409
MPEG decoder block
Memory
CPU
BLOCK DIAGRAM
Receive data FIFO (12 cells) MPEG packet transfer engine Receive PHY interface Receive controller Rx UTOPIA interface
PCI interface
PCI interface block
DMA controller
Sequencer
Control memory interface
Control memory (64 VCs) PHY control interface
Transmit controller Transmit PHY interface Transmit data FIFO (2 cells) Tx UTOPIA interface
2
PD98409
PIN CONFIGURATION (Top View) * 240-pin plastic QFP (0.5-mm fine pitch) (32 x 32 mm)
VDD3 AD30 AD31 VDD5 GND RST_B VDD5 GND RSTOUT_B IC IC IC GND IC IC PHYSEL1 IC GND NC GND VDD3 JRST_B JMS JDO JDI GND JCK GND IC IC IC IC IC GND VDD3 IC IC IC IC VDD3 GND IC L L GND PO0 PO1 PO2 PO3 GND VDD3 LASTB LA0 LA1 GND LA2 LA3 LA4 LA5 VDD3
NC : No connection. Leave this pin open. IC : Input pin with pull-down resistor for internal test. It is recommended to fix this pin to the low level. L : Fix this pin to the low level.
VDD3 AD4 AD3 AD2 AD1 GND VDD5 AD0 REQ_B GND GNT_B GND BUSCLK GND INTR_B VDD5 GND GND E2PCLK GND VDD3 E2PDO E2PDI E2PCS GND IC IC IC IC GND VDD3 IC IC IC IC GND IC GND IC VDD3 GND IC IC IC IC IC IC IC IC GND IC GND IC IC IC RX7 RX6 RX5 RX4 VDD3
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
GND GND AD29 AD28 AD27 AD26 GND VDD5 AD25 AD24 PCBE3_B GND IDSEL VDD5 GND AD23 AD22 AD21 AD20 GND VDD3 AD19 AD18 AD17 AD16 GND PCBE2_B FRAME_B IRDY_B TRDY_B GND VDD5 DEVSEL_B STOP_B PERR_B GND SERR_B PAR PCBE1_B VDD3 GND AD15 AD14 AD13 AD12 GND VDD5 AD11 AD10 AD9 AD8 VDD5 GND PCBE0_B AD7 AD6 AD5 VDD5 GND GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181
180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
GND GND CA8 CA7 CA6 CA5 GND CA4 CA3 CA2 CA1 VDD3 GND CA0 PHCE_B PHOE_B CD0 CD1 CD2 GND VDD3 CD3 CD4 CD5 GND CD6 CD7 PHRW_B PHINT_B VDD3 GND TX0 TX1 TX2 TX3 GND TX4 TX5 TX6 TX7 VDD3 GND TCLK GND TENBL_B TSOC FULL_B/TXCLAV RSOC RENBL_B EMPTY_B/RXCLAV VDD3 GND RCLK GND RX0 RX1 RX2 RX3 GND GND
PD98409GN-LMU
3
PD98409
PIN NAMES AD31_AD0 BUSCLK CA8-CA0 CD7-CD0 DEVSEL_B E2PCLK E2PCS E2PDI E2PDO FRAME_B FULL_B/TxCLAV GND GNT_B IDSEL INTR_B IRDY_B JCK JDI JDO JMS JRST_B LA5-LA0 LASTB PAR PERR_B PHCE_B : Address/Data : Bus Clock : PHY Device Address : PHY Device Data : Device Select : Clock for EEPROM
TM
PHINT_B PHOE_B PHRW_B PHYSEL1 PO3-PO0 RCLK RENBL_B REQ_B RSOC RST_B RSTOUT_B Rx7-Rx0 SERR_B STOP_B TCLK TENBL_B TRDY_B TSOC Tx7-Tx0 VDD3 VDD5
: PHY Interrupt : PHY Output Enable : PHY Read/Write : PHY Select : Generic Output Port : Receive Clock : Receive Enable : Request : Receive Start of Cell : Reset : Reset Output : Receive Data Bus : System Error : Stop : Transmit Clock : Transmit Enable : Target Ready : Transmit Start of Cell : Transmit Data Bus : +3.3 V Power Supply : +5 V Power Supply
: EEPROM Chip Select : Serial Data Input from EEPROM : Serial Data Output to EEPROM : Cycle Frame : PHY Buffer Full / Tx Cell Available : Ground : Grant : ID Select : Interrupt : Initiator Ready : JTAG Test Pin : JTAG Test Pin : JTAG Test Pin : JTAG Test Pin : JTAG Test Pin : Internal Test Pin : Internal Test Pin : Parity : Parity Error : PHY Chip Enable
EMPTY_B/RxCLAV: PHY Empty / Rx Cell Available
PCBE_B3-PCBE_B0: Bus Command and Byte Enables
4
PD98409
CONTENTS 1. PIN FUNCTION ...................................................................................................................................... 6
1.1 PHY Device Interface Pin............................................................................................................................... 6 1.1.1 UTOPIA interface................................................................................................................................. 6 1.1.2 PHY device control interface ............................................................................................................. 7 1.2 Bus Interface Pins.......................................................................................................................................... 8 1.3 Serial EEPROM Interface Pins .................................................................................................................... 10 1.4 JTAG Boundary Scan Pins.......................................................................................................................... 10 1.5 Other Pins..................................................................................................................................................... 11 1.6 Power and Ground Pins .............................................................................................................................. 11
2. ELECTRICAL SPECIFICATIONS ........................................................................................................ 12 3. PACKAGE DRAWING ......................................................................................................................... 33 4. SOLDERING CONDITIONS ................................................................................................................. 34
5
PD98409
1. PIN FUNCTION
The pin function of the PD98409 is descibed below. A detailed explanation of how to use each pin, and the points to be noted in using the pins are given in PD98409 User's Manual (Document Number: S12776E). Be sure to refer to this user's manual. The following describes the I/O levels in the tables. LV-TTL input : Can be connected to 5 V CMOS output TTL output PCI input PCI output : Can be connected to 5 V TTL input, VOH = 3.3 V, IOL = 6 mA : 5/3.3 V PCI input : 5/3.3 V PCI output CMOS output : 3.3 V CMOS output, VOH = 3.3 V, IOL = 12 mA
1.1 PHY Device Interface Pin PHY device interfaces include a UTOPIA interface through which the PD98409 transfers ATM cells with a PHY device, and a PHY control interface by which the PD98409 controls the PHY device. 1.1.1 UTOPIA interface (1/2)
Pin Name Rx7-Rx0 Pin No. 116 - 119, 123 - 126 I/O I I/O Level LV-TTL Function Receive Data Bus. Rx7 through Rx0 constitute an 8-bit input bus which inputs data received from a network in byte format from a PHY device. The PD98409 loads data in at the rising edge of RCLK. Receive Start Cell. The RSOC signal is input in synchronization with the first byte of the cell data from a PHY device. This signal remains high while the first byte of the header is input to Rx7 through Rx0. Receive Enable. The RENBL_B signal indicates to a PHY device that the PD98409 is ready to receive data in the next clock cycle. PHY Output Buffer Empty/Rx Cell Available. This signal notifies the PD98409 that there is no cell data to be transferred in the receive FIFO and that no receive data can be supplied to the PHY device. When the UTOPIA interface is in the octet-level handshake mode, this signal serves as EMPTY_B, indicating that the data on Rx7 through Rx0 are invalid in the current clock cycle. In the cell-level handshake mode, it serves as RxCLAV, indicating that there is no cell to be supplied next after the transfer of the current cell is completed. Receive Clock. This is a synchronization clock used to transfer cell data with the PHY device at the receive side. The system clock input to the BUSCLK pin is output from this pin as is. Transmit Data Bus. Tx7 through Tx0 constitute an 8-bit output bus which outputs transmit data in byte format to a PHY device. The PD98409 outputs data at the rising edge of TCLK. Transmit Start of Cell. The TSOC signal is output in synchronization with the first byte of transmit cell data.
RSOC
133
I
LV-TTL
RENBL_B
132
O
TTL
EMPTY_B/ RxCLAV
131
I
LV-TTL
RCLK
128
O
TTL
Tx7-Tx0
141 - 144, 146 - 149
O
TTL
TSOC
135
O
TTL
6
PD98409
(2/2)
Pin Name TENBL_B Pin No. 136 I/O O I/O Level TTL Transmit Enable. The TENBL_B signal indicates to a PHY device that data has been output to Tx7 through Tx0 in the current clock cycle. FULL_B/ TxCLAV 134 I LV-TTL PHY Buffer Full/Tx Cell Available. This signal notifies the PD98409 that the input buffer of the PHY device is full and that the device can receive no more data. When the UTOPIA interface is in the octet-level handshake mode, the PHY device inputs an inactive level to receive cell data. In the celllevel handshake mode, the PHY device inputs a signal that indicates that the PHY device can receive all the next one cell of data after the current cell has been completely transferred. TCLK 138 O TTL Transmit Clock. This is a synchronization clock used to transfer cell data with the PHY device at the transmission side. The system clock input to the BUSCLK pin is output from this pin as is. Function
1.1.2 PHY device control interface
Pin Name PHRW_B Pin No. 153 I/O O I/O Level TTL Function PHY Read/Write. The PD98409 indicates the direction in which the PHY device is controlled, by using PHRW_B. 1: Read 0: Write PHOE_B 165 O TTL PHY Output Enable. The PD98409 enables output from the PHY device by making PHOE_B low PHY Chip Enable. The PD98409 makes PHCE_B low to access a PHY device. PHY Interrupt. This is an interrupt input signal from a PHY device. The PHY device indicates to the PD98409 that it has an interrupt source, by inputting a low level to PHINT_B. Reset Output. This is a signal to reset a PHY device. The PD98409 makes this pin low for the duration of 11 to 22 clock cycles when a low level is input to the RST_B pin or a software reset is executed. PHY device data. CD7 through CD0 constitute an 8-bit data bus. These pins are threestate I/O pins. They are used to transfer data with a PHY device. PHY device address. CA8 through CA0 constitute a 9-bit address bus that outputs an address to a PHY device during read/write operation.
PHCE_B
166
O
TTL
PHINT_B
152
I
LV-TTL
RSTOUT_B
232
O
TTL
CD7-CD0
154, 155, 157 - 159, 162 - 164 178 - 175, 173 - 170, 167
I/O
3-state
LV-TTL in TTL out
CA8-CA0
O
TTL
7
PD98409
1.2 Bus Interface Pins The PD98409 employs a 32-bit PCI bus interface as a bus interface with the host. This interface conforms to "PCI Local Bus Specification Revision 2.1". (1/2)
Pin Name AD31-AD0 Pin No. 238, 239, 3 - 6, 9, 10, 16 - 19, 22 - 25, 42 - 45, 48 - 51, 55 - 57, 62 - 65, 68 11, 27, 39, 54 I/O I/O 3-state I/O Level PCI Function Address/data. AD31 through AD0 are 32 bits of multiplexed address and data bus signals. When the PD98409 operates as the bus master, it drives an address at the first one clock, and transfers data at the second clock and onward.
PCBE3_B PCBE2_B PCBE1_B PCBE0_B
I/O 3-state
PCI
Bus command and byte enable. These signals define "bus commands" (generated bus transaction) in an address phase. In a data phase, they indicate which byte lane holds valid data. The PCBE3_B pin corresponds to byte 3 (bits 31 through 24), and PCBE0_B pin corresponds to byte 0 (bits 7 through 0). Parity. This signal inputs/outputs an even parity on the AD31 through AD0 and PCBE3_B through PCBE0_B pins including the PAR signal. When the PD98409 operates as the master, the PAR signal is output in the address and write data phases. When the PD98409 operates as a target, the PAR signal is output in the read data phase. Frame. This signal indicates the start and period of bus transaction. When this signal becomes active, it indicates the start of bus transaction. While it is active, data is transferred. When the next data transfer phase is for the last data of the transaction, this signal becomes inactive. Target ready. This signal goes low when the target device is ready to complete the transaction of the current data phase. This signal is used in pairs with IRDY_B. When both IRDY_B and TRDY_B are low, read/write data transfer is executed. Initiator ready. This signal goes low when the initiator is ready to complete the transaction of the current data phase. This signal is used in pairs with TRDY_B. When both IRDY_B and TRDY_B are low, read/write data transfer is executed. If both FRAME_B and IRDY_B are inactive, the bus cycle is not executed, and wait cycles are inserted until both IRDY_B and TRDY_B become active.
PAR
38
I/O 3-state
PCI
FRAME_B
28
I/O Sustained 3-state
PCI
TRDY_B
30
I/O Sustained 3-state
PCI
IRDY_B
29
I/O Sustained 3-state
PCI
8
PD98409
(2/2) Pin Name STOP_B Pin No. 34 I/O I/O Sustained 3-state I/O Sustained 3-state I/O Level PCI Function Stop. This signal goes low when the target device requests the master device to stop the current transaction. Device select. This signal goes low when the PD98409 operates as a target and recognizes an address after the FRAME_B signal has become active. When the PD98409 operates as the master, it samples this signal to check to see whether a target device has been selected. Initialization device select. This signal inputs a high level when the configuration register of the PD98409 is read/written. Request. The PD98409 requests the arbiter for the bus mastership by making this signal low. Grant. This signal goes low when the arbiter grants the PD98409 the bus mastership. Parity error. This signal indicates that the PD98409 has detected a parity error. It is enabled when the "Parity Error Response" bit of the configuration register is set to 1. System error. This signal indicates that the PD98409 has detected an address parity error. It is enabled when both the "Parity Error Response" and "System Error Enable" bits of the configuration register are set to 1. Interrupt output. Pull up this pin because it outputs an open-drain signal. INTR_B informs the CPU that the interrupt bit (not masked) of the GSR register is set. PCI bus clock. Bus clock input pin. It inputs a clock of up to 33 MHz. Reset. The RST_B signal initializes the PD98409 (on starting). When a low level is input to RST_B, the internal state machine and registers of the PD98409 are reset, and all the 3-state signals go into a highimpedance state. When this signal is input while the PD98409 is operating, the operating status at that time is lost. Keep the input to RST_B low at least for the duration of 1 clock cycle. Do not access the PD98409 at least for 20 clocks after it has been reset.
DEVSEL_B
33
PCI
IDSEL
13
I
PCI
REQ_B
69
ONote
PCI
GNT_B
71
I
PCI
PERR_B
35
I/O Sustained 3-state
PCI
SERR_B
37
O
N-ch open-drain
INTR_B
75
O
N-ch open-drain
BUSCLK
73
I
PCI
RST_B
235
I
PCI
Note Although the "PCI Local Bus Specification Revision 2.1" specifies that the REQ_B pin go into a highimpedance state while a low level is input to the RST_B pin, the REQ_B pin of the PD98409 outputs a high level.
9
PD98409
1.3 Serial EEPROM Interface Pins The PD98409 has an interface for serial EEPROM supporting the MICROWIRETM interface. contents of the PCI configuration register can be loaded from the EEPROM connected. As the EEPROM, "NM93C46L" of National Semiconductor Corp. is recommended.
Pin Name E2PCS Pin No. 84 I/O O I/O Level TTL Function EEPROM chip select. A chip select signal for EEPROM. Leave this pin open when it is not used. EEPROM data input. This pin is connected to the data output pin of the EEPROM. Pull up or open this pin when it is not used. EEPROM data output. This pin is connected to the data input pin of the EEPROM. Pull up or open this pin when it is not used. EEPROM clock. This pin supplies a clock necessary for data transfer with the EEPROM. It outputs the clock input to the BUSCLK pin divided by 36. Leave this pin open when it is not used.
Some of the
E2PDI
83
I
TTL Internally pulled up TTL
E2PDO
82
O
E2PCLK
79
O
TTL
1.4 JTAG Boundary Scan Pins (These functions can be supported by request.)
Pin Name JDI Pin No. 216 I/O I I/O Level LV-TTL JTAG Test Data Input. The JDI pin is used to input data to the JTAG boundary scan circuit register. Normally, fix this pin to high or low level. JDO 217 O 3-state TTL JTAG Test Data Output. The JDO pin is used to output data from the JTAG boundary scan circuit register. It changes output at the falling edge of the clock input to the JCK pin. Normally, leave this pin open. JCK 214 I LV-TTL JTAG Test Clock. This pin is used to supply a clock to the JTAG boundary scan circuit register. Normally, fix this pin to a high or low level. JMS 218 I LV-TTL JTAG Test Mode Select. Normally, fix this pin to a high or low level. JRST_B 219 I LV-TTL JTAG Test Reset. This pin initializes the JTAG boundary scan circuit register. Normally, fix this pin to a low level. Function
10
PD98409
1.5 Other Pins
Pin Name PHYSEL1 Pin No. 225 I/O I I/O Level LV-TTL Internal test pin. Input a low level to this pin. PO3-PO0 192 - 195 O CMOS General-purpose output port. General-purpose output port pins. These pins output the value written to the GPOR register. Internal test pins. Leave these pins open during normal operation. Internal test pin. Leave this pin open during normal operation. Function
LA5-LA0
182 - 185, 187, 188 189
O
TTL
LASTB
O
TTL
1.6 Power and Ground Pins
Pin Name VDD3 Pin No. 21, 40, 61, 81, 91, 100, 120, 130, 140, 151, 160, 169, 181, 190, 201, 206, 220, 240 8, 14, 32, 47, 52, 58, 67, 76, 234, 237 I/O Function +3.3-V power supply. These pins supply +3.3 V to the chip.
VDD5
+5 V power supply. These pins supply +5 V to the chip when a +5-V bus interface is used. Supply +3.3 V to these pins when a +3.3-V bus interface is used. Ground. Connect to ground.
GND
1, 2, 7, 12, 15, 20, 26, 31, 36, 41, 46, 53, 59, 60, 66, 70, 72, 74, 77, 78, 80, 85, 90, 96, 98, 101, 110, 112, 121, 122, 127, 129, 137, 139, 145, 150, 156, 161, 168, 174, 179, 180, 186, 191, 196, 200, 207, 213, 215, 221, 223, 228, 233, 236
11
PD98409
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Supply voltage Symbol VDD3 VDD5 Input voltage VI
Note
Conditions
Ratings -0.5 to +4.6
Unit V V V V V
VDD3 VDD5 Except pin PCI, VI < VDD3 + 3.0 V PCI pin
-0.5 to +6.6 -0.5 to +6.6 -5.5 to +11.0 -0.5 to +6.6 -0.5 to +4.6 -0.5 to +6.6 20 40 20 0 to +70 -65 to +150
Output voltage
VO
Except PCI pin and PO0-PO3, VO < VDD3 + 3.0 V PO3-PO0, VO < VDD3 + 0.5 V PCI pin
V V mA mA mA C C
Output current
IO
Except PCI pin and PO0-PO3 PO3-PO0 PCI pin
Operating ambient temperature Storage temperature
TA Tstg
Note VDD5: Dedicated power supply for clamping diode Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the product(s). Be sure to use the product(s) within the ratings. Recommended Operating Conditions
Parameter Supply voltage Symbol VDD3 VDD5 Note VDD5 Operating ambient temperature High-level input voltage
Note
Conditions
MIN. 3.0
TYP. 3.3 3.3 5.00
MAX. 3.6 3.6 5.25 +70 5.5 VDD5 + 0.5 VDD5 + 0.5 +0.8 +0.8
Unit V V V C V V V V V
+3.3 V PCI +5 V PCI
3.0 4.75 0
TA VIH1 VIH2 VIH3 Input pins except PCI RST_B pin PCI pins except RST_B Input pins except PCI PCI pin
2.0 2.2 2.0 0 -0.5
Low-level input voltage
VIL1 VIL2
Note VDD5: Dedicated power supply for clamping diode
12
PD98409
DC Charateristics (TA = 0 to +70C, VDD3 = +3.3 V 0.3 V)
Parameter High-level output voltage Symbol VOH1 VOH2 Low-level output voltage VOL1 VOL2 VOL3 VOL4 Supply current IDD Conditions IOH = -2.0 mA
Note 1
MIN. 2.4 2.4
TYP.
MAX.
Unit V V
IOH = -12.0 mA IOL = 3.0 mA
Note 2
Note 3
0.55 0.55 0.40 0.40 250 10-4 10 80 400 10 200
V V V V mA
IOL = 6.0 mANote 4 IOL = 6.0 mA
Note 5
IOL = 12.0 mA
Note 6
fCLK = 33 MHz, normal transmission/ reception VI = VDD3 VI = GND
Input leakage current (normal input) Input leakage current (E2PDI pin with pull-up resistor)
II1 II2
A A
Notes 1. 2. 3. 4. 5. 6.
VOH1 applies to all output pins except pins PO3-PO0. VOH2 applies to pins PO3-PO0. VOL1 applies to PCI output pins AD31-AD0, PCBE3_B-PCBE0_B, PAR, REQ_B and INTR_B. VOL2 applies to PCI output pins FRAME_B, TRDY_B, IRDY_B, DEVSEL_B, STOP_B, SERR_B, and PERR_B. VOL3 applies to pins other than PCI output pins and pins other than pins PO3-PO0. VOL4 applies to pins PO3-PO0.
Capacitance (TA = +25C, VDD3 = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CIN COUT CI/O f = 1 MHz f = 1 MHz f = 1 MHz Conditions MIN. TYP. 10 10 10 MAX. 20 20 20 Unit pF pF pF
13
PD98409
AC Characteristics (TA = 0 to +70C, VDD3 = +3.3 V 0.3 V) BUSCLK input
Parameter CLK cycle time CLK high-level width CLK low-level width CLK amplitude CLK through rate Symbol tCYCLK tCLKH tCLKL VPPCLK slewCLK Conditions MIN. 30 11 11 2 1 4 TYP. MAX. 125 Unit ns ns ns V V/ns
CLK
0.8 V
RST input
Parameter RST low-level width RST through rate
PP @@ ,, P @ , PP PP PP P @@ @@ @@ @ ,, ,, ,, , P PP PP P @ @@ @@ @ , ,, ,, , P P,,,P @ @PPP@ , ,@@@, ,,,,,, PPPP PP @@@@ @@ ,,,, ,, PPPPPPP @@@@@@@ ,,,,,,, PP P @@ @ ,, , P @ ,
2.4 V (MIN.) 2.0 V 1.5 V VPPCLK 0.4 V (MAX.) tCLKH tCLKL tCYCLK
Symbol tRSTL slewRST
Conditions
MIN. tCYCLK 50
TYP.
MAX.
Unit ns mV/ns
14
PD98409
PCI Bus Interface Bus master read
Parameter CLKFRAME_B valid time CLKAD (Address) valid time CLKAD (Address) float time AD (Data) setup time AD (Data) hold time CLKPCBE_B valid time CLKPCBE_B float time CLKIRDY_B valid time CLKIRDY_B float time TRDY_B setup time TRDY_B hold time DEVSEL_B setup time DEVSEL_B hold time CLKPAR valid time CLKPAR float time PAR setup time PAR hold time CLKPERR_B valid time CLKPERR_B float time Symbol tDFRAME tDADDR tDADDRF tSDATA tHDATA tDPCBE tDPCBEF tDIRDY tDIRDYF tSTRDY tHTRDY tSDEVSEL tHDEVSEL tDPAR tDPARF tSPAR tHPAR tDPERR tDPERRF 2 7
Note 1
Conditions
MIN. 2 2
TYP.
MAX. 11 11 28
Unit ns ns ns ns ns
7 2
Note 1
2
11 28
ns ns ns ns ns ns ns ns
2
11 28
9Note 2 2
Note 1
7 2
Note 1
2
11 28
ns ns ns ns
2
11 28
ns ns
Notes 1. 2.
Relaxed specification from PCI Local Bus Specification Revision 2.1 0 ns 2 ns Relaxed specification from PCI Local Bus Specification Revision 2.1 7 ns 9 ns
15
PD98409
Bus master read
CLK
FRAME_B
AD31-AD0
PCBE3_BPCBE0_B
IRDY_B
TRDY_B
DEVSEL_B
PAR
PERR_B
PP P @@ @ ,, , PPP PPPP PP @@@ @@@@ @@ ,,, ,,,, ,, P @ , PPP PP P P @@@ @@ @ @ ,,, ,, , , PPPPPPP @@@@@@@ ,,,,,,, PP @@ ,, PPPPPPPP P @@@@@@@@ @ ,,,,,,,, , PPPPPPPP P @@@@@@@@ @ ,,,,,,,, , PPP PPPP P @@@ @@@@ @ ,,, ,,,, , P @ , PP @@ ,, PP PP P @@ @@ @ ,, ,, , P PP P P P @ @@ @ @ @ ,,,, , , , ,, PP PP @@ @@ ,, P PPPP P @ @@@@ @ , ,,,, , P PPPP P @ @@@@ @ , ,,,, , P PPPP P @ @@@@ @ , ,,,, , PP @@ ,, P PP PP P @ @@ @@ @ , ,, ,, , P PP PP PP @ @@ @@ @@ , ,, ,, ,, PP PP @@ @@ ,, ,, PP PP @@ @@ ,, ,,
tDFRAME tDADDR tDADDRF tSDATA tHDATA (Data) (Address) tDPCBE tDPCBEF tDIRDY tDIRDYF tSTRDY tHTRDY tSDEVSEL tHDEVSEL tDPAR tDPARF tSPAR tHPAR (output) (input) tDPERR tDPERRF
16
PD98409
Bus master write
Parameter CLK FRAME_B valid time CLK AD (Address) valid time CLK data valid time CLK data float time CLK PCBE_B valid time CLK PCBE_B float time CLK IRDY_B valid time CLK IRDY_B float time TRDY_B setup time TRDY_B hold time DEVSEL_B setup time DEVSEL_B hold time CLK PAR valid time CLK PAR float time PERR_B setup time PERR_B hold time Symbol tDFRAME tDADDR tDDATA tDDATAF tDPCBE tDPCBEF tDIRDY tDIRDYF tSTRDY tHTRDY tSDEVSEL tHDEVSEL tDPAR tDPARF tSPERR tHPERR 7 2Note 1 2 9
Note 2
Conditions
MIN. 2 2 2
TYP.
MAX. 11 11 11 28
Unit ns ns ns ns ns ns ns ns ns ns ns ns
2
11 28
2
11 28
2Note 1 7
Note 1
2
11 28
ns ns ns ns
Notes 1. 2.
Relaxed specification from PCI Local Bus Specification Revision 2.1 0 ns 2 ns Relaxed specification from PCI Local Bus Specification Revision 2.1 7 ns 9 ns
17
PD98409
Bus master write
CLK
FRAME_B
AD31-AD0
PCBE3_BPCBE0_B
IRDY_B
TRDY_B
DEVSEL_B
PAR
PERR_B
,,, PP @@ ,, PP,, @@PP ,,@@ P @ , PPPP @@@@ ,,,, PPPP @@@@ ,,,, PPP @@@ ,,, PP @@ ,, PP @@ ,, PPP @@@ ,,, PP @@ ,, PP @@ ,, PP @@ ,, PP @@ ,, P @ , PP @@ ,, P @ , PP @@ ,,
tDFRAME tDADDR (Address) tDPCBE
tDDATA
tDIRDY
tSTRDY
tSDEVSEL
tDPAR (output)
PP @@ ,, PPPP @@@@ ,,,, PP P P @@ @ @ ,, , , PPP @@@ ,,, PP P P @@ @ @ ,, , , P PP @ @@ , ,, P PP @ @@ , ,, PP P P @@ @ @ ,, , , PP @@ ,, P PP @ @@ , ,, P PP @ @@ , ,, PP PP @@ @@ ,, ,, PP PP @@ @@ ,, ,, PP PP @@ @@ ,, ,, PP PP @@ @@ ,, ,, PP PP @@ @@ ,, ,, PPP @@@ ,,, ,, PP @@ P @ ,
tDDATAF (Data) tDPCBEF tDIRDYF tHTRDY tHDEVSEL tDPARF (output) tSPERR
tHPERR
18
PD98409
Target read
Parameter FRAME_B setup time FRAME_B hold time AD (Address) setup time AD (Address) hold time CLK AD (Data) valid time CLK AD (Data) float time PCBE_B setup time PCBE_B hold time IRDY_B setup time IRDY_B hold time CLK TRDY_B valid time CLK TRDY_B float time CLK DEVSEL_B valid time CLK DEVSEL_B float time PAR setup time PAR hold time CLK PAR valid time CLK PAR float time PERR_B setup time PERR_B hold time Symbol tSFRAME tHFRAME tSADDR tHADDR tDDATA tDDATAF tSPCBE tHPCBE tSIRDY tHIRDY tDTRDY tDTRDYF tDDEVSEL tDDEVSELF tSPAR tHPAR tDPAR tDPARF tSPERR tHPERR 2 7
Note 1
Conditions
MIN. 7 2
Note 1
TYP.
MAX.
Unit ns ns ns ns
7 2Note 1 2 11 28 7 2 9
Note 1
ns ns ns ns ns ns
Note 2
2Note 1 2 11 28 2 11 28 7 2Note 1 2 11 28
ns ns ns ns ns ns ns ns ns
Notes 1. 2.
Relaxed specification from PCI Local Bus Specification Revision 2.1 0 ns 2 ns Relaxed specification from PCI Local Bus Specification Revision 2.1 7 ns 9 ns
19
PD98409
Target read
CLK
FRAME_B
AD31-AD0
PCBE3_BPCBE0_B
IRDY_B
TRDY_B
DEVSEL_B
PAR
PERR_B
P PPPP P @ @@@@ @ , ,,,, , PP P @@ @ ,, , PPP @@@ ,,, PP P P P P @@ @ @ @ @ ,, , , , , PP P P @@ @ @ ,, , , PP @@ ,, PP P P @@ @ @ ,, , , PP P P P P @@ @ @ @ @ ,, , , , , PP P P P P P @@ @ @ @ @ @ ,, , , , , , PP P @@ @ ,, , PP P @@ @ ,, , P PPPP @ @@@@ , ,,,, P PP P @ @@ @ , ,, , PPP @@@ ,,, PP PP @@ @@ ,, ,, PP PPPP @@ @@@@ ,, ,,,, PP P P @@ @ @ ,, , , PP @@ ,, P, @P ,@ PP @@ ,,
tSFRAME tHFRAME tSADDR tHADDR tDDATA tDDATAF
(Address)
(Data)
tSPCBE
tHPCBE
tSIRDY
tHIRDY
tDTRDYF
tDTRDY
tDDEVSELF
tDDEVSEL
tSPAR
tHPAR
tDPAR
tDPARF
(input)
(output)
tHPERR
tSPERR
20
PD98409
Target write
Parameter FRAME_B setup time FRAME_B hold time AD (Address) setup time AD (Address) hold time AD (Data) setup time AD (Data) hold time PCBE_B setup time PCBE_B hold time IRDY_B setup time IRDY_B hold time CLK TRDY_B valid time CLK TRDY_B float time CLK DEVSEL_B valid time CLK DEVSEL_B float time PAR setup time PAR hold time CLK PERR_B valid time CLK PERR_B float time Symbol tSFRAME tHFRAME tSADDR tHADDR tSDATA tHDATA tSPCBE tHPCBE tSIRDY tHIRDY tDTRDY tDTRDYF tDDEVSEL tDDEVSELF tSPAR tHPAR tDPERR tDPERRF 7 2Note 1 2 11 28 2 2 9 2 2 Conditions MIN. 7
Note 1
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns ns ns
7 2Note 1 7
Note 1
7
Note 1
Note 2
2Note 1 2 11 28 11 28
ns ns ns ns ns ns ns ns
Notes 1. 2.
Relaxed specification from PCI Local Bus Specification Revision 2.1 0 ns 2 ns Relaxed specification from PCI Local Bus Specification Revision 2.1 7 ns 9 ns
21
PD98409
Target write
CLK
FRAME_B
AD31-AD0
PCBE3_BPCBE0_B
IRDY_B
TRDY_B
DEVSEL_B
PAR
PERR_B
P PPPP P @ @@@@ @ , ,,,, , P @ , PP @@ ,, PP P P P P @@ @ @ @ @ ,, , , , , PP,, PP P @@PP @@ @ ,,@@ ,, , ,,, PP @@ ,, PP @@ ,, PP P P P P P @@ @ @ @ @ @ ,, , , , , , PP P P P P P @@ @ @ @ @ @ ,, , , , , , PP @@ ,, PP @@ ,, PP PP P @@ @@ @ ,, ,, , PP @@ ,, P PP P @ @@ @ , ,, , PP @@ ,, P PP P @ @@ @ , ,, , PP @@ ,, PP P P @@ @ @ ,, , , P P P PP @ @ @ @@ , , , ,, PP PP @@ @@ ,, ,, PP @@ ,,
tSFRAME tHFRAME tSADDR tHADDR tSDATA tHDATA
(Address)
(Data)
tSPCBE
tHPCBE
tSIRDY
tHIRDY
tDTRDYF
tDTRDY
tDDEVSELF
tDDEVSEL
tSPAR
tHPAR
(input)
(input)
tDPERR
tDPERRF
22
PD98409
Bus arbitration
Parameter CLK REQ_B valid time GNT_B setup time GNT_B hold time Symbol tDREQ tSGNT tHGNT Conditions MIN. 2 10 2
Note
TYP.
MAX. 12
Unit ns ns ns
Note Relaxed specification from PCI Local Bus Specification Revision 2.1 0 ns 2 ns Bus arbitration
CLK
REQ_B
P @ , PP @@ ,, P @ ,
tDREQ
GNT_B
P @ , P @ , ,, PP @@ ,,, P,, @PP ,@@ P @ , PP @@ ,,
tSGNT tHGNT
23
PD98409
Configuration read
Parameter FRAME_B setup time FRAME_B hold time AD (Address) setup time AD (Address) hold time CLK AD (Data) valid time CLK AD (Data) float time PCBE_B setup time PCBE_B hold time IDSEL setup time IDSEL hold time IRDY_B setup time IRDY_B hold time CLK TRDY_B valid time CLK TRDY_B float time CLK DEVSEL_B valid time CLK DEVSEL_B float time CLK PAR valid time CLK PAR float time PAR setup time PAR hold time PERR_B setup time PERR_B hold time Symbol tSFRAME tHFRAME tSADDR tHADDR tDDATA tDDATAF tSPCBE tHPCBE tSIDSEL tHIDSEL tSIRDY tHIRDY tDTRDY tDTRDYF tDDEVSEL tDDEVSELF tDPAR tDPARF tSPAR tHPAR tSPERR tHPERR 2 7
Note 1
Conditions
MIN. 7 2
Note 1
TYP.
MAX.
Unit ns ns ns ns
7 2Note 1 2 11 28 7 2
Note 1
ns ns ns ns ns ns ns ns
7 2Note 1 9 2
Note 2
Note 1
2
11 28
ns ns ns ns ns ns ns ns ns ns
2
11 28
2
11 28
7 2Note 1
Notes 1. 2.
Relaxed specification from PCI Local Bus Specification Revision 2.1 0 ns 2 ns Relaxed specification from PCI Local Bus Specification Revision 2.1 7 ns 9 ns
24
PD98409
Configuration read
CLK
tSFRAME FRAME_B
tSADDR AD31-AD0
tSPCBE PCBE3_BPCBE0_B
tSIDSEL IDSEL
IRDY_B
TRDY_B
DEVSEL_B
PAR
PERR_B
P P,,PPPP @ @PP@@@@ , ,@@,,,, P, @ PPP , @@@ ,,, ,,, PP P PP,PP @@ @ @@P@@ ,, , ,,@,, PP P P @@ @ @ P ,, , , @ PP PP @@ @@ ,, ,, PP P PPPPP @@ @ @@@@@ ,, , ,,,,, PP P P PPP @@ @ @ @@@ ,, , , ,,, PP @@ ,, PP P P PPP @@ @ @ @@@ ,, , , ,,, PP P @@ @ ,, , PPPPPP PPP @@@@@@ @@@ ,,,,,, ,,, PPPP P PPP @@@@ @ @@@ ,,,, , ,,, PP P PP @@ @ @@ ,, , ,, PP P PP @@ @ @@ ,, , ,, P PPP @ @@@ , ,,, P @ , PP @@ ,, P PP @ @@ , ,, P @ , PP , PP @@ P @@ ,, @ ,, PP @@ PPP ,, @@@ ,,,, ,,, PPPP PP @@@@ @@ ,,,, ,, PP @@ ,, PP @@ ,, PP @@ ,, PP @@ ,, PP @@ ,,
tHFRAME tHADDR tDDATA tDDATAF
(Address)
(Data)
tHPCBE
tHIDSEL
tSIRDY
tHIRDY
tDTRDYF
tDTRDY
tDDEVSELF
tDDEVSEL
tSPAR
tHPAR
tDPAR
tDPARF
(input)
(output)
tHPERR
tSPERR
25
PD98409
EEPROM Interface
Parameter E2PCLK high-level width Symbol tWE2PCLKH Conditions MIN. TYP. MAX. Unit ns
tCYCLK x 18 tCYCLK x 18 tCYCLK x 18 + 50 - 50 tCYCLK x 18 tCYCLK x 18 tCYCLK x 18 + 50 - 50 50 50 300 500 70 500
E2PCLK low-level width E2PCLK E2PCS valid time E2PCS E2PCLK P2PCLK E2PDO valid time E2PDI E2PCLK setup time E2PCLK E2PDI hold time E2PCS E2PDI (Status) valid delay time E2PCS E2PDI (Status) invalid delay time
tWE2PCLKL
ns
tDE2PCS tSE2PCS tDE2PDO tSE2PDI tHE2PDI tDE2PSTV
ns ns ns ns ns ns
tDE2PSTI
0
100
ns
EEPROM interface
E2PCLK
tDE2PCS E2PCS
tDE2PDO E2PDO
E2PDI (READ) E2PDI (Status)
P P PP @ @ @@ , , ,, PPPP @@@@ ,,,, PPP PP @@@ @@ ,,, ,, PP PP @@ @@ ,, ,, PP @@ ,, PPP P @@@ @ ,,, , PP @@ ,, PP P @@ @ ,, , PPPPPP @@@@@@ ,,,,,, PP @@ ,, PP P @@ @ ,, , PP @@ ,, PP @@ ,,
tWE2PCLKH tWE2PCLKL tSE2PCS tSE2PDI tHE2PDI tDE2PSTV
tDE2PCS
(Status)
P @ , PP @@ ,, PP @@ ,, PP @@ ,, P @ , P @ , P @ , P @ ,
tDE2PSTI
26
PD98409
UTOPIA Interface Transmission operation
Parameter TCLK Tx delay time TCLK TSOC delay time TCLK TENBL_B delay time FULL_B setup time FULL_B hold time Symbol tDTX tDTSOC tDTEN tSFULL tHFULL Conditions MIN. 3 3 3 8 1 TYP. MAX. 18 18 18 Unit ns ns ns ns ns
Reception operation
Parameter Rx setup time Rx hold time RSOC setup time RSOC hold time RCLK RENBL_B delay time EMPTY_B setup time EMPTY_B hold time Symbol tSRX tHRX tSRSOC tHRSOC tDREN tSEMPT tHEMPT Conditions MIN. 8 1 8 1 3 8 1 18 TYP. MAX. Unit ns ns ns ns ns ns ns
27
PD98409
,,, PPP @@@ ,,, ,, PP @@ ,, ,,,,,, PPPPPP @@@@@@ ,,,,,, , P @ , ,,,,,, PPPPPP @@@@@@ ,,,,,, ,,, PPP @@@ ,,, ,, PP @@ ,, , ,,, P PPP @ @@@ , ,,, , P @ , , P @ , , P @ , ,,,,,,,, PPPPPPPP @@@@@@@@ ,,,,,,,, , P @ , ,,, PPP @@@ ,,, , P @ , , P @ ,
INVALID `00H' P1 tDTEN tDTEN P2 H4
P3
P4
P5
P6
P7
P8
P9
Transmission operation
UTOPIA interface (1)
TCLK
TENBL_B
Tx7-Tx0
TSOC
28
FULL_B
,, PP @@ ,, ,,,,, PPPPP @@@@@ , ,, ,, PP @@ ,, , PP P @@ @ ,, ,,,,, ,,,,, PPPPP @@@@@ ,,,,, ,,,,, PPPPP @@@@@ ,,,,, ,, ,, PP PP @@ @@ ,, ,, ,, PP @@ ,,
tDTX
H3
tDTSOC
H2
tSFULL
tHFULL
tDTSOC
H1-H4: ATM header P1-P9: Payload data H1
PD98409
,, PP @@ ,, ,, PP @@ ,, ,,,,,, PPPPPP @@@@@@ ,,,,,, ,, PP @@ ,, ,,,,,, PPPPPP @@@@@@ ,,,,,, ,, PP @@ ,, ,, PP @@ ,,
INVALID
P3
P4
P5
P6
P7
UTOPIA interface (2)
Reception operation
,,, PPP @@@ ,,, ,, PP @@ ,, ,,,,,,,, PPPPPPPP @@@@@@@@ ,,,,,,,, ,, PP @@ ,, ,,,,,,,, PPPPPPPP @@@@@@@@ ,,,,,,,, , P @ , ,, PP @@ ,, ,, PP @@ ,, , P @ , ,, ,, PP PP @@ @@ ,, ,, ,,,,, PPPPP @@@@@ ,,,,, ,,,,, PPPPP @@@@@ ,,,,, ,, ,, PP PP @@ @@ ,, ,, ,, ,, PP PP @@ @@ ,, ,, ,,,,, PPPPP @@@@@ ,,,,,
INVALID H3 tHRSOC tHRX H2 tSEMPT tHEMPT H4 tSRX H1 Rx7-Rx0 RSOC RCLK tSRSOC RENBL_B EMPTY_B
H5
P1
tDREN
P2
tDREN
H1-H4: ATM header P1-P7: Payload data
29
PD98409
PHY Status Access Write
Parameter CLK CA delay time CLK PHRW_B delay time CLK PHCE_B delay time CLK CD delay time PHCE_B CD float time Symbol tDPCA tDPHRW tDPHCE tDPCD tFPCD 1tCYCLK - 10 Conditions MIN. TYP. MAX. 20 20 20 20 1tCYCLK + 10 Unit ns ns ns ns ns
Write timing
CLK
tDPCA CA8-CA0
PHRW_B
PHCE_B
PHOE_B
CD7-CD0
Read
Parameter CD setup time CD hold time CLK CA delay time
PP PP @@ @@ ,, ,, PPPPPPP @@@@@@@ ,,,,,,, PP PP @@ @@ ,, ,, PP PP @@ @@ ,, ,, PP PP @@ @@ ,, ,, PP PP @@ @@ ,, ,, PP PP @@ @@ ,, ,, PP PPP @@ @@@ ,, ,,, PP PP @@ @@ ,, ,, P @ , PP @@ ,, P @ , PP PP @@ @@ ,, ,, PP @@ ,, P @ ,
1 clock 4 clocks 1 clock tDPHRW tDPHCE tDPHCE "H" tDPCD tFPCD (output)
Symbol tSPCD tHPOECD tDPCA tDPHRW tDPHCE tDPHOE Conditions
tDPCA
tDPHRW
MIN. 0 0
TYP.
MAX.
Unit ns ns
20 20 20 20
ns ns ns ns
CLK PHRW_B delay time CLK PHCE_B delay time CLK PHOE_B delay time
30
PD98409
Read timing
,, PP PP @@ @@ ,, ,,,, ,,,, PPPP @@@@ ,, ,, , P @ , ,, PP @@ ,, ,,,,,,,, PPPPPPPP @@@@@@@@ ,,,,,,,, ,, PP @@ ,, , ,,,, P PPPP @ @@@@ , ,,,, , P @ , , P @ , , P @ , ,,,,,,,,, PPPPPPP,, @@@@@@@PP ,,,,,,,@@ ,, PP @@ ,, ,,, PPP @@@ ,,, , P @ , , P @ , , P @ , , P @ , ,, PP @@ ,, ,,, PPP @@@ ,,, ,, PP @@ ,, ,PP P@@ @,, ,,, , P @ , , P @ , , P @ , , P @ , , ,, P PP @ @@ , ,, ,,,,,, PPPPPP @@@@@@ ,,,,,, ,,,,,, PPPPPP @@@@@@ ,,,,,, ,,,, PP,, @@PP ,,@@ , P @ , ,,,, P,,, @PPP ,@@@ ,,,, PPPP @@@@ ,,,, , P @ ,
tDPHCE tHPOECD tDPHOE 4 clocks 5 clocks 6 clocks tDPCA 1 clock tDPCA tDPHRW tDPHCE PHCE_B tDPHOE tSPCD CD7-CD0 CA8-CA0 PHRW_B PHOE_B CLK (input)
31
PD98409
Others
Parameter PHINT_B setup time PHINT_B hold time CLK PO delay time CLK RSTOUT_B delay time RSTOUT_B output pulse width Symbol tSPHI tHPHI tDPO tDRSTO tWRSTO Conditions MIN. 8 1 2 2 11 25 25 22 TYP. MAX. Unit ns ns ns ns tCYCLK
Other timing
CLK
PHINT_B
PO3-PO0
RSTOUT_B
P @ , PP @@ ,, P @ , PP @@ ,, PP @@ ,, P @ , PP @@ ,, P @ , P @ , P @ , PPPPPPPPPPP @@@@@@@@@@@ ,,,,,,,,,,, P @ , P @ , P @ ,
tSPHI tHPHI tDPO tDRSTO tWRSTO
32
PD98409
3. PACKAGE DRAWING
240 PIN PLASTIC QFP (FINE PITCH) (32x32)
A B
180 181 121 120
detail of lead end S
C
D Q R
240 1
61 60
F G P
H
I
M
J K M N S L S
ITEM MILLIMETERS 34.60.2 32.00.2 32.00.2 34.60.2 1.25 1.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.30.2 0.50.2 0.17 +0.03 -0.07 0.10 3.20.1 0.40.1 3 +7 -3 3.8 MAX. INCHES 1.3620.008 1.2600.008 1.2600.008 1.3620.008 0.049 0.049 0.0090.002 0.004 0.020 (T.P.) 0.051+0.009 -0.008 0.020 +0.009 -0.008 0.007 +0.001 -0.003 0.004 0.1260.004 0.016 +0.004 -0.005 3 +7 -3 0.150 MAX. P240GN-50-LMU, MMU-2 A B C D F G H I J K L M N P Q R S
NOTE 1. Controlling dimention millimeter.
2. Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.
33
PD98409
4. SOLDERING CONDITIONS
Solder the product under the following recommended conditions. For details of the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and soldering conditions other than those recommended, consult NEC. Surface Mount Type
PD98409GN-LMU: 240-pin plastic QFP (0.5-mm fine pitch) (32 x 32 mm)
Symbol of Recommended Condition IR35-203-1
Soldering Method
Soldering Conditions
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds max. (210C min.), Number of Note times: once, Number of days: 3 (Afterwards, prebaking is necessary at 125C for 20 hours.) Products other than in heat-resistant trays (such as those packaged in a magazine, taping, or non-thermal-resistant tray) cannot be baked in their package.
Partial heating
Pin temperature: 300 C max., Time: 3 seconds max. (per side of device)
--
Note Number of days in storage after the dry pack has been opened. The storage conditions are at 25C, 65%RH max.
34
PD98409
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
35
PD98409
NEASCOT-S40C and EEPROM are trademarks of NEC Corporation. MICROWIRE is a trademark of National Semiconductor Corporation.
The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96. 5

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