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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT280 9-bit odd/even parity generator/checker Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 9-bit odd/even parity generator/checker FEATURES * Word-length easily expanded by cascading * Similar pin configuration to the "180" for easy system up-grading * Generates either odd or even parity for nine data bits * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT280 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT280 are 9-bit parity generators or checkers commonly used to detect errors in high-speed data QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns 74HC/HCT280 transmission or data retrieval systems. Both even and odd parity outputs are available for generating or checking even or odd parity up to 9 bits. The even parity output (E) is HIGH when an even number of data inputs (I0 to I8) are HIGH. The odd parity output (0) is HIGH when an odd number of data inputs are HIGH. Expansion to larger word sizes is accomplished by tying the even outputs (E) of up to nine parallel devices to the data inputs of the final stage. For a single-chip 16-bit even/odd parity generator/checker, see PC74HC/HCT7080. APPLICATIONS * 25-line parity generator/checker * 81-line parity generator/checker TYPICAL SYMBOL PARAMETER tPHL/ tPLH propagation delay In to E In to O CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". input capacitance power dissipationcapacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 17 20 3.5 65 18 22 3.5 65 ns ns pF pF HCT UNIT December 1990 2 Philips Semiconductors Product specification 9-bit odd/even parity generator/checker PIN DESCRIPTION PIN NO. 8, 9, 10, 11, 12, 13, 1, 2, 4 5, 6 7 14 SYMBOL I0 to I8 E, O GND VCC NAME AND FUNCTION data inputs parity outputs ground (0 V) positive supply voltage 74HC/HCT280 Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification 9-bit odd/even parity generator/checker 74HC/HCT280 FUNCTION TABLE INPUTS number of HIGH data inputs (I0 to I8) even odd Note 1. H = HIGH voltage level L = LOW voltage level OUTPUTS E H L O L H Fig.4 Functional diagram. Fig.5 Logic diagram. December 1990 4 Philips Semiconductors Product specification 9-bit odd/even parity generator/checker DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Out put capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay In to E propagation delay In to O output transition time +25 typ. 55 20 16 63 23 18 19 7 6 -40 to +85 max. min. 200 40 34 200 40 34 75 15 13 max. 250 50 43 250 50 43 95 19 16 -40 to +125 min. max. 300 60 51 300 60 51 110 22 19 ns UNIT 74HC/HCT280 TEST CONDITIONS VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 WAVEFORMS Fig.6 tPHL/ tPLH ns Fig.6 tTHL/ tTLH ns Fig.6 December 1990 5 Philips Semiconductors Product specification 9-bit odd/even parity generator/checker DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types 74HC/HCT280 The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT In UNIT LOAD COEFFICIENT 1.0 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL/ tPLH tTHL/ tTLH propagation delay In to E propagation delay In to O output transition time +25 typ. 21 26 7 -40 to +85 max. min. 42 45 15 max. 53 56 19 -40 to +125 min. max. 63 68 22 ns ns ns 4.5 4.5 4.5 Fig.6 Fig.6 Fig.6 UNIT VCC (V) WAVEFORMS TEST CONDITIONS December 1990 6 Philips Semiconductors Product specification 9-bit odd/even parity generator/checker AC WAVEFORMS 74HC/HCT280 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the data input (In) to parity outputs (E, O) propagation delays and the output transition time. APPLICATION INFORMATION For a single-chip 16-bit even/odd parity generator/checker, see PC74HC/HCT7080. Fig.7 Cascaded 17-bit odd/even parity generator/checker. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". December 1990 7 |
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