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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT299 8-bit universal shift register; 3-state Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 8-bit universal shift register; 3-state FEATURES * Multiplexed inputs/outputs provide improved bit density * Four operating modes: - shift left - shift right - hold (store) - load data * Operates with output enable or at high-impedance OFF-state (Z) * 3-state outputs drive bus lines directly * Can be cascaded for n-bits word length * Output capability: bus driver (parallel I/Os), standard (serial outputs) * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT299 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns 74HC/HCT299 The 74HC/HCT299 contain eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and hold operations. The type of operation is determined by the mode select inputs (S0 and S1), as shown in the mode select table. All flip-flop outputs have 3-state buffers to separate these outputs (I/O0 to I/O7) such, that they can serve as data inputs in the parallel load mode. The serial outputs (Q0 and Q7) are used for expansion in serial shifting of longer words. A LOW signal on the asynchronous master reset input (MR) overrides the Sn and clock (CP) inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock pulse. Inputs can change when the clock is either state, provided that the recommended set-up and hold times, relative to the rising edge of CP, are observed. A HIGH signal on the 3-state output enable inputs (OE1 or OE2) disables the 3-state buffers and the I/On outputs are set to the high-impedance OFF-state. In this condition, the shift, hold, load and reset operations can still occur. The 3-state buffers are also disabled by HIGH signals on both S0 and S1, when in preparation for a parallel load operation. TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay CP to Q0, Q7 CP to I/On tPHL fmax CI CI/O CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V December 1990 2 ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V MR to Q0, Q7 or I/On maximum clock frequency input capacitance input/output capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 20 20 20 50 3.5 10 120 19 19 23 46 3.5 10 125 ns ns ns MHz pF pF pF HCT UNIT Philips Semiconductors Product specification 8-bit universal shift register; 3-state PIN DESCRIPTION PIN NO. 1, 19 2, 3 7, 13, 6, 14, 5, 15, 4, 16 8, 17 9 10 11 12 18 20 SYMBOL S0, S1 OE1, OE2 I/O0 to I/O7 Q0, Q7 MR GND DSR CP DSL VCC NAME AND FUNCTION mode select inputs 3-state output enable inputs (active LOW) 74HC/HCT299 parallel data inputs or 3-state parallel outputs (bus driver) serial outputs (standard output) asynchronous master reset input (active LOW) ground (0 V) serial data shift-right input clock input (LOW-to-HIGH, edge-triggered) serial data shift-left input positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification 8-bit universal shift register; 3-state 74HC/HCT299 Fig.4 Functional diagram. MODE SELECT TABLE INPUTS RESPONSE MR L H H H H Notes 1. H = HIGH voltage level L = LOW voltage level X = don't care = LOW-to-HIGH CP transition S1 X H L H L S0 X H H L L CP X X asynchronous reset; Q0-Q7 = LOW parallel load; I/On Qn shift right; DSR Q0, Q0 Q1 etc. shift left; DSL Q7, Q7 Q6 etc. hold December 1990 4 Philips Semiconductors Product specification 8-bit universal shift register; 3-state 74HC/HCT299 Fig.5 Logic diagram. December 1990 5 Philips Semiconductors Product specification 8-bit universal shift register; 3-state DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver (parallel I/Os) standard (serial outputs) ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER 74HC/HCT299 TEST CONDITIONS UNIT V WAVEFORMS CC (V) ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 +25 min. typ. max. -40 to +85 min. max. 250 50 43 250 50 43 250 50 43 195 39 33 165 33 28 230 46 39 195 39 33 75 15 13 95 19 16 100 20 17 100 20 17 -40 to +125 min. max. 300 60 51 300 60 51 300 60 51 235 47 40 195 39 33 280 56 48 235 47 40 90 18 15 110 22 19 120 24 20 120 24 20 tPHL/ tPLH propagation delay CP to Q0, Q7 tPHL/ tPLH propagation delay CP to I/On tPHL/ propagation delay MR to Q0, Q7 or I/On 3-state output enable time OEn to I/On 3-state output enable time OEn to I/On 3-state output disable time OEn to I/On 3-state output disable time OEn to I/On 66 24 19 66 24 19 66 24 19 50 18 14 41 15 12 66 24 19 55 20 16 14 5 4 19 7 6 80 16 14 80 16 14 17 6 5 19 7 6 200 40 34 200 40 34 200 40 34 155 31 26 130 26 22 185 37 31 155 31 26 60 12 10 75 15 13 ns Fig.6 ns Fig.7 tPZH ns Fig.9 tPZL ns Fig.9 tPHZ ns Fig.9 tPLZ ns Fig.9 tTHL/ tTLH output transition time bus driver (I/On) tTHL/ tTLH output transition time standard (Q0, Q7) tW clock pulse width HIGH or LOW master reset pulse width LOW ns Fig.6 ns Fig.6 ns Fig.6 tW ns Fig.7 December 1990 6 Philips Semiconductors Product specification 8-bit universal shift register; 3-state 74HC/HCT299 Tamb (C) 74HC SYMBOL PARAMETER TEST CONDITIONS WAVEFORMS UNIT V CC (V) ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.7 +25 min. typ. max. -40 to +85 min. 5 5 5 125 25 21 125 25 21 155 31 26 0 0 0 0 0 0 4.0 20 24 max. -40 to +125 min. 5 5 5 150 30 26 150 30 26 190 38 32 0 0 0 0 0 0 3.4 17 20 max. trem removal time MR to CP set-up time DSR, DSL to CP set-up time S0, S1 to CP set-up time I/On to CP hold time I/On, DSR, DSL to CP hold time S0, S1 to CP maximum clock pulse frequency 5 5 5 100 20 17 100 20 17 125 25 21 0 0 0 0 0 0 5.0 25 29 -14 -5 -4 33 12 10 33 12 10 39 14 11 -14 -5 -4 -28 -10 -8 15 45 54 tsu ns Fig.6 tsu ns Fig.8 tsu ns Fig.6 th ns Fig.6 th ns Fig.8 fmax MHz Fig.6 December 1990 7 Philips Semiconductors Product specification 8-bit universal shift register; 3-state DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver (parallel I/Os) standard (serial outputs) ICC category: MSI Note to HCT types 74HC/HCT299 The value of additional quiescent supply current (ICC) for unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT I/On DSR, DSL CP, S0 MR, S1 OEn UNIT LOAD COEFFICIENT 0.25 0.25 0.60 0.25 0.30 December 1990 8 Philips Semiconductors Product specification 8-bit universal shift register; 3-state AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. 74HC/HCT299 TEST CONDITIONS UNIT +25 typ. 22 22 27 19 24 20 5 7 20 20 10 25 32 0 0 25 10 11 2 14 18 -11 -17 42 max. 37 37 46 30 37 32 12 15 -40 to +85 min. max. 46 46 58 38 46 40 15 19 25 25 9 31 40 0 0 20 -40 to +125 min. max. 56 56 69 45 56 48 18 22 30 30 11 38 48 0 0 17 VCC WAVEFORMS (V) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.6 Fig.6 Fig.7 Fig.9 Fig.9 Fig.9 Fig.6 Fig.6 Fig.6 Fig.7 Fig.7 Fig.6 Fig.8 Fig.6 Fig.8 Fig.6 tPHL/ tPLH tPHL/ tPLH tPHL tPZH/ tPZL tPHZ tPLZ tTHL/ tTLH tTHL/ tTLH tW tW trem tsu tsu th th fmax propagation delay CP to Q0, Q7 propagation delay CP to I/On propagation delay MR to Q0, Q7 or I/On 3-state output enable time OEn to I/On 3-state output disable time OEn to I/On 3-state output disable time OEn to I/On output transition time bus driver (I/On) output transition time standard (Q0, Q7) clock pulse width HIGH or LOW master reset pulse width LOW removal time MR to CP set-up time I/On, DSR, DSL to CP set-up time S0, S1 to CP hold time I/On, DSR, DSL to CP hold time S0, S1 to CP maximum clock pulse frequency ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz December 1990 9 Philips Semiconductors Product specification 8-bit universal shift register; 3-state AC WAVEFORMS 74HC/HCT299 handbook, full pagewidth I/O n ,DSR,DSL INPUTS VM (1) t su th 1/ f max V M (1) tW t PHL The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. I/O n,Q 0 ,Q 7 OUTPUTS MBA335 t su th CP INPUT t PLH (1) VM t THL t TLH Fig.6 Waveforms showing the clock (CP) to output (I/On, Q0, Q7) propagation delays, the clock pulse width, the I/On, DSR and DSL to CP set-up and hold times, the output transition times and the maximum clock frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the master reset (MR) pulse width (LOW), the master reset to output (I/On, Q0, Q7) propagation delays and the master reset to clock (CP) removal time. December 1990 10 Philips Semiconductors Product specification 8-bit universal shift register; 3-state 74HC/HCT299 (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the set-up and hold times from the mode control inputs (S0, S1) to the clock (CP). (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the 3-state enable and disable times for OEn inputs. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". December 1990 11 |
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