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BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
Integrated Device Technology, Inc.
IDT71B74
FEATURES:
* High-speed address to MATCH comparison time -- Commercial: 8/10/12/15/20ns (max.) * High-speed address access time -- Commercial: 8/10/12/15/20ns (max.) * High-speed chip select access time -- Commercial: 6/7/8/10ns (max.) * Power-ON Reset Capability * Low power consumption -- 830mW (typ.) for 12ns parts -- 880mW (typ.) for 10ns parts -- 920mW (typ.) for 8ns parts * Produced with advanced BiCMOS high-performance technology * Input and output directly TTL-compatible * Standard 28-pin plastic DIP and 28-pin SOJ (300 mil)
DESCRIPTION:
The IDT71B74 is a high-speed cache address comparator subsystem consisting of a 65,536-bit static RAM organized as 8K x 8 and an 8-bit comparator. A single IDT71B74 can map 8K cache words into a 2 megabyte address space by using the 21 bits of address organized with the 13 LSBs for the cache address bits and the 8 higher bits for cache data bits. Two IDT71B74s can be combined to provide 29 bits of address comparison, etc. The IDT71B74 also provides a single RAM clear control, which clears all words in the internal RAM to zero when activated. This allows the tag bits for all locations to be cleared at power-on or system-reset, a requirement for cache comparator systems. The IDT71B74 can also be used as a resettable 8K x 8 high-speed static RAM. The IDT71B74 is fabricated using IDT's high-performance, high-reliability BiCMOS technology. Address access times as fast as 8ns, chip select times of 6ns and address-to-match times of 8ns are available. The MATCH pin of several IDT71B74s can be wired-ORed together to provide enabling or acknowledging signals to the data cache or processor, thus eliminating logic delays and increasing system throughput.
FUNCTIONAL BLOCK DIAGRAM
A0 ADDRESS DECODER A12 65,536-BIT MEMORY ARRAY VCC GND
RESET
I/O0 - 7
8
I/O CONTROL
WE OE CS
CONTROL LOGIC
EQUAL
MATCH (OPEN DRAIN)
3013 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc.
AUGUST 1996
DSC-3013/4
14.1
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IDT71B74 BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
RESET
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25
VCC
WE
A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O 0 I/O 1 I/O 2 GND
P28-2 SO28-5
24 23 22 21 20 19 18 17 16 15
MATCH A8 A9 A11
OE
A10
CS
I/O 7 I/O 6 I/O 5 I/O 4 I/O 3
3013 drw 02
DIP/SOJ TOP VIEW
TRUTH TABLE(1, 2)
WE CS OE RESET
ABSOLUTE MAXIMUM RATINGS(1)
MATCH HIGH HIGH LOW HIGH HIGH HIGH I/O -- Hi-Z DIN DIN DOUT DIN Function Reset all bits to LOW Deselect chip No MATCH MATCH Read Write TA TBIAS TSTG PT IOUT Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Com'l. -0.5 to +7.0 0 to +70 -55 to +125 -55 to +125 1.0 50 Unit V C C C W mA
X X H H H L
X H L L L L
X X H H L X
L H H H H H
NOTES: 3013 tbl 01 1. H = VIH, L = VIL, X = DON'T CARE 2. HIGH = High-Z (pulled up by an external resistor), and LOW = VOL.
PIN DESCRIPTIONS
Pin Names A0-12 I/O0-7
CS RESET
Description Address Data Input/Output Chip Select Memory Reset Data/Memory Match (Open Drain) Write Enable Output Enable Ground Power
3013 tbl 02
NOTES: 3013 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V.
CAPACITANCE
(TA = +25C, f = 1.0MHz, SOJ Package)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 3dV VOUT = 3dV Max. Unit 6 7 pF pF
MATCH
WE OE
GND VCC
NOTE: 3013 tbl 04 1. This parameter is determined by device characterization, but is not production tested.
14.1
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IDT71B74 BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH VIHR VIL Parameter Supply Voltage Supply Voltage Input HIGH Voltage
RESET
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Max. Unit 5.5 0 6.0
(4)
Min. 4.5 0
(1)
Typ. 5.0 0 -- -- --
Grade Commercial
Ambient Temperature 0C to +70C
GND 0V
VCC 5V 10%
3013 tbl 06
V V V V V
2.2 2.5
(2) (3)
Input Voltage
6.0 0.8
Input LOW Voltage
-0.5
NOTES: 3013 tbl 05 1. All inputs except RESET. 2. When using bipolar devices to drive the RESET input, a pullup resistor of 1k-10k is usually required to assure this voltage. 3. VIL (min.) = -1.5V for pulse width less than 10ns, once per cycle. 4. VTERM must not exceed VCC + 0.5V.
DC ELECTRICAL CHARACTERISTICS(1)
(VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC - 0.2V)
Symbol ICC Parameter Dynamic Operating Current Outputs Open, VCC = Max., f = fMAX(2)
WE WE
71B74S8 = VLC = VHC 230 210
71B74S10 210 200
71B74S12 200 170
71B74S15 190 160
71B74S20 180 150
Unit mA mA
3013 tbl 07
NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC, only input addresses are cycling at fMAX.
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE (VCC = 5.0V 10%)
IDT71B74S Symbol |ILI| |ILO| VOL Parameter Input Leakage Current Output Leakage Current Output LOW Voltage Test Condition VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC IOL = 22mA MATCH IOL = 18mA MATCH IOL = 10mA, VCC = Min. (Except MATCH) IOL = 8mA, VCC = Min. (Except MATCH) VOH Output HIGH Voltage IOH = -4mA, VCC = Min. (Except MATCH) Min. -- -- -- -- -- -- 2.4 Max. 5 5 0.5 0.4 0.5 0.4 -- V
3013 tbl 08
Unit A A V
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1, 2, and 3
3013 tbl 09
1.5V 50 DATAOUT
3013 drw 03
Figure 1. AC Test Load
14.1
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IDT71B74 BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
7 6 TADM (Typical, ns) 5 4 3 2 1
*
DATAOUT
5V 480
* * * *
*
255
5pF*
3013 drw 05
*
*Includes scope and jig.
8 20 40 60 80 100 120 140 160 180 200 CAPACITANCE (pF)
Figure 1A. Lumped Capacitive Load Typical Derating Curve
3013 drw 04
Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ)
7 6
5V RL MATCH
*
TAA (Typical, ns) 5 4 3 2 1
* * * *
*
RL = 200 (COM'L.) = 270 (MIL.)
Figure 3. AC Test Load for MATCH
*
3013 drw 06
8 20 40 60 80 100 120 140 160 180 200 CAPACITANCE (pF)
3013 drw 07
Figure 3A. Lumped Capacitive Load Typical Derating Curve
DATA ADDR
13
32 32 8
D0-D31 A0-A31 7 A17-A24
DATA LOGIC 1
8 A25-A31 8 9 8 9 8
ADDR
5V
80486 32-BIT MICROPROCESSOR
A4-A16
IDT71B74 CACHETAG RAM MATCH
IDT71B74 CACHETAG RAM MATCH
IDT71256 CACHEDATA RAM
256
256
256
MAIN MEMORY
RL(2) RDY
CLEAR
MEMORY READ/WRITE CONTROL LOGIC
CACHE READ/WRITE MAIN MEMORY READ/WRITE
3013 drw 08
NOTES: 1. For more information refer to IDT Application Notes AN-07 and AN-78 and Technical Notes TN-11 and TN-13. 2. RL = 200. Figure 4. Example of Cache Memory System Block Diagram
14.1
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IDT71B74 BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%)
71B74S8 Symbol Read Cycle tRC tAA tACS tCLZ tOE tOLZ
(1) (1) (1) (1)
71B74S10 Min. Max.
71B74S12 Min. Max.
71B74S15 Min. Max.
71B74S20 Min. Max. Unit
Parameter
Min.
Max.
Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low-Z Output Enable to Output Valid Output Enable to Output in Low-Z Chip Select to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change
8 -- -- 2 -- 2 -- -- 3
-- 8 6 -- 5 -- 4 4 --
10 -- -- 2 -- 2 -- -- 3
-- 10 7 -- 6 -- 5 4 --
12 -- -- 2 -- 2 -- -- 3
-- 12 8 -- 6 -- 5 5 --
15 -- -- 3 -- 2 -- -- 3
-- 15 8 -- 8 -- 7 5 --
20 -- -- 3 -- 2 -- -- 3
-- 20 10 -- 9 -- 8 8 --
ns ns ns ns ns ns ns ns ns
3013 tbl 10
tCHZ
tOHZ tOH
NOTE: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC ADDRESS tAA
OE
t OH
tOE tOLZ (5)
CS
t OHZ (5)
tACS (3) t CLZ (5) DATAOUT DATAOUT VALID t CHZ (5)
3013 drw 09
TIMING WAVEFORM OF READ CYCLE NO. 2 (1, 2, 4)
tRC ADDRESS tAA tOH DATAOUT
NOTES: 1. WE is HIGH for Read cycle. 2. Device is continuously selected, CS is LOW. 3. Address valid prior to or coincident with CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is continuously active, OE is LOW. 5. Transition is measured 200mV from steady state.
tOH DATAOUT VALID
3013 drw 10
14.1
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IDT71B74 BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%)
71B74S8 Symbol Write Cycle tWC tCW tAW tAS tWP tWR tWHZ tDW tDH tOW
(1) (1)
71B74S10 Min. Max.
71B74S12 Min. Max.
71B74S15 Min. Max.
71B74S20 Min. Max. Unit
Parameter
Min.
Max.
Write Cycle Time Chip Select to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Write Recovery Time (CS, WE) Write Enable to Output in High-Z Data Valid to End of Write Data Hold from Write Time Output Active from End of Write
8 7 7 0 7 0 -- 5 0 2
-- -- -- -- -- -- 5 -- -- --
10 8 8 0 8 0 -- 5 0 2
-- -- -- -- -- -- 5 -- -- --
12 9 9 0 9 0 -- 6 0 2
-- -- -- -- -- -- 5 -- -- --
15 10 10 0 10 0 -- 8 0 2
-- -- -- -- -- -- 5 -- -- --
20 15 15 0 15 0 -- 10 0 2
-- -- -- -- -- -- 5 -- -- --
ns ns ns ns ns ns ns ns ns ns
3013 tbl 11
NOTE: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE Controlled Timing, OE HIGH During Write)(1, 6) WE
tWC ADDRESS
OE
CS
t AW t AS
WE
t WR (3)
t WHZ (8,9) DATAOUT t OHZ DATAIN
(4,9)
t WP (2)
t OW (9)
t DW
t DH DATA VALID
3013 drw 11 NOTES: 1. WE, CS must be inactive during all address transitions. 2. A write occurs during the overlap of a LOW WE and a LOW CS. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. During this period, I/O pins are in the output state and input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. OE is continuously HIGH, OE VIH. If during the WE controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O drivers to turn off and the data to be placed on the bus for the required tDW. If OE is HIGH during the WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW timing. 7. DATAOUT is never enabled, therefore the output is in High-Z state during the entire write cycle. 8. tWHZ is not included if OE remains HIGH during the write cycle. If OE is LOW during the Write Enabled write cycle then tWHZ must be added to tWP and tCW. 9. Transition is measured 200mV from steady state.
14.1
6
IDT71B74 BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS Controlled Timing)(1, 6) CS
tWC ADDRESS
OE
CS
(5)
t CW t AW
(2)
t WR (3)
t AS
WE
t WHZ (8,9) DATAOUT
(7)
tOW (9)
t DW DATA IN DATA VALID
t DH
3013 drw 12
NOTES: 1. WE, CS must be inactive during all address transitions. 2. A write occurs during the overlap of a LOW WE and a LOW CS. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. During this period, I/O pins are in the output state and input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. OE is continuously HIGH, OE VIH. If during the WE controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O drivers to turn off and the data to be placed on the bus for the required tDW. If OE is HIGH during the WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW timing. 7. DATAOUT is never enabled, therefore the output is in High-Z state during the entire write cycle. 8. tWHZ is not included if OE remains HIGH during the write cycle. If OE is LOW during the Write Enabled write cycle then tWHZ must be added to tWP and tCW. 9. Transition is measured 200mV from steady state.
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%)
71B74S8 Symbol Match Cycle tADM tCSM tCSMHI tDAM tOEMHI
(1) (1) (1)
71B74S10 Min. Max.
71B74S12 Min. Max.
71B74S15 Min. Max.
71B74S20 Min. Max. Unit
Parameter
Min.
Max.
Address to MATCH Valid Chip Select to MATCH Valid Chip Select to MATCH HIGH Data Input to MATCH Valid
OE WE
-- -- -- -- -- -- -- 2 2
8 7 7 7 7 7 8 -- --
-- -- -- -- -- -- -- 2 2
10 7 8 8 8 8 10 -- --
-- -- -- -- -- -- -- 2 2
12 8 8 10 10 10 10 -- --
-- -- -- -- -- -- -- 2 2
15 10 8 12 10 10 12 -- --
-- -- -- -- -- -- -- 2 2
20 10 8 12 10 10 15 -- --
ns ns ns ns ns ns ns ns ns
3013 tbl 12
LOW to MATCH HIGH LOW to MATCH HIGH LOW to MATCH HIGH
tWEMHI tRSMHI tMHA tMHD
(1)
RESET
MATCH Valid Hold From Address MATCH Valid Hold From Data
NOTE: 1. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested.
14.1
7
IDT71B74 BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
MATCH TIMING(1)
ADDRESS tADM tCSM
CS
tMHA
tCSMHI
OE
(2)
tOEMHI
WE
(2)
tWEMHI
RESET
(2)
t RSMHI DATA VALID READ DATA t DAM MATCH MATCH NO MATCH
NOTES: 1. It is not recommended to float data and address input pins while the MATCH pin is active. 2. Transition is measured at 200mV from steady state.
VALID MATCH DATA
(2)
t MHD MATCH VALID
3013 drw 13
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%)
71B74S8 Symbol Reset Cycle tRSPW(1) tWERS tRSRC tPORS
(2)
71B74S10 Min. Max.
71B74S12 Min. Max.
71B74S15 Min. Max.
71B74S20 Min. Max. Unit
Parameter
Min.
Max.
Reset Pulse Width
WE
30 5 25 100
-- -- -- --
35 5 25 100
-- -- -- --
35 5 25 100
-- -- -- --
40 5 30 120
-- -- -- --
45 5 30 120
-- -- -- --
ns ns ns ns
3013 tbl 13
HIGH to Reset HIGH
Reset HIGH to WE LOW Power On Reset
NOTES: 1. Recommended duty cycle = 10% maximum. 2. This parameter is guaranteed with the AC Load (Figure 1) by device characterization, but is not production tested.
RESET TIMING
tRSPW
RESET
tRSRC
WE
t WERS
3013 drw 14
14.1
8
IDT71B74 BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
POWER ON RESET TIMING
tPORS VCC
RESET
tRSRC
WE
t WERS
3013 drw 15
5V
IDT71B74 RESET
1K - 10K
IDT71B74 RESET
CMOS GATE
3013 drw 16
BIPOLAR GATE
3013 drw 17
Driving the RESET pin with CMOS logic. Figure 5.
Driving the RESET pin with bipolar logic.
ORDERING INFORMATION
IDT 71B74 Device Type S Power XX Speed X Package X Process/ Temperature Range Blank TP Y 8 10 12 15 20 Commercial (0C to +70C) Plastic DIP (300 mil) (P28-2) SOJ (Small Outline IC, J-bend) (SO28-5) Commercial Only, SOJ Only Commercial Only Commercial Only Commercial Only Commercial Only
Speed in ns
3013 drw 18
14.1
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