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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75108F,75112F,75116F
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The PD75116F offers high-speed operation (tCY = 1.91 s) at a low supply voltage (VDD = 2.7 V) which is not possible with the PD75116. It has the same functions as, and is pin compatible with, the PD75116, allowing low voltage sets to be developed by making efficient use of previously developed and used software resources. Note, however, that the operating voltage range is different from that of the PD75116. A version of the PD75116F with on-chip PROM, the PD75P116*, is also available for evaluation during system development. * There are some differences in electrical specifications between the PD75116F and the PD75P116. Functions are described in detail in the following User's Manual, which should be read when carrying out design work.
PD75116 User's Manual : IEM-922
FEATURES
* PD75116 low voltage high-speed operation product * Instruction execution time
Ta = -40 to +50 C VDD = 2.7 to 5.0 V 1.91 s , 15.3 s (operation at 4.19 MHz) 2 s, 4 s, 32 s (operation at 2 MHz) 1.91 s , 15.3 s (operation at 4.19 MHz) 2 s, 4 s, 32 s (operation at 2 MHz) 0.95 s, 1.91 s, 15.3 s (operation at 4.19 MHz) Ta = -40 to +60 C
VDD = 2.8 to 5.0 V VDD = 4.5 to 5.0 V
* 43 systematically arranged instructions * 8-bit data transfer, compare, operation and increment/decrement instructions * GETI instruction allowing any 2-byte or 3-byte instruction to be implemented in 1 byte * Wide range of input/output ports : 58 ports * 3 on-chip 8-bit timer channels : synchronous/asynchronous (start/stop) * 8-bit serial interface on chip * Programmable threshold port : 4-bit resolution x 4 channels
"Unless there are any particular functional differences, the PD75116F is described in this document as a representative product."
The information in this document is subject to change without notice.
Document No. IC-2810B (O.D.No. IC-8224B) Date Published April 1994P Printed in Japan
The mark 5 shows major revised points.
(c) NEC Corporation 1991
PD75108F,75112F,75116F
ORDERING INFORMATION
Ordering Code Package 64-pin plastic QFP (14 x 12 mm) 64-pin plastic QFP (14 x 12 mm) 64-pin plastic QFP (14 x 20 mm) Quality Grade Standard Standard Standard
PD75108FGF-xxx-3BE PD75112FGF-xxx-3BE PD75116FGF-xxx-3BE
Remarks xxx: ROM code number
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
APPLICATIONS
Cordless telephone subsets, portable radio equipment, pager, etc.
2
PD75108F,75112F,75116F
OVERVIEW OF FUNCTIONS
Item Basic instructions 43
Contents
Instruction cycle
0.95 s, 1.91 s, 15.3 s (VDD = 4.5 to 5.0 V, 4.19 MHz operation) 2 s, 4 s, 32 s (VDD = 2.7 to 5.0 V, 2 MHz operation) 3-stage switching capability 0.95 s (operating at 4.5 to 5.0 V) 1.91 s (operating at 2.7 V ) 8064 x 8 bits (PD75108F)
Minimum instruction execution time
On-chip memory
ROM
12160 x 8 bits (PD75112F) 16256 x 8 bits (PD75116F)
RAM General register Accumulator
512 x 4 bits 4-bits x 8 x 4 banks (memory mapping) 3 accumulators for different manipulated data lengths * 1-bit accumulator (CY), 4-bit acculumalor (A), 8-bit accumulator (XA) Total 58 * CMOS input pins : 10 * CMOS input/output pins (LED direct drive capability) : 32 * Middle-high voltage N-ch open-drain input/output pins : 12 (LED direct drive capability, a pull-up resistor can be incorporated bit-wise.) * Comparator input pins (4-bit precision) :4 * 8-bit timer/event counter x 2 * 8-bit basic interval timer (watchdog timer applicable) * 2 transfer modes * Serial transmission/reception modes * Serial reception mode * LSB top/MSB top switchable External : 3 Internal : 4
Input/output port
Timer/counter
8-bit serial interface
Vector interrupt
Test input Standby
External : 2 * STOP/HALT mode * * * * Various bit manipulation instructions (set, reset, test, Boolean operation) 8-bit data transfer, comparison, operation, increment/decrement instructions 1-byte relative branch instruction GETI instruction that can implement arbitrary 2-byte/3-byte instructions with 1 byte
Instruction set
Others Package
* Bit manipulation memory (bit sequential buffer) on chip * 64-pin plastic QFP (14 x 20 mm)
3
PD75108F,75112F,75116F
CONTENTS
1. 2. 3.
PIN CONFIGURATION (TOP VIEW) ..................................................................................................... BLOCK DIAGRAM .................................................................................................................................. PIN FUNCTIONS ....................................................................................................................................
3.1 3.2 3.3 3.4 3.5 PORT PINS ..................................................................................................................................................... OTHER PINS ................................................................................................................................................... PIN INPUT/OUTPUT CIRCUITS ................................................................................................................... RECOMMENDED CONNECTION OF UNUSED PINS ................................................................................. PRECAUTIONS CONCERNING P00/INT4 PIN AND RESET PIN ...............................................................
6 7 8
8 9 10 11 12
4. 5.
MEMORY CONFIGURATION ................................................................................................................ 13 PERIPHERAL HARDWARE FUNCTIONS .............................................................................................. 18
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 DIGITAL INPUT/OUTPUT PORTS ................................................................................................................ CLOCK GENERATOR ..................................................................................................................................... CLOCK OUTPUT CIRCUIT ............................................................................................................................. BASIC INTERVAL TIMER .............................................................................................................................. TIMER/EVENT COUNTER ............................................................................................................................. SERIAL INTERFACE ....................................................................................................................................... PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT) ............................................................ BIT SEQUENTIAL BUFFER ........................................................................................................................... 18 19 20 21 21 23 25 26
6. 7. 8. 9.
INTERRUPT FUNCTION ........................................................................................................................ 27 STANDBY FUNCTION ........................................................................................................................... 29 RESET FUNCTION ................................................................................................................................. 30 INSTRUCTION SET ................................................................................................................................ 32
10. APPLICATION EXAMPLE ...................................................................................................................... 41
10.1 CORDLESS TELEPHONE (SUBSET) ............................................................................................................ 10.2 DISPLAY PAGER ............................................................................................................................................ 41 42
11. MASK OPTION SELECTION .................................................................................................................. 43 12. ELECTRICAL SPECIFICATIONS ............................................................................................................ 44
12.1 WHEN Ta = -40 to +50 C, VDD = 2.7 to 5.0 V ........................................................................................... 12.2 WHEN Ta = -40 to +60 C, VDD = 2.8 to 5.0 V ........................................................................................... 45 55
4
PD75108F,75112F,75116F
13. CHARACTERISTIC CURVES (REFERENCE) ......................................................................................... 65
14. PACKAGE INFORMATION ..................................................................................................................................... 71
15. RECOMMENDED SOLDERING CONDITIONS ..................................................................................... 73 APPENDIX A. FUNCTIONAL DIFFERENCES AMONG PD751xx SERIES PRODUCTS ....................... 74 APPENDIX B. DEVELOPMENT TOOLS ...................................................................................................... 76 APPENDIX C. RELATED DOCUMENTS ..................................................................................................... 77
5
PD75108,75112F,75116F
1. PIN CONFIGURATION (TOP VIEW)
64-Pin Plastic QFP (14 x 20 mm)
P141
P142
P143
P41 P40 P53 P52 P51 P50 RESET X2 X1 P63 P62 P61 P60 P73 P72 P71 P70 P83 P82
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
64 63 62 61 60 59 58 57 56 55 54 53 52
NC P140
P130
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P42
P43
P30
P31
P32
P33
VDD
P131 P132 P133 P120 P121 P122 P123 P00/INT4 P01/SCK P02/SO P03/SI P20/PTO0 P21/PTO1 P22/PCL P23 T11 T10 PTH00 PTH01
20 21 22 23 24 25 26 27 28 29 30 31 32
PTH03
P13/INT3
P12/INT2
P11/INT1
5 Pin Name
P00-P03 P10-P13 P20-P23 P30-P33 P40-P43 P50-P53 P60-P63 P70-P73 P80-P83 P90-P93 : Port 0 : Port 1 : Port 2 : Port 3 : Port 4 : Port 5 : Port 6 : Port 7 : Port 8 : Port 9 SCK SO SI PTO0, PTO1 PCL PTH00-PTH03 INT2, INT3 TI0, TI1 X1, X2 RESET NC VDD VSS : Serial Clock : Serial Output : Serial Input : Programmable Timer Output : Programmable Clock : Programmable Treshold Input : External Test Input : Timer Input : Clock Oscillation : Reset : No Connection : Positive Power Supply : Ground
INT0, INT1, INT4 : External Vectored Interrupt Input
P120-P123 : Port 12 P130-P133 : Port 13 P140-P143 : Port 14
6
P10/INT0
PTH02
P81 P80
P93
P92
P91
P90
VSS
PD75116FGF-xxx-3BE PD75112FGF-xxx-3BE PD75116FGF-xxx-3BE
2. BLOCK DIAGRAM
BASIC INTERVAL TIMER INTBT TI0 PTO0/P20 TIMER/EVENT COUNTER #0 INTT0 TI1 PTO1/P21 TIMER/EVENT COUNTER #1 INTT1 SI/P03 SO/P02 SCK/P01 SERIAL INTERFACE PROGRAM* COUNTER ALU SP(8) CY
BIT SEQ. BUFFER (16) PORT 0 PORT 1 BANK PORT 2 4 4 P20-P23 4 4 P00-P03 P10-P13
ROM PROGRAM MEMORY 8064 x 8 BITS (PD75108F) 12160 x 8 BITS (PD75112F) 16256 x 8 BITS (PD75116F)
DECODE AND CONTROL
PORT 3 GENERAL REG. PORT 4
P30-P33
4 4
P40-P43
PORT 5 RAM DATA MEMORY 512 x 4 BITS PORT 6 PORT 7
P50-P53 P60-P63
4 4
INTSIO
P70-P73
INT0/P10 INT1/P11 INT2/P12 INT3/P13 INT4/P00 INTERRUPT CONTROL fXX / 2 PROGRAMMABLE THRESHOLD PORT #0 CLOCK OUTPUT CONTROL CLOCK DIVIDER
N
PORT 8
4
P80-P83
PORT 9
4
P90-P93
PD75108F,75112F,75116F
PTH00-PTH03
4
CLOCK GENERATOR
STAND BY CONTROL
CPU CLOCK
PORT 12
4
P120-P123
PORT 13 PCL/P22 X1 X2 VDD VSS RESET PORT 14
4
P130-P133
4
P140-P143
* 7
The PD75108F program counter is composed of 13 bits and the PD75112F/75116F program counter is composed of 14 bits
PD75108F,75112F,75116F
3. PIN FUNCTIONS
3.1 PORT PINS
Pin Name P00 P01 P02 P03 P10 P11
Input/Output Input Input/output Input/output Input
DualFunction Pin INT4 SCK
Function
8-bit I/O
After Reset
I/OCircuit Type *1 B F
4-bit input port (PORT 0). SO SI INT0 INT1 Input P12 P13 P20 *3 P21 *3 Input/output P22 *3 P23 *3 P30 to P33 *3 Input/output PCL -- -- Programmable 4-bit input/output port (PORT 3). Input/output can be specified bit-wise. 4-bit input/output port (PORT 4). 4-bit input/output port (PORT 5). Programmable 4-bit input/output port (PORT 6). Input/output can be specified bit-wise. 4-bit input/output port (PORT 7). 4-bit input/output port (PORT 8). 4-bit input/output port (PORT 9). N-ch open-drain 4-bit input/output port (PORT 12). On-chip pull-up resistor can be specified bit-wise (mask option). Open-drain: +10 V withstand voltage N-ch open-drain 4-bit input/output port (PORT 13). On-chip pull-up resistor can be specified bit-wise (mask option). Open-drain: +10 V withstand voltage N-ch open-drain 4-bit input/output port (PORT 14). On-chip pull-up resistor can be specified bit-wise (mask option). Open-drain: +10 V withstand voltage x INT2 INT3 PTO0 PTO1 4-bit input/output port (PORT 2). 4-bit input port (PORT 1). x
Input E B
Input
B
Input
E
Input
E
P40 to P43 *3 P50 to P53 *3 P60 to P63 *3
Input/output Input/output Input/output
-- -- --
Input Input Input
E E E
P70 to P73 *3 P80 to P83 *3 P90 to P93 *3
Input/output Input/output Input/output
-- -- --
Input Input Input
E E E
P120 to P123 *3
Input/output
--
Input *2
M
P130 to P133 *3
Input/output
--
Input *2
M
P140 to P143 *3
Input/output
--
--
Input *2
M
* 1. 2. 3.
q : Schmitt trigger input Open-drain ... high impedance On-chip pull-up resistor ... high level Direct LED drive capability
8
PD75108F,75112F,75116F
3.2
OTHER PINS
Pin Name PTH00 to PTH03 TI0
Input/Output Input
DualFunction Pin --
Function Variable threshold voltage 4-bit analog input port. External event pulse input to timer/event counter. Or edge detection vectored interrupt input or 1-bit input is also possible.
After Reset
I/O Circuit Type *1 N
Input TI1 PTO0 Input/output PTO1 SCK SO SI Input/output Input/output Input
--
B
P20 Timer/event counter output P21 P01 P02 P03 Serial clock input/output Serial data output Serial data input Edge detection vector interrupt input (detection of both rising and falling edges) Input Input Input F E B Input E
INT4
Input
P00
Input
B
INT0 Input INT1 INT2 Input INT3 PCL Input/output
P10 P11 P12
Edge detection vector interrupt input (detection edge selectable)
Input
B
Edge detection testable input (rising edge detection) P13 P22 Clock output System clock oscillation crystal/ceramic connection pin. When an external clock is used, the clock is input to X1 and the inverted clock is input to X2. System reset input (low-level active). No Connection Positive power supply GND potential
Input
B
Input
E
X1, X2
--
RESET NC*2 VDD VSS
Input --
-- -- -- --
B
* 1. 2.
q : Schmitt trigger input When sharing a print board with PD75P116, NC pin should be connected to VDD.
9
PD75108F,75112F,75116F
3.3 PIN INPUT/OUTPUT CIRCUITS The input/output circuits of each pin of the PD75116F are shown in abbreviated form. Fig. 3-1 Pin Input/Output Circuit List
Type A VDD
Type F
data P-ch IN N-ch Type D output disable Type B
IN/OUT
CMOS standard input buffer Type B
This is an input/output circuit made up of a Type D push-pull output and Type B Schmitt-triggered input. Type M Pull-Up Resistor (Mask Option) N-ch (+6 V Withstand Voltage) VDD IN/OUT
data IN output disable
Schmitt-trigger input with hysteresis characteristic Type D VDD data P-ch OUT Type N
Middle-High Voltage Input Buffer (+6 V Withstand Voltage)
Comparator +
- output disable N-ch VREF (Threshold Voltage)
Push-pull output that can be made highimpedance output (P-ch and N-ch OFF) Type E
data Type D output disable
IN/OUT
Type A
This is an input/output circuit made up of a Type D push-pull output and Type A input buffer.
10
PD75108F,75112F,75116F
3.4
RECOMMENDED CONNECTION OF UNUSED PINS
Pin PTH00 to PTH03 TI0 TI1 P00 P01 to P03 P10 to P13 P20 to P23 P30 to P33 P40 to P43 P50 to P53 Input P60 to P63 P70 to P73 P80 to P83 P90 to P93 P120 to P123 P130 to P133 P140 to P143 NC Leave open * Connect to VSS.
Recommended Connection
Connect to VSS or VDD.
Connect to VSS or VDD. Connect to VSS.
: Connect to VSS or VDD.
Output : Leave open.
*
If a printed board is used with the PD75P116, NC pin should be connected to VDD directly.
11
PD75108F,75112F,75116F
3.5 PRECAUTIONS CONCERNING P00/INT4 PIN AND RESET PIN In addition to the functions shown in 3.1 and 3.2, the P00/INT4 pin and RESET pin are also used to set the test mode for testing internal PD75116F operation (for IC testing). The test mode is set when a voltage greater than VDD is applied to either of these pins. Consequently, if noise exceeding VDD is applied during normal operation, the test mode may be entered, making it impossible for normal operation to continue. If, for example, inter-wiring noise is applied to the P00/INT4 or RESET pin due to the length of the wiring from these pins, and the pin voltage exceeds VDD, misoperation may result. Wiring should therefore be carried out so that interwiring noise is suppressed as far as possible. If it is completely impossible to suppress noise, noise prevention measures should be taken using an external component as shown below.
q
Diode with small VF (0.3 V or less) connected between P00/INT4 or RESET and VDD
VDD
q
Capacitor connected between P00/INT4 or RESET and VDD
VDD
Diode with small VF
VDD P00/INT4, RESET
VDD P00/INT4, RESET
12
PD75108F,75112F,75116F
4. MEMORY CONFIGURATION
* Program memory (ROM) : 8064 x 8 bits (0000H to 1F7FH) : PD75108F 12160 x 8 bits (0000H to 2F7FH) : PD75112F 16256 x 8 bits (0000H to 3F7FH) : PD75116F * 0000H to 0001H : Vector table in which a program start address after reset is written.
* 0002H to 000BH : Vector table in which program start addresses after interruption are written. * 0020H to 007FH : Table area referred by GETI instruction * Data memory * Data area : 512 x 4 bits (000H to 1FFH) * Peripheral hardware area : 128 x 4 bits (F80H to FFFH)
13
PD75108F,75112F,75116F
Fig. 4-1 Program Memory Map (PD75108F)
Address 7 0000H 6 5 0 0 Internal Reset Start Address (High-Order 5 Bits) Internal Reset Start Address (Low-Order 8 Bits) 0002H MBE RBE 0 INTBT/INT4 Start Address INTBT/INT4 Start Address 0004H MBE RBE 0 INT0/INT1 Start Address INT0/INT1 Start Address 0006H MBE RBE 0 INTSIO Start Address INTSIO Start Address 0008H MBE RBE 0 INTT0 Start Address INTT0 Start Address 000AH MBE RBE 0 INTT1 Start Address INTT1 Start Address (High-Order 5 Bits) (Low-Order 8 Bits) (High-Order 5 Bits) (Low-Order 8 Bits) (High-Order 5 Bits) (Low-Order 8 Bits) (High-Order 5 Bits) (Low-Order 8 Bits) (High-Order 5 Bits) (Low-Order 8 Bits) CALLF ! faddr Instruction Entry Address BRCB ! caddr Instruction Branch Address CALL ! addr Instruction Subroutine Entry Address MBE RBE
BR ! addr Instruction Branch Address
BR $ addr Instruction Relative Branch Address -15 to -1, +2 to +16
0020H GETI Instruction Reference Table 007FH 0080H
07FFH 0800H
Branch Destination Address and Subroutine Entry Address by GETI Instruction
0FFFH 1000H BRCB !caddr Instruction Branch Address 1F7FH
Remarks
Apart from the above instructions, branching is possible to an address at which only the PC low-order 8 bits have been changed by the BR PCDE or BR PCXA instruction.
14
PD75108F,75112F,75116F
Fig. 4-2 Program Memory Map (PD75112F)
Address 7 0000H MBE 6 RBE Internal Reset Start Address (High-Order 6 Bits) Internal Reset Start Address (Low-Order 8 Bits) 0002H MBE RBE INTBT/INT4 Start Address INTBT/INT4 Start Address 0004H MBE RBE INT0/INT1 Start Address INT0/INT1 Start Address 0006H MBE RBE INTSIO Start Address INTSIO Start Address 0008H MBE RBE INTT0 Start Address INTT0 Start Address 000AH MBE RBE INTT1 Start Address INTT1 Start Address (High-Order 6 Bits) (Low-Order 8 Bits) (High-Order 6 Bits) (Low-Order 8 Bits) (High-Order 6 Bits) (Low-Order 8 Bits) (High-Order 6 Bits) (Low-Order 8 Bits) (High-Order 6 Bits) (Low-Order 8 Bits) CALLF ! faddr Instruction Entry Address BRCB ! caddr Instruction Branch Address CALL ! addr Instruction Subroutine Entry Address 0
BR ! addr Instruction Branch Address
BR $ addr Instruction Relative Branch Address -15 to -1, +2 to +16
0020H GETI Instruction Reference Table 007FH 0080H
07FFH 0800H
Branch Destination Address and Subroutine Entry Address by GETI Instruction
0FFFH 1000H BRCB !caddr Instruction Branch Address 1FFFH 2000H BRCB !caddr Instruction Branch Address 2F7FH
Remarks
Apart from the above instructions, branching is possible to an address at which only the PC low-order 8 bits have been changed by the BR PCDE or BR PCXA instruction.
15
PD75108F,75112F,75116F
Fig. 4-3 Program Memory Map (PD75116F)
Address 7 0000H MBE 6 RBE Internal Reset Start Address (High-Order 6 Bits) Internal Reset Start Address (Low-Order 8 Bits) 0002H MBE RBE INTBT/INT4 Start Address INTBT/INT4 Start Address 0004H MBE RBE INT0/INT1 Start Address INT0/INT1 Start Address 0006H MBE RBE INTSIO Start Address INTSIO Start Address 0008H MBE RBE INTT0 Start Address INTT0 Start Address 000AH MBE RBE INTT1 Start Address INTT1 Start Address (High-Order 6 Bits) (Low-Order 8 Bits) (High-Order 6 Bits) (Low-Order 8 Bits) (High-Order 6 Bits) (Low-Order 8 Bits) (High-Order 6 Bits) (Low-Order 8 Bits) (High-Order 6 Bits) (Low-Order 8 Bits) CALLF ! faddr Instruction Entry Address BRCB ! caddr Instruction Branch Address CALL ! addr Instruction Subroutine Entry Address 0
BR ! addr Instruction Branch Address
BR $ addr Instruction Relative Branch Address -15 to -1, +2 to +16
0020H GETI Instruction Reference Table 007FH 0080H
07FFH 0800H
0FFFH 1000H
Branch Destination Address and Subroutine Entry Address by GETI Instruction BRCB !caddr Instruction Branch Address BRCB !caddr Instruction Branch Address BRCB !caddr Instruction Branch Address
1FFFH 2000H
2FFFH 3000H
3F7FH
Remarks
Apart from the above instructions, branching is possible to an address at which only the PC low-order 8 bits have been changed by the BR PCDE or BR PCXA instruction.
16
PD75108F,75112F,75116F
Fig. 4-4 Data Memory Map
Data Memory General Register Area 000H (32 x 4) 01FH
Memory Bank
Bank 0
Data Area Static RAM (512 x 4)
Stack Area 256 x 4
0FFH 100H 256 x 4 1FFH Bank 1
Not On-Chip
F80H
Peripheral Hardware Area
128 x 4
Bank 15
FFFH
17
PD75108F,75112F,75116F
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 DIGITAL INPUT/OUTPUT PORTS
There are the following three digital input/output ports. * CMOS input (PORT0, PORT1) : 8
* CMOS input/output (PORT2 to PORT9) : 32 * N-ch open-drain input/output (PORT12 to PORT14) : 12 Total : 52
Table 5-1 List of Input/Output Pin Manipulation Commands
Port Name
Function
Operation/Features
Remarks These pins are shared with SI, SO, SCK, INT0 to INT4.
PORT 0 4-bit input PORT 1 PORT 3
Regardless of the operating mode of the shared pin, reading or test is always possible.
Can be set in the input or output bit-wise. PORT 6 PORT 2 PORT 4 PORT 5 PORT 7 PORT 8 PORT 9 PORT12 4-bit input/output * PORT13 PORT14 (N-ch open-drain +10 V withstand voltage) Can be set to input or output mode as a 4-bit unit. Ports 12 and 13 are paired and data input/ output is possible as an 8-bit unit. On-chip pull-up resistor specifiable bit-wise by mask option.
4-bit input/output *
Can be set in the input or output mode as a 4bit unit. Ports 4 and 5, 6 and 7, and 8 and 9 are paired and data input/output is possible as an 8-bit unit.
Port 2, PT00, PT01, and PCL share the same pins.
*
Can drive a LED directly.
18
PD75108,75112F,75116F
5.2
CLOCK GENERATOR
(1) Clock generator configuration This is the circuit which generates various kinds of clock supplied to the CPU and peripheral hardware to control the CPU operating mode. This circuit can also change the instruction execution time. * 0.95 s/1.91 s/15.3 s (4.19 MHz operation) Fig. 5-1 Clock Generator Block Diagram
* Basic Interval Timer (BT) * Clock Output Circuit * Timer/Event Counter * Serial Interface X1 1/8 to 1/4096 System Clock Oscillation Circuit X2 fXX or fX Frequency Divider 1/2 1/16 Oscillation Stop Frequency Divider 1/4
Selector
* CPU * Clock Output Circuit
PCC PCC0
Internal Bus
PCC1 4 HALT * STOP * PCC2, PCC3 Clear PCC2 PCC3 R Q HALT F/F S
STOP F/F Q S
Wait Release Signal from BT
RESET Signal R Standby Release Signal from Interrupt Control Circuit
Remarks
1. 2. 3. 4. 5. 6.
fXX = Crystal/ceramic oscillator frequency fX = External clock frequency
= CPU Clock
* indicates instruction execution PCC : Processor clock control register One clock cycle (tCY) is one machine cycle. See "AC CHARACTERISTICS" in 12. "ELECTRICAL SPECIFICATIONS" for tCY.
19
PD75108F,75112F,75116F
5.3
CLOCK OUTPUT CIRCUIT
The clock output circuit is a circuit which outputs a clock pulse from P22/PCL and is used to supply clock pulses to remote control outputs or peripheral LSI's. * Clock output (PCL) : , 524 kHz, 262 kHz (4.19 MHz operation) Fig. 5-2 Configuration of Clock Output Circuit
From Clock Generator
Output Buffer fXX/2
3
Selector P22/PCL
fXX/2
4
PORT2.2 CLOM3 0 CLOM1 CLOM0 CLOM P22 Output Latch
Bit 2 of PMGB Bit Specified in Port 2 Input/Output Mode
4 Internal Bus
20
PD75108,75112F,75116F
5.4
BASIC INTERVAL TIMER
The basic interval timer includes the following functions. * It operates as an interval timer which generates reference time interrupts. * It can be applied as a watchdog timer which detects when a program is out of control. * Selects and counts wait times when the standby mode is released. * It reads count contents. Fig. 5-3 Basic Interval Timer Configuration
From Clock Generator fXX/2
5
Clear
Clear
fXX/2
7
MPX fXX/2 fXX/2
9
Basic Interval Timer (8-Bit Frequency Divider)
Set
BT Interrupt Request Flag
12
BT
IRQBT
Vector Interrupt Request Signal
3 Wait Release Signal during Standby Release
BTM3
BTM2
BTM1
BTM0
BTM
*SET1
4 Internal Bus
8
Remarks
* indicates instruction execution.
5.5 TIMER/EVENT COUNTER The PD75116F incorporates two internal timer/event counter channels. Timer/event counter channel 0 and channel 1 differ only in selectable count pulse (CP) and clock supply function to serial interface and are the same in other configurations and functions. The functions of the timer/event counter are as follows. * Operates as a programmable interval timer. * Outputs square waves in the desired frequency to the PTOn pin. * Operates as an event counter. * Use of TIn pin as an external interrupt input pin. * Divides the TIn pin input into N divisions and outputs it to the PTOn pin (frequency divider operation). * Supplies a serial shift clock to the serial interface circuit. (channel 0 only) * Count status read function.
21
22 Fig. 5-4 Timer/Event Counter Block Diagram (n = 0, 1)
Internal Bus SET1 8 *1
TMn
8 8 Modulo Register (8) TOFn TMODn TOEn TO Enable Flag TOn PORT2.n Bit 2 of PGMB Port 2 P2n Input/ Output Output Latch Mode To Serial Interface*3 TO Selector P2n/PTOn Output Buffer Edge Detector INTTn (IRQTn Set Signal)
TMn7 TMn6 TMn5 TMn4 TMn3 TMn2 TMn1 TMn0
TIn
8 Comparator (8)
Match TOUT F/F
Input Buffer TIn *2 From Clock Generator MPX
8 Tn Count Register (8) CP Clear Timer Operation Start RESET
TMn1
TMn0
IRQTn Clear Signal
PD75108F,75112F,75116F
* 1. SET1 : Instruction execution. 2. For details, see Fig. 5-1. 3. The serial interface signal is output only from timer/event counter channel 0.
PD75108,75112F,75116F
5.6
SERIAL INTERFACE
The PD75116F incorporates the clocked 8-bit serial interface. There are the following two modes of serial interface. * 3-wire serial I/O mode (MSB-first/LSB-first switchable) * Operation stop mode In the 3-wire serial I/O mode, the PD75116F can be connected with the 75X series, 78K series and various kinds of I/O devices.
23
24 Fig. 5-5 Serial Interface Block Diagram
Internal Bus 8 8 SIO0 P03/SI Shift Registor (8) SIO7 SIO SIOM7 SIOM6 SIOM5 SIOM4 SIOM3 SIOM2 SIOM1 SIOM0 8 SET1 * SIOM P02/SO Serial Clock Counter (3) Overflow INTSIO IRQSIO Set Signal IRQSIO Clear Signal Clear P01/SCK R Q S Serial Start
PD75108F,75112F,75116F
fxx/2 MPX fxx/2
4
10
TOF0 (from Timer Channel 0)
* SET1 : instruction execution
PD75108,75112F,75116F
5.7
PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT)
The PD75116F is provided with 4-bit analog input pins (PTH00 to PTH03) for which the threshold voltage can be changed. These pins have a configuration as shown in Fig. 5-6. The threshold voltage (VREF) can be selected in 16 ways (VDD x ------ -- VDD x ------) and analog signals can be 16 16 directly input. This port can also be used as a digital signal input port by selecting VDD x 7.5/16 as VREF. Fig. 5-6 Programmable Threshold Port Block Diagram
Input Buffer PTH00 + Programmable Threshold Port Input Latch (4)
0.5 15.5
PTH01
+ -
PTH02
+ -
PTH03
+ Operation Stopped
PTH0
VDD PTHM7 1 2R R R MPX VREF PTHM4 8 PTHM3 1 2R 4 PTHM2 PTHM1 PTHM0 PTHM PTHM6 PTHM5
Internal Bus
25
PD75108F,75112F,75116F
5.8
BIT SEQUENTIAL BUFFER ****** 16 BITS
Bit manipulation of the bit sequential buffer is the bit manipulation special data memory. Since, in particular, the bit manipulation can easily be performed by changing sequentially address and bit specification, it is convenient when processing data comprising a large number of bits bit-wise. Fig. 5-7 Bit Sequential Buffer Format
Address Bit Symbol 3 FC3H 2 1 0 3 FC2H 2 1 BSB2 0 3 FC1H 2 1 0 3 FC0H 2 1 0
BSB3
BSB1
BSB0
L Register L = F
L=CL=B INCS L
L=8L=7 DECS L
L=4 L=3
L=0
Remarks
In pmem. @L addressing, the specified bit moves according to the L register.
26
PD75108F,75112F,75116F
6. INTERRUPT FUNCTION
The PD75116F has 7 interrupt sources. Multiple interrupts with priority is are also possible. Two test sources are also provided. The test sources are edge detection testable inputs. Table 6-1 Interrupt Sources
Interrupt Source
Internal/External
Interrupt Order*1
Vector Interrupt Request Signal (Vector Table Address)
INTBT (standard time interval signal from basic interval timer) INT4 (both rising edge and falling edge detection) (rising edge and falling edge detection selection)
Internal 1 External External 2 External Internal 3 VRQ1 (0002H)
INT0 INT1
VRQ2 (0004H) VRQ3 (0006H) VRQ4 (0008H) VRQ5 (000AH)
INTSIO (serial data transfer end signal) INTT0 (match signal from timer/event counter# 0 or TI0 input edge detection) (match signal from timer/event counter# 1 or TI1 input edge detection)
Internal/external
4
INTT1
Internal/external
5
INT2*2 (rising edge detection) External INT3*2 (rising edge detection)
Testable input signal (Set IRQ2 and IRQ3)
*
1. The interrupt order is the priority order when multiple interrupt requests are generated simultaneously. 2. INT2 and INT3 are of test sources . These are affected by interrupt enable flags in the same way as interrupt sources, but do not generate vector interrupts. The PD75116F interrupt control circuit has the following functions: * Hardware control vector interrupt function that can control interrupt acceptance by interrupt enable flag (IExxx) and interrupt master enable flag (IME). * Arbitrary setting of interrupt start address. * Multiple interruption function by which priority can be specified using the interrupt priority selection register (IPS). * Interrupt request flag (IRQxxx) test function (interrupt generation confirmation by software possible). * Standby mode release (selection of interrupt that releases the standby mode by interrupt enable flag possible).
27
28 Fig. 6-1 Interrupt Control Circuit Block Diagram
Internal Bus 2 IM1 2 IM0 9 Interrupt Enable Flag (IEXXX) (IME) 4 IPS 2 IST INT BT INT4 /P00 INT0 /P10 INT1 /P11
Edge Detection Circuit Edge Detection Circuit Edge Detection Circuit
Decoder IRQBT IRQ4 IRQ0 IRQ1 IRQSIO IRQT0 IRQT1 IRQ2 IRQ3 Interrupt Request Flag Standby Release Signal Priority Control Circuit Vector Table Address Generator
INTSIO INTT0 INTT1 INT2 /P12 INT3 /P13
Edge Detection Circuit Edge Detection Circuit
PD75108F,75112F,75116F
PD75108F,75112F,75116F
7. STANDBY FUNCTION
To reduce the power consumption during program wait, the PD75116F has two standby modes (STOP mode and HALT mode). Table 7-1 Standby Mode Setting and Operation Status
STOP Mode Setting instruction Clock generator circuit STOP instruction System clock oscillation stopped
HALT Mode HALT instruction Only CPU clock stopped Operable (IRQBT set at reference time intervals)
Basic interval timer
Operation stopped
Operation Status
Serial interface
Operation possible only when the external SCK input and TO0 output (when timer/event counter 0 is external TI0 input) are selected as a serial clock Operable only when TIn pin input specified as count clock Operation stopped Operation of INT0 to INT4 possible Operation stopped
Operation possible if a clock other than is specified as a serial clock
Timer/event counter
Operation possible
Clock output circuit External interrupt CPU
Except CPU clock , output possible.
Operation stopped
Release signal
Interrupt request signal from operable hardware enabled by interrupt enable flag, or RESET input
29
PD75108F,75112F,75116F
8. RESET FUNCTION
The reset operation timing is shown in Fig. 8-1. Fig. 8-1 Reset Operation by RESET Input
Wait (Approx. 31.3 ms: 4.19 MHz) RESET Input
Operating Mode or Standby Mode
HALT Mode
Operating Mode
Internal Reset Operation
The state of hardware after reset operation is as shown in Table 8-1.
30
PD75108F,75112F,75116F
Table 8-1 Status of Each Hardware after Resetting
Hardware
RESET Input in Standby Mode Low-order 5 bits of program memory address 0000H are set in PC12 to PC8 and the contents of address 0001H are set in PC7 to PC0. Low-order 6 bits of program memory address 0000H are set in PC13 to PC8 and the contents of address 0001H are set in PC7 to PC0. Held 0 0 Sets program memory address 0000H bit 6 and bit 7 to RBE and MBE, respectively. Undefined Held* Held 0, 0 Undefined 0 0 FFH 0 0, 0 Held 0 0 0 Reset (0) 0 0 0, 0 OFF Clear (0) 0 Undefined 0 0
RESET Input during Operation
PD75108F
Program counter (PC)
Same as left
PD75112F PD75116F
Carry flag (CY) Skip flag (SK0 to SK2) PSW Interrupt status flag (IST0, IST1) Bank enable flag (MBE, RBE) Stack pointer (SP) Data memory (RAM) General register (X, A, H, L, D, E, B, C) Bank selection register (MBS, RBS) Basic interval timer Counter (BT) Mode register (BTM) Counter (Tn) Timer/event counter (n = 0, 1) Modulo register (TMODn) Mode register (TMn) TOEn, TOFn Serial interface Clock generator, clock output circuit Shift register (SIO) Mode register (SIOM) Processor clock control register (PCC) Clock output mode register (CLOM) Interrupt request flag (IRQxxx) Interrupt Interrupt enable flag (IExxx) Priority selection register (IPS) INT0, 1 mode registers (IM0, IM1) Output buffer Digital port Output latch I/O mode register (PMGA, B, C) PTH00 to 03 input latch Analog port Mode register (PTHM) Bit sequential buffer (BSB0 to BSB3)
Undefined 0 0 Same as left Undefined Undefined Undefined 0, 0 Undefined 0 0 FFH 0 0, 0 Undefined 0 0 0 Reset (0) 0 0 0, 0 OFF Clear (0) 0 Undefined 0 0
*
Data of data memory addresses 0F8H to 0FDH becomes undefined by RESET input.
31
PD75108F,75112F,75116F
9.
INSTRUCTION SET
(1) Operand identifier and description The operand is described in the operand field of each instruction in accordance with the description for the operand identifier of the instruction. (For details, refer to RA75X Assembler Package User's Manual Language Volume (EEU-730).) When there are multiple elements in the description, one of the elements is selected. Upper case letters and symbols (+,-) are keywords and are described unchanged. Various register or flag symbols can be used as a label instead of mem, fmem, pmem, bit, etc. (For details, refer to PD75116 User's Manual (IEM-922).) However, there are restrictions on the labels for which fmem and pmem can be used.
Identifier reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem X, A, B, C, D, E, H, L X, B, C, D, E, H, L
Description
XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label* 2-bit immediate data or label FB0H to FBFH, FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label
PD75108F
addr
0000H to 1F7FH immediate data or label 0000H to 2F7FH immediate data or label 0000H to 3F7FH immediate data or lebel
PD75112F PD75116F
caddr faddr taddr PORTn IExxx RBn MBn
12-bit immediate data or label 11-bit immediate data or label 20H to 7FH immediate data (however, bit0 = 0) or label PORT 0 to PORT 9, PORT12 to PORT14 IEBT, IESIO, IET0, IET1, IE0 to IE4 RB0 to RB3 MB0, MB1, MB15
*
In the case of the 8-bit data processing, an even address only can be described for mem.
32
PD75108F,75112F,75116F
(2) Operation description legend A : A register; 4-bit accumulator B : B register C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE PORTn IME IPS IExxx RBS MBS PCC . (xx) xxH : : : : : : : : : : : : : : : : : : : : : : : : : : : : C register D register E register H register L register X register Register pair (XA); 8-bit accumulator Register pair (BC) Register pair (DE) Register pair (HL) Extension register pair (XA') Extension register pair (BC') Extension register pair (DE') Extension register pair (HL') Program counter Stack pointer Carry flag; bit accumulator Program status word Memory bank enable flag Register bank enable flag Portn (n = 0 to 9, 12 to 14) Interrupt master enable flag Interrupt priority selection register Interrupt enable flag Register bank selection register Memory bank selection register Processor clock control register Address, bit delimiter
: Contents addressed by xx : Hexadecimal data
33
PD75108F,75112F,75116F
(3) Description of addressing area field symbols
*1 *2
MB = MBE * MBS (MBS = 0, 1, 15) MB = 0 MBE = 0 : MB = 0 (00H to 7FH) MB = 15 (80H to FFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) MB = 15, fmem = FB0H to FBFH, FF0H to FFFH MB = 15, pmem = FC0H to FFFH
*3
Data memory addressing
*4 *5 *6
PD75108F : addr = 0000H to 1F7FH PD75112F : addr = 0000H to 2F7FH PD75116F : addr = 0000H to 3F7FH
addr = (Current PC) -15 to (Current PC) + 16
*7
*8
PD75108F : caddr = = PD75112F : caddr = = = PD75116F : caddr = = = =
0000H 1000H 0000H 1000H 2000H 0000H 1000H 2000H 3000H
to to to to to to to to to
0FFFH 1F7FH 0FFFH 1FFFH 2F7FH 0FFFH 1FFFH 2FFFH 3F7FH
(PC12 = 0) or (PC12 = 1) (PC13, PC12 = (PC13, PC12 = (PC13, PC12 = (PC13, PC12 = (PC13, PC12 = (PC13, PC12 = (PC13, PC12 =
00B) 01B) 10B) 00B) 01B) 10B) 11B)
or or or or or
Program memory addressing
*9 *10
faddr = 0000H to 07FFH taddr = 0020H to 007FH
Remarks
1. 2. 3. 4.
MB indicates the accessible memory bank. For *2, MB = 0 without regard to MBE and MBS. For *4 and *5, MB = 15 without regard to MBE and MBS. *6 to *10 indicate the addressable area.
(4) Explanation of machine cycle field S shows the number of machine cycles required when skip is performed by an instruction with skip. The value of S changes as follows: * No skip ....................................................................................................................................................................... S = 0 * When instruction to be skipped is 1-byte or 2-byte instruction ......................................................................... S = 1 * When instruction to be skipped is 3-byte instruction (BR !addr, CALL !addr instructions) ........................... S = 2 Note One machine cycle is required to skip a GETI instruction.
One machine cycle is equivalent to one cycle (= tCY) of the CPU clock. Three times can be selected by PCC setting.
34
PD75108F,75112F,75116F
Instruction Group
Mnemonic
Operands A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HLA, @rpa1
Bytes Machine Cycles 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 A n4
Operation
Addressing Area
Skip Condition Stack A
reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (HL), then L L + 1 A (HL), then L L - 1 A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp' reg1 A rp'1 XA A (HL) A (HL), then L L + 1 A (HL), then L L - 1 A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp' * PD75108F XA (PC12-8 + DE)ROM * PD75112F, 75116F XA (PC13-8 + DE)ROM *1 *1 *1 *2 *1 *3 *3 L=0 L = FH *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH Stack A Stack B
MOV
XA, @HL @HL, A @HL, XA A, mem XA, mem
Transfer
mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA A, @HL A, @HL+ A, @HLA, @rpa1 XCH XA, @HL A, mem XA, mem A,reg1 XA, rp'
XA, @PCDE
1
3
Table Reference
MOVT XA, @PCXA 1 3
* PD75108F XA (PC12-8 + XA)ROM * PD75112F, 75116F XA (PC13-8 + XA)ROM
35
PD75108F,75112F,75116F
Instruction Group
Mnemonic
Operands CY, fmem.bit CY, pmem.@L
Bytes Machine Cycles 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2
Operation CY (fmem.bit) CY (pmem7 - 2 + L3 - 2.bit(L1-0)) CY (H + mem3 - 0.bit) (fmem.bit) CY (pmem7 - 2 + L3 - 2.bit(L1-0)) CY (H + mem3 - 0.bit) CY A A + n4 XA XA + n8 A A + (HL) XA XA + rp' rp'1 rp'1 + XA A, CY A + (HL) + CY XA, CY XA + rp' + CY rp'1, CY rp'1 + XA + CY A A - (HL) XA XA - rp' rp'1 rp'1 - XA A, CY A - (HL) - CY XA, CY XA - rp' - CY rp'1, CY rp'1 - XA - CY A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA
Addressing Area *4 *5 *1 *4 *5 *1
Skip Condition
Bit transfer
MOV1
CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY A, #n4 XA, #n8
carry carry *1 carry carry carry *1
ADDS
A, @HL XA, rp' rp'1, XA A, @HL
ADDC
XA, rp' rp'1, XA A, @HL
*1
borrow borrow borrow
SUBS
XA, rp' rp'1, XA A, @HL
*1
Operations
SUBC
XA, rp' rp'1, XA A, #n4
AND
A, @HL XA, rp' rp'1, XA A, #n4
*1
OR
A, @HL XA, rp' rp'1, XA A, #n4 A, @HL
*1
*1
XOR XA, rp' rp'1, XA
36
PD75108F,75112F,75116F
Instruction Group
Mnemonic A A
Operands
Bytes Machine Cycles 1 2 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 1+S 1+S 2+S 2+S 1+S 2+S 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S
Operation CY A0, A3 CY, An-1 An AA reg reg + 1 rp1 rp1 + 1 (HL) (HL) + 1 (mem) (mem) + 1 reg reg - 1 rp' rp' - 1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY 1 CY 0 Skip if CY = 1 CY CY (mem.bit) 1 (fmem.bit) 1 (pmem7-2 + L3-2.bit (L1-0)) 1 (H + mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2 + L3-2.bit (L1-0)) 0 (H + mem3-0.bit) 0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1 Skip if (pmem7-2 + L3-2.bit (L1-0)) = 1 Skip if (H + mem3-0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7-2 + L3-2.bit (L1-0)) = 0 Skip if (H + mem3-0.bit) = 0 Skip if (fmem.bit) = 1 and clear Skip if (pmem7-2 + L3-2.bit (L1-0)) = 1 and clear Skip if (H + mem3-0.bit) = 1 and clear
Addressing Area
Skip Condition
Accumulator RORC manipulation NOT
reg rp1 INCS Increment /decrement @HL mem DECS reg rp' reg, #n4 @HL, #n4 Comparison SKE A, @HL XA, @HL A, reg XA, rp' SET1 Carry flag CLR1 manipulation SKT NOT1 CY CY CY CY mem.bit SET1 fmem.bit pmem.@L @H + mem.bit mem.bit fmem.bit CLR1 pmem.@L @H + mem.bit mem.bit Memory bit manipulation SKT fmem.bit pmem.@L @H + mem.bit mem.bit fmem.bit SKF pmem.@L @H + mem.bit fmem.bit SKTCLR pmem.@L
reg = 0 rp1 = 00H *1 *3 (HL) = 0 (mem) = 0 reg = FH rp' = FFH reg = n4 *1 *1 *1 (HL) = n4 A = (HL) XA = (HL) A = reg XA = rp'
CY = 1
*3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1
(@H + mem.bit) = 1
(mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0
(@H + mem.bit) = 0
(fmem.bit) = 1 (pmem.@L) = 1
@H + mem.bit
2
2+S
*1
(@H + mem.bit) = 1
37
PD75108F,75112F,75116F
Instruction Group
Mnemonic
Operands CY, fmem.bit
Bytes Machine Cycles 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Operation CY CY (fmem.bit) CY CY (pmem7-2 + L3-2.bit (L1-0)) CY CY (H + mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2 + L3-2.bit (L1-0)) CY CY (H + mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2 + L3-2.bit (L1-0)) CY CY (H + mem3-0.bit) * PD75108F PC12-0 addr (The assembler selects the optimum instruction from among the BR !addr, BRCB !caddr, and BR $addr instructions.) * PD75112F, 75116F PC13-0 addr (The assembler selects the optimum instruction from among the BR !addr, BRCB !caddr, and BR $addr instructions.) * PD75108F PC12-0 addr * PD75112F, 75116F PC13-0 addr * PD75108F PC12-0 addr * PD75112F, 75116F PC13-0 addr * PD75108F PC12-0 PC12 + caddr11-0 * PD75112F, 75116F PC13-0 PC13, PC12 + caddr11-0 * PD75108F PC12-0 PC12-8 + DE * PD75112F, 75116F PC13-0 PC13-8 + DE * PD75108F PC12-0 PC12-8 + XA * PD75112F, 75116F PC13-0 PC13-8 + XA * PD75108F (SP-4) (SP-1) (SP-2) PC11-0 (SP-3) MBE, RBE, 0, PC12
Skip Addressing Condition Area *4 *5 *1 *4 *5 *1 *4 *5 *1
AND1
CY, pmem.@L CY, @H + mem.bit CY, fmem.bit
Memory bit manipulation
OR1
CY, pmem.@L CY, @H + mem.bit CY, fmem.bit
XOR1
CY, pmem.@L CY, @H + mem.bit
addr
--
--
*6
BR !addr 3 3
*6
Branch $addr 1 2
*7
BRCB
!caddr
2
2
*8
PCDE BR PCXA
2
3
2
3
Subroutine stack control
CALL
!addr
3
3
PC12-0 addr, SP SP-4 * PD75112F, 75116F (SP-4) (SP-1) (SP-2) PC11-0 (SP-3) MBE, RBE, PC13, PC12 PC13-0 addr, SP SP-4
*6
38
PD75108F,75112F,75116F
Instruction Group
Mnemonic
Operands Bytes Machine Cycles
Operation * PD75108F (SP - 4) (SP - 1) (SP - 2) PC11-0 (SP - 3) MBE, RBE, 0, PC12 PC12-0 00, faddr, SP SP - 4 * PD75112F, 75116F (SP - 4) (SP - 1) (SP - 2) PC11-0 (SP - 3) MBE, RBE, PC13, PC12 PC13-0 000, faddr, SP SP - 4 * PD75108F MBE, RBE, x, PC12 (SP + 1) PC11-0 (SP) (SP + 3) (SP + 2) SP SP + 4 * PD75112F, 75116F MBE, RBE, PC13, PC12 (SP + 1) PC11-0 (SP) (SP + 3) (SP + 2) SP SP + 4 * PD75108F MBE, RBE, x, PC12 (SP + 1) PC11-0 (SP) (SP + 3) (SP + 2) SP SP + 4, then skip unconditionally * PD75112F, 75116F MBE, RBE, PC13, PC12 (SP + 1) PC11-0 (SP) (SP + 3) (SP + 2) SP SP + 4, then skip unconditionally * PD75108F MBE, RBE, x, PC12 (SP + 1) PC11-0 (SP) (SP + 3) (SP + 2) PSW (SP + 4) (SP + 5 ), SP SP + 6 * PD75112F, 75116F MBE, RBE, PC13, PC12 (SP + 1) PC11-0 (SP) (SP + 3) (SP + 2) PSW (SP + 4) (SP + 5 ), SP SP + 6 (SP - 1) (SP - 2) rp, SP SP - 2 (SP - 1) MBS, (SP - 2) RBS, SP SP - 2 rp (SP + 1) (SP), SP SP + 2 MBS (SP + 1), RBS (SP), SP SP + 2 IME (IPS.3) 1 IExxx 1 IME (IPS.3) 0 IExxx 0
Addressing Skip Condition Area
CALLF
!faddr
2
2
*9
RET
1
3
Subroutine stack control
RETS
1
3+S
Unconditional
RETI
1
3
rp PUSH BS rp POP BS EI Interrupt control DI IExxx IExxx
1 2 1 2 2 2 2 2
1 2 1 2 2 2 2 2
39
PD75108F,75112F,75116F
Instruction Group
Mnemonic IN *1
Operands A, PORTn XA, PORTn
Bytes Machine Cycles 2 2 2 2 2 2 1 2 2 2 2 2 2 1 2 2 A PORTn
Operation (n = 0 to 9, 12 to 14)
Addressing Skip Condition Area
Input/output *1 OUT HALT CPU control STOP NOP SELL
XA PORTn + 1, PORTn (n = 4, 6, 8, 12) PORTn A (n = 2 to 9, 12 to 14)
PORTn, A PORTn, XA
PORTn + 1, PORTn XA (n = 4, 6, 8, 12) Set HALT Mode (PCC.2 1) Set STOP Mode (PCC.3 1) No Operation RBS n (n = 0 to 3)
RBn MBn
2 2
MBS n (n = 0, 1, 15) * PD75108F TBR Instruction PC12-0 (taddr)4-0 (taddr + 1) ---------------------------------------------------------TCALL Instruction (SP - 4) (SP - 1) (SP - 2) PC11-0 (SP - 3) MBE, RBE, 0, PC12 PC12-0 (taddr)4-0 (taddr + 1) SP SP - 4 ---------------------------------------------------------Other than TBR and TCALL Instruction Execution of an instruction addressed at (taddr) and (taddr + 1) * PD75112F, 75116F TBR Instruction PC13-0 (taddr)5-0 (taddr + 1) ---------------------------------------------------------TCALL Instruction (SP - 4) (SP - 1) (SP - 2) PC11-0 (SP - 3) MBE, RBE, 0, PC13, PC12 PC13-0 (taddr)5-0 (taddr + 1) SP SP - 4 ---------------------------------------------------------Other than TBR and TCALL Instruction Execution of an instruction addressed at (taddr) and (taddr + 1) *10
Special
*2 GETI
taddr
1
3
-----------------------Conforms to referenced instruction.
----------------------Conforms to referenced instruction.
*
1. When executing the IN/OUT instruction, or must be set. 2. The TBR or TCALL instruction is a GETI instruction table definition assembler pseudo-instruction.
40
10.1 CORDLESS TELEPHONE (SUBSET)
10. APPLICATION EXAMPLE
Power Amp IDC
Amp Compression Transmitter/ Receiver
PD2840 PD2841
Prescaler
PD6130 PD6131
MSK Modem
MPX
Extension
Speaker VCO PLL TCXO MPX Prescaler LED Display Speaker Amp
VCO
PLL
PD75116F
SIO
Key Matrix
Radio Wave Detection
LCD Controller/ Driver PD7228 Console
LED Display
Extra-Area Detection
ID ROM
PD6252
Detection Mixer 2SC4226 1SS281 3SK177
Legend IDC LED PLL VCO : : : : Immediate Deviation Controller, Light Emitting Diode, Phase Locked Loop, Voltage Control Oscillator ID ROM MPX SIO : : : ID (Identification) Code ROM, LCD Multiplexer, Serial Data Input/Output, MSK TCXO : : : Liquid Crystal Display, Minimum Shift Keying, Temperature Compensation Crystal Oscillator,
PD75108F,75112F,75116F
Filter
Amp 2SC2757 2SC4182
41
PD75108F,75112F,75116F
10.2 DISPLAY PAGER
PD75116F
Filter INT
RAM PD446
Code ROM Switch TO High-Current Output LED Display
Piezoelectric Buzzer
Comparator Input SIO LCD Controller/Driver PD7228/7229 LCD Display
Battery Check
42
PD75108F,75112F,75116F
11. MASK OPTION SELECTION
The PD75116F has the following mask option to select whether or not a pull-up resistor is incorporated.
Pin P120 to P123 P130 to P133 P140 to P143
Mask Option
Pull-up resistor can be incorporated bit-wise.
43
PD75108F,75112F,75116F
12. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 C)
PARAMETER Supply voltage SYMBOL VDD VI1 Input voltage VI2*1 Ports 12 to 14 Open-drain Output voltage Output current high VO One pin IOH All pins Peak value One pin Effective value Total of ports 0, 2 to 4, 12 to 14 Peak value Effective value Peak value Total of ports 5 to 9 Effective value Operating temperature Storage temperature Topt 60 -40 to +60 mA C C 15 100 60 100 mA mA mA mA -30 30 mA mA -0.3 to +11 -0.3 to VDD +0.3 -15 V V mA Except ports 12, 13 and 14 Internal pull-up resistor TEST CONDITIONS RATING -0.3 to +5.5 -0.3 to VDD +0.3 -0.3 to VDD +0.3 UNIT V V V
Output current low
IOL*2
Tstg
-65 to +150
*
1. When a voltage exceeding 10V is applied to ports 12, 13 and 14, the power supply impedance (pull-up resistor) should be 50K or more. 2. Effective value should be calculated: [Effective value] = [Peak value] x duty Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. The absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded.
Note
44
PD75108F,75112F,75116F
12.1 WHEN Ta = -40 to +50 C, VDD = 2.7 to 5.0 V OPERATING VOLTAGE (Ta = -40 to +50 C)
PARAMETER CPU*1 Programmable threshold port (comparator input) Other hardware*1 TEST CONDITIONS MIN. *2 4.5 2.7 MAX. 5.0 5.0 5.0 UNIT V V V
*
1. Except system clock oscillation circuit, programmable threshold port. 2. The operable supply voltage range depends on the cycle time. See "AC CHARACTERISTICS".
OSCILLATION CIRCUIT CHARACTERISTICS (Ta = -40 to +50 C, VDD = 2.7 to 5.0 V)
RESONATOR RECOMMENDED CONSTANT PARAMETER TEST CONDITIONS VDD = Oscillation voltage range After VDD reaches MIN. of oscillation voltage range MIN. TYP. MAX. UNIT
X1 Ceramic resonator C1
X2
Oscillator frequency (fXX)*1
2.0
5.0*3
MHz
C2
Oscillation stabilization time*2
4
ms
X1 Crystal resonator C1
X2
Oscillator frequency (fXX)*1
2.0
4.19
5.0*3
MHz
C2
Oscillation stabilization time*2
VDD = 4.5 to 5.0 V
10 30
ms ms
X1 External clock
X2
X1 input frequency (fX)*1 X1 input high-/low-level width (tXH, tXL)
2.0
5.0*3
MHz
PD74HCU04
100
250
ns
*
1. Oscillator frequency and X1 input frequency indicate oscillation circuit characteristics only. See AC CHARACTERISTICS for instruction execution time. 2. The oscillation stabilization time is the time required for oscillation to stabilize after VDD reaches MIN. of oscillation voltage range or the STOP mode is released. 3. When the oscillator frequency is 4.19 MHz < fXX 5.0 MHz, PCC = 0011 should not be selected as the instruction execution time. If PCC = 0011 is selected, one machine cycle is less than 0.95 s and the rated MIN. value of 0.95 s is not observed. When the clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. * The wiring should be kept as short as possible. * No other signal lines should be crossed. * Keep away from lines carrying a high fluctuating current. * The oscillator capacitor grounding point should always be at the same potential as VSS. Do not connect to a ground pattern carrying a high current. * A signal should be not taken from the oscillator. 5
Note
45
PD75108F,75112F,75116F
RECOMMENDED OSCILLATION CIRCUIT CONSTANT RECOMMENDED CERAMIC RESONATOR (Ta = -40 to +50 C)
EXTERNAL CAPACITANCE [pF] MANUFACTURER PRODUCT NAME CSA 2.00MG Murata Mfg. CSA 4.19MG CSA 4.19MGU CST 4.19T KBR-2.0MS Kyocera KBR-4.0MS KBR-4.19MS KBR-4.9152M C1 30 30 30 -- 100 33 33 33 C2 30 30 30 -- 100 33 33 33 OSCILLATION VOLTAGE RANGE [V] MIN. 2.7 3.0 2.7 3.0 3.0 3.0 3.0 3.0 MAX. 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0
RECOMMENDED CRYSTAL RESONATOR (Ta = -20 to +50 C)
EXTERNAL CAPACITANCE [pF] MANUFACTURER Kinseki PRODUCT NAME HC-49/U C1 22 C2 22 OSCILLATION VOLTAGE RANGE [V] MIN. 2.7 MAX. 5.0
46
PD75108F,75112F,75116F
DC CHARACTERISTICS (Ta = -40 to +50 C, VDD = 2.7 to 5.0 V)
PARAMETER SYMBOL VIH1 VIH2 Input voltage high VIH3 Ports 12 and 14 Open-drain VIH4 VIL1 Input voltage low VIL2 VIL3 X1, X2 Other than below Ports 0,1,TI0, 1, RESET X1, X2 VDD = 4.5 to 5.0 V, IOH = -1 mA Output voltage high VOH IOH = -100 A Ports 0, 2 to 9, IOL = 15 mA VDD = 4.5 to 5.0 V Ports 12 to 14, IOL = 10 mA Output voltage low VOL VDD = 4.5 to 5.0 V, IOL = 1.6 mA IOL = 400 A ILIH1 Input leakage current high VIN = VDD ILIH2 ILIH3 Input leakage current low Output leakage current high Output leakage current low Internal pull-up resistor (mask option) ILIL1 VIN = 0 V ILIL2 ILOH1 ILOH2 ILOL VOUT = VDD VOUT = 10 V VOUT = 0 V VDD = 4.5 to 5.0 V RL Ports 12 to 14 10 VDD = 4.5 to 5.0 V*2 IDD1 Supply current*1 IDD2 4.19 MHz VDD = 3 V 10 %*3 Crystal oscillation C1 = C2 = 22 pF VDD = 4.5 to 5.0 V HALT mode VDD = 3 V 10 % STOP mode, VDD = 3 V 10 % 0.55 600 200 0.1 1.5 1800 600 10 mA 3 80 9 k mA 15 40 X1, X2 Other than below Ports 12 to 14 (open-drain) -20 3 20 -3 70 VIV = 10 V X1, X2 Ports 12 to 14 (open-drain) Except X1, X2 20 20 -3 Other than below 0.4 0.5 3 V V 0.35 2.0 V VDD - 0.5 0.35 2.0 V V 0.7 VDD VDD - 0.5 0 0 0 VDD - 1.0 12 VDD 0.3 VDD 0.2 VDD 0.4 V V V V V V TEST CONDITIONS Other than below Ports 0,1,TI0, 1, RESET Internal pull-up resistor MIN. 0.7 VDD 0.8 VDD 0.7 VDD TYP. MAX. VDD VDD VDD UNIT V V V
A A A A A A A A
k
A A A
IDD3
*
1. Excluding current flowing in the internal pull-up resistors and comparator circuit. 2. When the processor clock control register (PCC) is set to 0011 for operation in the high-speed mode. 3. When the PCC register is set to 0000 for operation in the low-speed mode.
47
PD75108F,75112F,75116F
CAPACITANCE (Ta = 25 C, VDD = 0 V)
PARAMETER Input capacitance Output capacitance Input/output capacitance SYMBOL CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V 15 pF TEST CONDITIONS MIN. TYP. MAX. 15 15 UNIT pF pF
COMPARATOR CHARACTERISTICS (Ta = -40 to +50 C, VDD = 4.5 to 5.0 V)
PARAMETER Compare accuracy Threshold voltage PTH input voltage Comparator circuit current consumption SYMBOL VACOMP VTH VIPTH 0 0 TEST CONDITIONS MIN. TYP. MAX. 100 VDD VDD UNIT mV V V
PTHM7 set to "1"
1
mA
48
PD75108F,75112F,75116F
AC CHARACTERISTICS (Ta = -40 to +50 C, VDD = 2.7 to 5.0 V)
PARAMETER CPU clock cycle time* (Minimum instruction execution time = 1 machine cycle) TI0, TI1 input frequency SYMBOL TEST CONDITIONS VDD = 4.5 to 5.0 V tCY 1.91 VDD = 4.5 to 5.0 V fTI 0 tTIH, tTIL Input VDD = 4.5 to 5.0 V Output SCK cycle time tKCY Input Output Input VDD = 4.5 to 5.0 V SCK high/low-level width tKH, tKL Output Input Output SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK INT0 to INT4 High/low-level width RESET low-level width tSIK tKCY/2 - 50 1.6 tKCY/2 - 150 100 ns 3.2 3.8 0.4 0.95 VDD = 4.5 to 5.0 V 0.48 1.8 0.8 275 kHz 0 32 1 MIN. 0.95 TYP. MAX. 32 UNIT
s s
MHz
TI0, TI1 input high/ low-level width
s s s s s s s
s
ns ns
tKSI VDD = 4.5 to 5.0 V tKSO
400 300 1000
ns ns ns
tINTH, tINTL tRSL
5
s s
5
49
PD75108F,75112F,75116F
*
The CPU clock cycle time is determined by the oscillation frequency of the connected resonator and the setting of the processor clock control register (PCC). The graph on the right shows the characteristic for cycle time tCY supply current VDD during system clock operation.
tCY vs. VDD
40 32 7 6 5 4 3
Operating Guarantee Range
tCY [ s]
2
1
0.5 0 1 2 3 4 5 6
VDD [V]
50
PD75108F,75112F,75116F
AC Timing Test Point (Except ports 0, 1, TI0, TI1, X1, X2, RESET)
0.7 VDD 0.3 VDD
Test Points
0.7 VDD 0.3 VDD
Clock Timing
1/fX tXL tXH
X1 Input
VDD - 0.5 V 0.4 V
TI0,TI1 Input Timing
1/fTI tTIL tTIH
TI0, TI1
0.8 VDD 0.2 VDD
51
PD75108F,75112F,75116F
Serial Transfer Timing
tKCY tKL tKH
SCK
0.8 VDD 0.2 VDD
tSIK
tKSI
SI
Input Data
0.8 VDD 0.2 VDD
tKSO
SO
Output Data
Interrupt Input Timing
tINTL
tINTH
INT0-INT4
0.8 VDD 0.2 VDD
RESET Input Timing
tRSL
RESET
0.2 VDD
52
PD75108F,75112F,75116F
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = -40 to +50 C)
PARAMETER Data retention supply voltage Data retention supply current*1 Release signal set time SYMBOL VDDDR IDDDR tSREL Release by RESET Oscillation stabilization time*2 tWAIT Release by interrupt request *3 ms VDDDR = 2.0 V 0 217/fXX TEST CONDITIONS MIN. 2.0 0.1 TYP. MAX. 5.0 10 UNIT V
A s
ms
*
1. Excluding current flowing in the internal pull-up resistors and comparator circuit. 2. The oscillation stabilization wait time is the time during which CPU operation is stopped to prevent unstable operation when oscillation is started. 3. Depends on the basic interval timer mode register (BTM) setting (see table below).
WAIT TIME (Figures in parentheses are for operation at fXX = 4.19 MHz) 220/fXX (approx. 250 ms) 217/fXX (approx. 31.3 ms) 215/fXX (approx. 7.82 ms) 213/fXX (approx. 1.95 ms)
BTM3 -- -- -- --
BTM2 0 0 1 1
BTM1 0 1 0 1
BTM0 0 1 1 1
Data Retention Timing (STOP mode release by RESET)
Internal Reset Operation HALT Mode STOP Mode Data Retention Mode Operating Mode
VDD VDDDR STOP Instruction Execution tSREL
RESET
tWAIT
53
PD75108F,75112F,75116F
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
HALT Mode STOP Mode Data Retention Mode Operating Mode
VDD VDDDR STOP Instruction Execution tSREL
Standby Release Signal (Interrupt Request) tWAIT
54
PD75108F,75112F,75116F
12.2 WHEN Ta = -40 to +60 C, VDD = 2.8 to 5.0 V OPERATING VOLTAGE (Ta = -40 to +60 C)
PARAMETER CPU*1 Programmable threshold port (comparator input) Other hardware*1 TEST CONDITIONS MIN. *2 4.5 2.8 MAX. 5.0 5.0 5.0 UNIT V V V
*
1. Except system clock oscillation circuit, programmable threshold port. 2. The operable supply voltage range depends on the cycle time. See "AC CHARACTERISTICS".
OSCILLATION CIRCUIT CHARACTERISTICS (Ta = -40 to +60 C, VDD = 2.8 to 5.0 V)
RESONATOR RECOMMENDED CONSTANT PARAMETER TEST CONDITIONS VDD = Oscillation voltage range After VDD reaches MIN. of oscillation voltage range MIN. TYP. MAX. UNIT
X1 Ceramic resonator C1
X2
Oscillator frequency (fXX)*1
2.0
5.0*3
MHz
C2
Oscillation stabilization time*2
4
ms
X1 Crystal resonator C1
X2
Oscillator frequency (fXX)*1
2.0
4.19
5.0*3
MHz
C2
Oscillation stabilization time*2
VDD = 4.5 to 5.0 V
10 30
ms ms
X1 External clock
X2
X1 input frequency (fX)*1 X1 input high-/low-level width (tXH, tXL)
2.0
5.0*3
MHz
PD74HCU04
100
250
ns
*
1. Oscillator frequency and X1 input frequency indicate oscillation circuit characteristics only. See AC CHARACTERISTICS for instruction execution time. 2. The oscillation stabilization time is the time required for oscillation to stabilize after VDD reaches MIN. of oscillation voltage range, or the STOP mode is released. 3. When the oscillator frequency is 4.19 MHz < fXX 5.0 MHz, PCC = 0011 should not be selected as the instruction execution time. If PCC = 0011 is selected, one machine cycle is less than 0.95 s and the rated MIN. value of 0.95 s is not observed. When the clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. * The wiring should be kept as short as possible. * No other signal lines should be crossed. * Keep away from lines carrying a high fluctuating current. * The oscillator capacitor grounding point should always be at the same potential as VSS. Do not connect to a ground pattern carrying a high current. * A signal should be not taken from the oscillator.
Note
5
55
PD75108F,75112F,75116F
RECOMMENDED OSCILLATION CIRCUIT CONSTANT RECOMMENDED CERAMIC RESONATOR (Ta = -40 to +60 C)
EXTERNAL CAPACITANCE [pF] MANUFACTURER PRODUCT NAME CSA 2.00MG Murata Mfg. CSA 4.19MG CSA 4.19MGU CST 4.19T KBR-2.0MS Kyocera KBR-4.0MS KBR-4.19MS KBR-4.9152M C1 30 30 30 -- 100 33 33 33 C2 30 30 30 -- 100 33 33 33 OSCILLATION VOLTAGE RANGE [V] MIN. 2.7 3.0 2.7 3.0 3.0 3.0 3.0 3.0 MAX. 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0
RECOMMENDED CRYSTAL RESONATOR (Ta = -20 to +60 C)
EXTERNAL CAPACITANCE [pF] MANUFACTURER Kinseki PRODUCT NAME HC-49/U C1 22 C2 22 OSCILLATION VOLTAGE RANGE [V] MIN. 2.7 MAX. 5.0
56
PD75108F,75112F,75116F
DC CHARACTERISTICS (Ta = -40 to +60 C, VDD = 2.8 to 5.0 V)
PARAMETER SYMBOL VIH1 VIH2 Input voltage high VIH3 Ports 12 to 14 Open-drain VIH4 VIL1 Input voltage low VIL2 VIL3 X1, X2 Other than below Ports 0,1,TI0, 1, RESET X1, X2 VDD = 4.5 to 5.0 V, IOH = -1 mA Output voltage high VOH IOH = -100 A Ports 0, 2 to 9, IOL = 15 mA VDD = 4.5 to 5.0 V Ports 12 to 14, IOL = 10 mA Output voltage low VOL VDD = 4.5 to 5.0 V, IOL = 1.6 mA IOL = 400 A ILIH1 Input leakage current high VIN = VDD ILIH2 ILIH3 Input leakage current low Output leakage current high Output leakage current low Internal pull-up resistor (mask option) ILIL1 VIN = 0 V ILIL2 ILOH1 ILOH2 ILOL VOUT = VDD VOUT = 10 V VOUT = 0 V VDD = 4.5 to 5.0 V RL Ports 12 to 14 10 VDD = 4.5 to 5.0 V*2 IDD1 Supply current*1 IDD2 4.19 MHz VDD = 2.8 to 3.3 V*3 Crystal oscillation C1 = C2 = 22 pF VDD = 4.5 to 5.0 V HALT mode VDD = 2.8 to 3.3 V STOP mode, VDD = 2.8 to 3.3 V 0.55 600 200 0.1 1.5 1800 600 10 mA 3 80 9 k mA 15 40 X1, X2 Other than below Ports 12 to 14 (open-drain) -20 3 20 -3 70 VIV = 10 V X1, X2 Ports 12 to 14 (open-drain) Except X1, X2 20 20 -3 Other than below 0.4 0.5 3 V V 0.35 2.0 V VDD - 0.5 0.35 2.0 V V 0.7 VDD VDD - 0.5 0 0 0 VDD - 1.0 10 VDD 0.3 VDD 0.2 VDD 0.4 V V V V V V TEST CONDITIONS Other than below Ports 0,1,TI0, 1, RESET Internal pull-up resistor MIN. 0.7 VDD 0.8 VDD 0.7 VDD TYP. MAX. VDD VDD VDD UNIT V V V
A A A A A A A A
k
A A A
IDD3
*
1. Excluding current flowing in the internal pull-up resistors and comparator circuit. 2. When the processor clock control register (PCC) is set to 0011 for operation in the high-speed mode. 3. When the PCC register is set to 0000 for operation in the low-speed mode.
57
PD75108F,75112F,75116F
CAPACITANCE (Ta = 25 C, VDD = 0 V)
PARAMETER Input capacitance Output capacitance Input/output capacitance SYMBOL CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V 15 pF TEST CONDITIONS MIN. TYP. MAX. 15 15 UNIT pF pF
COMPARATOR CHARACTERISTICS (Ta = -40 to +60 C, VDD = 4.5 to 5.0 V)
PARAMETER Compare accuracy Threshold voltage PTH input voltage Comparator circuit current consumption SYMBOL VACOMP VTH VIPTH 0 0 TEST CONDITIONS MIN. TYP. MAX. 100 VDD VDD UNIT mV V V
PTHM7 set to "1"
1
mA
58
PD75108F,75112F,75116F
AC CHARACTERISTICS (Ta = -40 to +60 C, VDD = 2.8 to 5.0 V)
PARAMETER CPU clock cycle time* (Minimum instruction execution time = 1 machine cycle) TI0, TI1 input frequency SYMBOL TEST CONDITIONS VDD = 4.5 to 5.0 V tCY 1.91 VDD = 4.5 to 5.0 V fTI 0 tTIH, tTIL Input VDD = 4.5 to 5.0 V Output SCK cycle time tKCY Input Output Input VDD = 4.5 to 5.0 V SCK high/low-level width tKH, tKL Output Input Output SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK INT0 to INT4 High/low-level width RESET low-level width tSIK tKCY/2 - 50 1.6 tKCY/2 - 150 100 ns 3.2 3.8 0.4 0.95 VDD = 4.5 to 5.0 V 0.48 1.8 0.8 275 kHz 0 32 1 MIN. 0.95 TYP. MAX. 32 UNIT
s s
MHz
TI0, TI1 input high/ low-level width
s s s s s s s
s
ns ns
tKSI VDD = 4.5 to 5.0 V tKSO
400 300 1000
ns ns ns
tINTH, tINTL tRSL
5
s s
5
59
PD75108F,75112F,75116F
*
The CPU clock cycle time is determined by the oscillation frequency of the connected resonator and the setting of the processor clock control register (PCC). The graph on the right shows the characteristic for cycle time tCY supply current VDD during system clock operation.
tCY vs. VDD
40 32 7 6 5 4 3
Operating Guarantee Range
tCY [ s]
2
1
0.5 0 1 2 3 4 5 6
VDD [V]
60
PD75108F,75112F,75116F
AC Timing Test Point (Except ports 0, 1, TI0, TI1, X1, X2, RESET)
0.7 VDD 0.3 VDD
Test Points
0.7 VDD 0.3 VDD
Clock Timing
1/fX tXL tXH
X1 Input
VDD - 0.5 V 0.4 V
TI0, TI1 Input Timing
1/fTI tTIL tTIH
TI0, TI1
0.8 VDD 0.2 VDD
61
PD75108F,75112F,75116F
Serial Transfer Timing
tKCY tKL tKH
SCK
0.8 VDD 0.2 VDD
tSIK
tKSI
SI
Input Data
0.8 VDD 0.2 VDD
tKSO
SO
Output Data
Interrupt Input Timing
tINTL
tINTH
INT0-INT4
0.8 VDD 0.2 VDD
RESET Input Timing
tRSL
RESET
0.2 VDD
62
PD75108F,75112F,75116F
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = -40 to +60 C)
PARAMETER Data retention supply voltage Data retention supply current*1 Release signal set time SYMBOL VDDDR IDDDR tSREL Release by RESET Oscillation stabilization time*2 tWAIT Release by interrupt request *3 ms VDDDR = 2.0 V 0 217/fXX TEST CONDITIONS MIN. 2.0 0.1 TYP. MAX. 5.0 10 UNIT V
A s
ms
*
1. Excluding current flowing in the internal pull-up resistors and comparator circuit. 2. The oscillation stabilization wait time is the time during which CPU operation is stopped to prevent unstable operation when oscillation is started. 3. Depends on the basic interval timer mode register (BTM) setting (see table below).
WAIT TIME (Figures in parentheses are for operation at fXX = 4.19 MHz) 220/fXX (approx. 250 ms) 217/fXX (approx. 31.3 ms) 215/fXX (approx. 7.82 ms) 213/fXX (approx. 1.95 ms)
BTM3 -- -- -- --
BTM2 0 0 1 1
BTM1 0 1 0 1
BTM0 0 1 1 1
Data Retention Timing (STOP mode release by RESET)
Internal Reset Operation HALT Mode STOP Mode Data Retention Mode Operating Mode
VDD VDDDR STOP Instruction Execution tSREL
RESET
tWAIT
63
PD75108F,75112F,75116F
Data Retention Timing (Standby release signal: STOP mode release by interrupt signal)
HALT Mode STOP Mode Data Retention Mode Operating Mode
VDD VDDDR STOP Instruction Execution tSREL
Standby Release Signal (Interrupt Request) tWAIT
64
PD75108F,75112F,75116F
13. CHARACTERISTIC CURVES (REFERENCE)
IDD vs. VDD (Crystal Oscillator : 4.19 MHz)
(Ta = 25 C)
High-Speed Mode
Medium-Speed Mode 1000
Low-Speed Mode
Supply Current IDD [A]
HALT Mode
100
X1
X2 Crystal 4.19 MHz
22pF
22pF
10 0 1 2 3 4 5 6
Supply Voltage VDD [V]
65
PD75108F,75112F,75116F
IDD vs. fXX Characteristic Examples (Crystal Oscillation) (VDD = 5.0 V, Ta = 25 C) 3.0
Values in parentheses indicate PCC set values. X1 X2 C1 C2 High-Speed Mode [0011]
2.5
Supply Current IDD [mA]
2.0
Medium-Speed Mode [0010]
1.5
Low-Speed Mode [0000]
1.0
HALT Mode [0100] 0.5
0 0 1 2 3 4 fXX [MHz] 5
IDD vs. fXX Characteristic Examples (Ceramic Oscillation) (VDD = 5.0 V, Ta = 25 C) 3.0
Values in parentheses indicate PCC set values. High-Speed Mode [0011] X1 X2 C1 C2 Medium-Speed Mode [0010]
2.5
Supply Current IDD [mA]
2.0
1.5
Low-Speed Mode [0000]
1.0 HALT Mode [0100] 0.5
0 0 1 2 3 4 fXX [MHz] 5
66
PD75108F,75112F,75116F
IDD vs. fX Characteristic Examples (External Clock) (VDD = 5.0 V, Ta = 25 C) 3.0
Values in parentheses indicate PCC set values. X1 X2
2.5
PD74HCU04
High-Speed Mode [0011]
Supply Current IDD [mA]
2.0
1.5
Medium-Speed Mode [0010]
Low-Speed Mode [0000] 1.0
0.5 HALT Mode [0100] 0 0 1 2 3 4 fX [MHz] 5
67
PD75108F,75112F,75116F
fTI vs. VDD Characteristic (Ta = -40 to +50 C)
TIn Input Frequency fTI [kHz]
1000
500
100
Operating Guarantee Range
50
0 0 1 2 3 4 VDD [V] 5 6 7
fTI vs. VDD Characteristic (Ta = -40 to +60 C)
TIn Input Frequency fTI [kHz]
1000
500
100
Operating Guarantee Range
50
0 0 1 2 3 4 VDD [V] 5 6 7
68
PD75108F,75112F,75116F
VOL vs. IOL (Ports 0, 2 to 9) Characteristic Examples 30 VDD = 5 V VDD = 4 V
Ports 0, 2 to 9 Output Current Low IOL [mA]
VDD = 3 V 20
10
0 0 1 2 VOL [V] 3 4
VOL vs. IOL (Ports 12 to 14) Characteristic Examples 30 VDD = 5 V VDD = 4 V
Ports 12 to 14 Output Current Low IOL [mA]
20
VDD = 3 V
10
0 0 1 2 VOL [V] 3 4
69
PD75108F,75112F,75116F
VOH vs. IOH (Ports 0, 2 to 9) Characteristic Examples -15 VDD = 5 V
VDD = 4 V
Ports 0, 2 to 9 Output Current High IOH [mA]
-10
VDD = 3 V -5
0 0 1 2 VDD - VOH [V] 3 4
Remarks
Characteristic curves not marked "Guarantee Range" indicate reference values.
70
PD75108F,75112F,75116F
14. PACKAGE INFORMATION
64 PIN PLASTIC (14 x 20) 64-Pin Plastic QFP QFP (14x20)
A B
51 52
33 32
detail of lead end
C
D
S
64 1
20 19
F
G
H
IM
J K
P
N L P64GF-100-3B8,3BE,3BR-1 NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 23.6 0.4 20.0 0.2 14.0 0.2 17.6 0.4 1.0 1.0 0.40 0.10 0.20 1.0 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.12 2.7 0.1 0.1 3.0 MAX. INCHES 0.929 0.016 0.795+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.016 +0.004 -0.005 0.008 0.039 (T.P.) 0.071-0.009 0.031+0.009 -0.008 0.006+0.004 -0.003 0.005 0.106 0.004 0.004 0.119 MAX.
+0.008
M
55
Q
71
PD75108F,75112F,75116F
64-Pin Ceramic QFP for ES (Reference Diagram)
14.2 12.0
1
64
52 51
18.0
19 20 33 32 1.0 0.4
20
0.15
2.25
Caution
1.
Note that the metal cap is connected to pin 26, and is at the VSS (GND) level. Note that the leads on the underside are formed at an angle. Cutting of the lead tips is not process-controlled, and therefore there is no standard lead length.
2.
Bottom View
3.
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PD75108F,75112F,75116F
15. RECOMMENDED SOLDERING CONDITIONS
The PD75116F should be soldered and mounted under the conditions recommended in the table below. For details of recommended conditions, refer to the information document "Semiconductor Device Mount Technology Manual" (IEI-1207). For soldering methods and conditions other than those recommended below, contact our salesman. Table 15-1 Surface Mount Type Soldering Conditions
PD75108FGF-xxx-3BE : 64-Pin Plastic QFP (14 x 20 mm) PD75112FGF-xxx-3BE : 64-Pin Plastic QFP (14 x 20 mm) PD75116FGF-xxx-3BE : 64-Pin Plastic QFP (14 x 20 mm)
Soldering Method
Soldering Conditions Package peak temperature : 230 C, Duration : 30 sec. max. (at 210 C or avove), Number of times : once Package peak temperature : 215 C, Duration : 40 sec. max. (at 200 C or above), Number of times : once Solder bath temperature : 260 C max., Duration : 10 sec. max., Number of times : once, Preheating temperature : 120 C max. (package surface temperature) Pin part temperature : 300 C max., Duration : 3 sec. max. (per device side)
Recommended Condition Symbol IR30-00-1
Infrared reflow
VPS
VP15-00-1
Wave soldering
WS60-00-1
Pin part heating
Pin part heating
Note
Use of more than one soldering method should be avoided (except in the case of pin part heating).
Notice A version of this product with improved recommended soldering conditions is available. For details (improvements such as infrared reflow peak temperature extension (235 C), number of times: twice, relaxation of time limit, etc.), contact NEC sales personnel.
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PD75108F,75112F,75116F
5
APPENDIX A. FUNCTIONAL DIFFERENCES AMONG PD751xx SERIES PRODUCTS
Product Name Item ROM (byte) RAM (x 4 bits) Instruction set Total CMOS input CMOS input/output I/O N-ch open-drain port input/output Withstand voltage Pull-up resistor Analog input Power-on reset circuit On-chip (Mask option) Power-on flag Operating voltage Operating temperature range Minimum instruction execution time 2.7 to 6.0 V -40 to +85 C 0.95 s (operating at 4.5 to 6.0 V) 3.8 s (operating at 2.7 V) 2.7 to 5.0 V (Ta = -40 to +50 C) 2.8 to 5.0 V -40 to +60 C 0.95 s (operating at 4.5 to 5.0 V) 1.91 s (operating at 2.7V) None 10 32 (LED direct drive capability)
PD75104/106/108/112/116
4K/6K/8K/12K/16K (Mask ROM) 320/320/512/512/512
PD75104A/108A
4K/8K (Mask ROM) 320/512 75X High-End 58 10 (Pull-up resistor mask option : 4) 10
PD75108F/112F/116F
8K/12K/16K (Mask ROM) 512
32 (Pull-up resistor mask option : 24, 32 (LED direct drive capability) LED direct drive capability) 12 (LED direct drive capability)
+12 V Can be incorporated by mask option 4 (4-bit precision)
+10 V
Package *2
* 64-pin plastic shrink DIP * 64-pin plastic QFP(GF-3BE) * 64-pin plastic QFP (G-1B) : PD75104/106/108 only
* 64-pin plastic QFP(GC-AB8) * 64-pin plastic QFP (G-22) : PD75108A only
* 64-pin plastic QFP(GF-3BE)
*
1. 75X High-End can also be used by means of the 16K-byte mode/24K-byte mode switching function. 2. The following five types of plastic QFP are available. * G-1B ........ 14 x 20 x 2.05 mm, 1.0 mm pitch * GC-AB8 ... 14 x 14 x 2.55 mm, 0.8 mm pitch * GF-3BE .... 14 x 20 x 2.7 mm, 1.0 mm pitch * G-22 ........ 14 x 14 x 1.5 mm, 0.8 mm pitch * GK-7ET ... 12 x 12 x 1.45 mm, 0.65 mm pitch 3. Under development.
74
PD75108F,75112F,75116F
PD75116H/117H
16K/24K (Mask ROM) 768 75X High-End/Extended High-End
PD75P108B
8K (One-time PROM) 512 75X High-End
PD75P116
PD75P117H
24K (One-time PROM) 768 75X Extended High-End*1
58 10 32 (LED direct drive capability : 8) 12 +6 V Can be incorporated by mask option 4 (4-bit precision) 32 (LED direct drive capability) 32 (LED direct drive capability : 8) 12 +6 V None
12 (LED direct drive capability) +12 V
None
None
1.8 to 5.0 V -40 to +60 C 0.95 s (operating at 2.7 V) 1.91 s (operating at 1.8 V)
2.7 to 6.0 V -40 to +85 C
5 V 10 %
1.8 to 5.0 V -40 to +60 C
0.95 s (operating at 4.5 to 6.0 V) 3.8 s (operating at 2.7 V)
0.95 s (operating at 4.75 to 5.5 V)
0.95 s (operating at 2.7 V) 1.91 s (operating at 1.8 V)
* 64-pin plastic QFP (GC-AB8) * 64-pin plastic shrink DIP * 64-pin plastic QFP (GK-7ET) * 64-pin plastic QFP (GF-3BE) * 64-pin ceramic shrink DIP with window
* 64-pin plastic shrink DIP * 64-pin plastic QFP (GC-AB8) * 64-pin plastic QFP (GF-3BE) * 64-pin plastic QFP (GK-7ET)*3
75
PD75108F,75112F,75116F
5
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD75116F.
IE-75000-R*1 IE-75001-R IE-75000-R-EM*2 Hardware EP-75108GF-R EV-9200G-64 PG-1500 PA-75P116GF IE Control Program Software PG-1500 Controller RA75X Relocatable Assembler
75X series in-circuit emulator Emulation board for the IE-75000-R or IE-75001-R Emulation probe for the PD75116FGF. A 64-pin conversion socket (EV-9200G-64) is also provided. PROM programmer PROM programmer adapter for the PD75P116GF, connected to the PG-1500.
Host machines * PC-9800 series (MS-DOSTM Ver. 3.30 to Ver. 5.00A*3) * IBM PC/ATTM (PC-DOSTM Ver.3.1)
*
1. Maintenance product 2. Not incorporated in the IE-75001-R. 3. A task swapping function is provided in Ver. 5.00/5.00A, but this function cannot be used with this software.
Remarks
Please refer to the 75X Series Selection Guide (IF-151) for third party development tools.
76
PD75108F,75112F,75116F
APPENDIX C. RELATED DOCUMENTS
Device Related Documents
5
Document Name User's Manual Instruction Application Table (I) (II) Application Note Introductory Volume Remote Control Reception Volume
Document Number IEM-1260 Not Available IEM-1139 IEM-1281 IEM-1265 IEM-1278 IF-1027
(III) Barcode Reader Volume (IV) MSK Transmission/Reception IC Control Volume
75X Series Selection Guide
Development Tools Documents
Document Name IE-75000-R/IE-75001-R User's Manual IE-75000-R-EM User's Manual Hardware EP-75108GF-R User's Manual PG-1500 User's Manual Operation Volume RA75X Assembler Package User's Manual Software PG-1500 Controller User's Manual Language Volume
Document Number EEU-1455 EEU-1294 EEU-1318 EEU-1335 EEU-1346 EEU-1343 EEU-1291
Other Documents
Document Name Package Manual Surface Mount Technology Manual Quality grade on NEC Semiconductor Devices NEC Semiconductor Device Reliability & Quality Control Electrostatic Discharge (ESD) Test Semiconductor Devices Quality Guide Guarantee Guide Microcomputer Related Products Guide Other Manufacturers Volume
Document Number IEI-1213 IEI-1207 IEI-1209 Not Available Not Available MEI-1202 Not Available
Note
The information in these related documents is subject to change without notice. For design purpose, etc., be sure to use the latest ones.
77
PD75108F,75112F,75116F
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special : Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
M4 92.6
MS-DOS is a trademark of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation.

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