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74ALVC16821 Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs
October 2001 Revised October 2001
74ALVC16821 Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16821 contains twenty non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The 74ALVC16821 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The 74ALVC16821 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
s 1.65V-3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD 4.0 ns max for 3.0V to 3.6V VCC 4.9 ns max for 2.3V to 2.7V VCC 8.8 ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Supports live insertion and withdrawal (Note 1) s Uses patented noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance: Human body model > 2000V Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number 74ALVC16821MTD Package Number MTD56 Package Descriptions 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names OEn CLKn D0-D19 O0-O19 Description Output Enable Input (Active LOW) Clock Input Inputs Outputs
(c) 2001 Fairchild Semiconductor Corporation
DS500685
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74ALVC16821
Connection Diagram
Truth Tables
Inputs CLK1 OE1 H L L L Inputs CLK2 OE2 H L L L D10-D19 X L H X D0-D9 X L H X Outputs O0-O9 Z L H O0 Outputs O10-O19 Z L H O0

L or H
X

L or H
X
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance O0 = Previous O0 before LOW-to-HIGH transition of Clock = LOW-to-HIGH transition
Functional Description
The 74ALVC16821 contains twenty D-type flip-flops with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of each other. Control pins can be shorted together to obtain full 20-bit operation. The following description applies to each byte. The twenty flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CLK) transition. The 3-STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the flip-flops.
Logic Diagrams
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74ALVC16821
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC) DC Input Voltage (VI) Output Voltage (VO) (Note 3) DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (ICC or GND) Storage Temperature Range (TSTG)
-0.5V to +4.6V -0.5V to 4.6V -0.5V to VCC +0.5V -50 mA -50 mA 50 mA 100 mA -65C to +150C
Recommended Operating Conditions (Note 4)
Power Supply Operating Input Voltage (VI) Output Voltage (VO) Free Air Operating Temperature (TA) Minimum Input Edge Rate (t/V) VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 3: IO Absolute Maximum Rating must be observed. Note 4: Floating or unused control inputs must be held HIGH or LOW.
1.65V to 3.6V 0V to VCC 0V to VCC
-40C to +85C
DC Electrical Characteristics
Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VIL LOW Level Input Voltage 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VOH HIGH Level Output Voltage IOH = 100 A IOH = -4 mA IOH = -6 mA IOH = -12 mA 1.65 - 3.6 1.65 2.3 2.3 2.7 3.0 IOH = -24 mA VOL LOW Level Output Voltage IOL = 100 A IOL = 4 mA IOL = 6 mA IOL = 12 mA IOL = 24 mA II IOZ ICC ICC Input Leakage Current 3-STATE Output Leakage Quiescent Supply Current Increase in ICC per Input 0 VI 3.6V 0 VO 3.6V VI = V CC or GND, IO = 0 VIH = VCC - 0.6V 3.0 1.65 - 3.6 1.65 2.3 2.3 2.7 3.0 3.6 3.6 3.6 3 - 3.6 VCC - 0.2 1.2 2.0 1.7 2.2 2.4 2 0.2 0.45 0.4 0.7 0.4 0.55 5.0 10 40 750 A A A A V V Min 0.65 x VCC 1.7 2.0 0.35 x VCC 0.7 0.8 V V Max Units
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74ALVC16821
AC Electrical Characteristics
TA = -40C to +85C, RL = 500 Symbol Parameter CL = 50 pF VCC = 3.3V 0.3V Min fMAX tPHL, tPLH tPZL, tPZH tPLZ, tPHZ tW tS tH Maximum Clock Frequency Propagation Delay CLK to On Output Enable Time Output Disable Time Pulse Width Setup Time Hold Time 250 1.3 1.3 1.3 1.5 1.5 1.0 4.0 4.2 4.2 Max VCC = 2.7V Min 200 1.5 1.5 1.5 1.5 1.5 1.0 4.9 5.3 4.7 Max CL = 30 pF VCC = 2.5V 0.2V Min 200 1.0 1.0 1.0 1.5 1.5 1.0 4.4 4.7 4.2 Max VCC = 1.8V 0.15V Min 100 1.5 1.5 1.5 4.0 2.5 1.0 8.8 9.8 7.6 Max MHz ns ns ns ns ns ns Units
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter Conditions VI = 0V or VCC VI = 0V or VCC Outputs Enabled f = 10 MHz, CL = 50 pF TA = +25C VCC 3.3 3.3 3.3 2.5 Typical 6 7 20 20 pF pF pF Units
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74ALVC16821
AC Loading and Waveforms
TABLE 1. Values for Figure 1 TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open VL GND
FIGURE 1. AC Test Circuit TABLE 2. Symbol Vmi Vmo VX VY VL VCC 3.3V 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 6V 2.7V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 6V 2.5V 0.2V VCC /2 VCC /2 VOL + 0.15V VOH - 0.15V VCC*2 1.8V 0.15V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V VCC*2
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and trec Waveforms
FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic
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74ALVC16821 Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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