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74VHC4316 Quad Analog Switch with Level Translator
April 1994 Revised April 1999
74VHC4316 Quad Analog Switch with Level Translator
General Description
These devices are digitally controlled analog switches implemented in advanced silicon-gate CMOS technology. These switches have low "on" resistance and low "off" leakages. They are bidirectional switches, thus any analog input may be used as an output and vice-versa. Three supply pins are provided on the 4316 to implement a level translator which enables this circuit to operate with 0V-6V logic levels and up to 6V analog switch levels. The 4316 also has a common enable input in addition to each switch's control which when HIGH will disable all switches to their off state. All analog inputs and outputs and digital inputs are protected from electrostatic damage by diodes to VCC and ground.
Features
s Typical switch enable time: 20 ns s Wide analog input voltage range: 6V s Low "on" resistance: 50 typ. (VCC-VEE = 4.5V) 30 typ. (VCC-VEE = 9V) s Low quiescent current: 80 A maximum (74VHC) s Matched switch characteristics s Individual switch controls plus a common enable s Pin functional compatible with 74HC4316
Ordering Code:
Order Number 74VHC4316M 74VHC4316WM 74VHC4316MTC 74VHC4316N Package Number M16A M16B MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Truth Table
Inputs E H L L CTL X L H Switch I/O-O/I "OFF" "OFF" "ON"
Connection Diagram
Top View
Logic Diagram
(c) 1999 Fairchild Semiconductor Corporation
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74VHC4316
Absolute Maximum Ratings(Note 1)
(Note 2) Supply Voltage (VCC) Supply Voltage (VEE) DC Control Input Voltage (VIN ) DC Switch I/O Voltage (VIO ) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260C -0.5 to +7.5V +0.5 to -7.5V -1.5 to VCC+1.5V VEE-0.5 to VCC+0.5V 20 mA 25 mA 50 mA -65C to +150C 600 mW 500 mW
Recommended Operating Conditions
Min Supply Voltage (VCC) Supply Voltage (VEE) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC = 2.0V VCC = 4.5V VCC = 6.0V VCC = 12.0V 1000 500 400 250 ns ns ns ns -40 +85 C 2 0 0 Max 6 -6 VCC Units V V V
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating -- plastic "N" package: - 12 mW/C from 65C to 85C.
DC Electrical Characteristics
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage RON Minimum "ON" Resistance (Note 5) VCTL = V IH, IS = 2.0 mA VIS = VCC to VEE (Figure 1) VCTL = V IH, IS = 2.0 mA VIS = VCC or VEE (Figure 1) RON Maximum "ON" Resistance Matching IIN IIZ Maximum Control Input Current Maximum Switch "OFF" Leakage Current IIZ Maximum Switch "ON" Leakage Current ICC Maximum Quiescent Supply Current VOS = VCC or VEE VIS = VEE or VCC VCTL = V IL (Figure 2) VIS = VCC to VEE VCTL = V IH, VOS = OPEN (Figure 3) VIN = VCC or GND IOUT = 0 A VIN = VCC or GND VCTL = V IH VIS = VCC to VEE Conditions
(Note 4)
VEE VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V GND -4.5V -6.0V GND GND -4.5V -6.0V GND -4.5V -6.0V GND 4.5V 4.5V 6.0V 2.0V 4.5V 4.5V 6.0V 4.5V 4.5V 6.0V 6.0V 100 40 30 100 40 50 20 10 5 5 TA = 25C Typ 1.5 3.15 4.2 0.5 1.35 1.8 170 85 70 180 80 60 40 15 10 10 0.1 TA = -40C to +85C Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 200 105 85 215 100 75 60 20 15 15 1.0 A V V Units
GND -6.0V
6.0V 6.0V
30 50
300 500
nA
GND -6.0V GND -6.0V
6.0V 6.0V 6.0V 6.0V
20 30 1.0 4.0
75 150 10 40
nA
A
Note 4: For a power supply of 5V 10% the worst case on resistances (RON) occurs for VHC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at V CC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current occurs for CMOS at the higher voltage and so the 5.5V values should be used. Note 5: At supply voltages (VCC-VEE) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that these devices be used to transmit digital only when using these supply voltages.
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74VHC4316
AC Electrical Characteristics
VCC = 2.0V - 6.0V, VEE = 0V - 6V, CL = 50 pF unless otherwise specified Symbol tPHL, tPLH Parameter Maximum Propagation Delay Switch In to Out tPZL, tPZH Maximum Switch Turn "ON" Delay (Control) tPHZ, tPLZ Maximum Switch Turn "OFF" Delay (Control) tPZL, tPZH Maximum Switch Turn "ON" Delay (Enable) tPLZ, tPHZ Maximum Switch Turn "OFF" Delay (Enable) Minimum Frequency Response (Figure 7) 20 log (VOS/VIS)= -3 dB Control to Switch Feedthrough Noise (Figure 8) Crosstalk Between any Two Switches (Figure 9) Switch OFF Signal Feedthrough Isolation (Figure 10) THD Sinewave Harmonic Distortion (Figure 11) CIN CIN CIN CPD Maximum Control Input Capacitance Maximum Switch Input Capacitance Maximum Feedthrough Capacitance Power Dissipation Capacitance
Note 6: Adjust 0 dBm for f = 1 kHz (Null RL/Ron Attenuation). Note 7: VIS is centered at VCC-VEE/2. Note 8: Adjust for 0 dBm.
Conditions
VEE GND GND -4.5V -6.0V
VCC 3.3V 4.5V 4.5V 6.0V 3.3V 4.5V 4.5V 6.0V 3.3V 4.5V 4.5V 6.0V 3.3V 4.5V 4.5V 6.0V 3.3V 4.5V 4.5V 6.0V 4.5 4.5V 4.5V 4.5V 4.5V 4.5V
TA=+25C Typ 15 5 4 3 25 20 15 14 35 25 20 20 27 20 19 18 42 28 23 21 40 100 100 250 -52 -50 30 10 8 7 97 35 32 30 145 50 44 44 120 41 38 36 155 53 47 47
TA=-40C to +85C Guaranteed Limits 37 13 12 11 120 43 39 37 180 63 55 55 150 52 48 45 190 67 59 59
Units
ns
RL = 1 k
GND GND -4.5V -6.0V
ns
RL = 1 k
GND GND -4.5V -6.0V GND GND -4.5V -6.0V GND GND -4.5V -6.0V
ns
ns
ns
RL = 600, VIS = 2VPP at (VCC-VEE/2) (Note 6)(Note 7) RL = 600, f = 1 MHz CL = 50 pF (Note 7)(Note 8) RL = 600, f = 1 MHz
0V -4.5V 0V -4.5V 0V -4.5V
MHz
mV
dB
RL = 600, f = 1 MHz VCTL = VIL (Note 7)(Note 8) RL = 10 K, CL = 50 pF, f = 1 KHz VIS = 4 VPP VIS = 8 VPP 0V -4.5V 4.5V 4.5V 0.013 0.008 5 35 VCTL = GND 0.5 15 pF pF pF pF % 0V -4.5V 4.5V 4.5V -42 -44 dB
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74VHC4316
AC Test Circuits and Switching Time Waveforms
FIGURE 1. "ON" Resistance
FIGURE 2. "OFF" Channel Leakage Current
FIGURE 3. "ON" Channel Leakage Current
FIGURE 4. tPHL, tPLH Propagation Delay Time Signal Input to Signal Output
FIGURE 5. tPZL, tPLZ Propagation Delay Time Control to Signal Output
FIGURE 6. tPZH, tPHZ Propagation Delay Time Control to Signal Output
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74VHC4316
AC Test Circuits and Switching Time Waveforms
(Continued)
FIGURE 7. Frequency Response
FIGURE 8. Crosstalk: Control Input to Signal Output
FIGURE 9. Crosstalk between Any Two Switches
FIGURE 10. Switch OFF Signal Feedthrough Isolation
FIGURE 11. Sinewave Distortion
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74VHC4316
Typical Performance Characteristics
Typical "ON" Resistance Typical Crosstalk between Any Two Switches
Typical Frequency Response
Special Considerations
In certain applications the external load-resistor current may include both VCC and signal line components. To avoid drawing VCC current when switch current flows into the analog switch input pins, the voltage drop across the switch must not exceed 0.6V (calculated from the ON resistance).
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74VHC4316
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M16B
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74VHC4316
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
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74VHC4316 Quad Analog Switch with Level Translator
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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