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| = Preliminary Technical Data FEATURES 2.5V Stereo Audio Codec with 3.3 V Tolerant Digital Interface Supports 96 kHz Sample Rates Supports 16/18 /20/24-Bit Word Lengths Multibit Sigma Delta Modulators with "Perfect Differential Linearity Restoration" for Reduced Idle Tones and Noise Floor Data Directed Scrambling DACs - Least Sensitive to Jitter Performance (20 Hz to 20 kHz) 90 dB ADC and DAC SNR Digitally Programmable Input/Output Gain On-chip Volume Controls Per Output Channel Hardware and Software Controllable Clickless Mute Supports 256xFs, 512xFs and 768xFs Master Mode Clocks Master Clock Pre-Scaler for use with DSP master clocks Flexible Serial Data Port with Right-Justified, LeftJustified, I2S-Compatible and DSP Serial Port Modes Supports Packed Data Mode ("TDM") for cascading devices. On-Chip Reference 16, 20 and 24-Lead SOIC, SSOP and TSSOP Package options. APPLICATIONS Digital Video Camcorders (DVC) Portable Audio Devices (Walkman etc) Audio Processing Voice Processing Conference Phones General Purpose Analog I/O GENERAL DESCRIPTION CDIN CDOUT CCLK CLATCH Low Cost, Low Power Stereo Audio Analog Front End AD74322 FUNCTIONALBLOCKDIAGRAM DVDD1(EXT) DVDD2(INT) CLKIN AVDD VIN1P ADC SPI Port Control Block ADC CHANNEL 2 CHANNEL 1 VIN1N VIN2P VIN2N ASDATA/SDO DSDATA/SDI RY A IN AL IM IC LN RE CH A PE AT TD LRCLK/SDIFS DAC CHANNEL 1 VOUT1P I2S Port VOUT1N SDOFS Reference DAC CHANNEL 2 VOUT2P BCLK/SCLK VOUT2N DGND REFCAP AGND DVDD1(EXT) DVDD2(INT) CLKIN AVDD CDIN ADC Control Block ADC CHANNEL 2 VIN2 CDOUT CCLK SPI CHANNEL 1 VIN1 Port CLATCH ASDATA DSDATA DAC CHANNEL 1 VOUT1 LRCLK I2S Port Reference BCLK DAC CHANNEL 2 VOUT2 DGND REFCAP AGND The AD74322 is a front-end processor for general purpose audio and voice applications. It features two multi-bit A/D conversion channels and two multi-bit D/A conversion channels. Each ADC channel provides >85 dB signal-to-noise ratio while each DAC channel provides >90 dB, both over an audio signal bandwidth. The AD74322 is particularly suitable for a variety of applications where stereo input and output channels are required, including audio sections of Digital Video Camcorder, portable personal audio devices and the analog front ends of conference phones . Its high quality performance also make it suitable for speech and telephony applications such as speech recognition and synthesis and modern feature phones. DVDD1(EXT) DVDD2(INT) CLKIN AVDD ADC Control Block ADC CHANNEL 2 SDO SDI SDIFS SDOFS VIN2 CHANNEL 1 VIN1 DAC Data Port Reference CHANNEL 1 VOUT1 DAC CHANNEL 2 VOUT2 SCLK DGND REFCAP AGND REV. Pr D 03/00 One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A. .O. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1998 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. AD74322 An on-chip reference voltage is included but can be bypassed if required for use with an external reference source. The AD74322 offers sampling rates which, depending on MCLK selection and MCLK divider ratio, range from 8 kHz in the voiceband range to 96 kHz in the audio range. The digital interface to the AD74322 is configured as two separate ports which allow separation of device control and data streams. Control and status are monitored using an SPI(R) compatible serial port while the input and output data streams are controlled using an I2S(R) port. The two I2S streams are controlled by a common Bit-Clock and Left/Right Clock pins. There is also a DSP mode available on the audio data port which will also allow both control and data to be streamed through the same interface where controller resources are limited. The AD74322 is available in various lead count package options. These range from a 16-pin variant with singleended inputs/outputs and no SPI port through a 20-pin variant with single-ended inputs/outputs and an SPI port to a 24-pin variant with differential inputs/outputs and an SPI port. These devices will be available in SOIC, SSOP and TSSOP package options and are specified for the industrial temperature range of -40C to +85C. PRELIMINARY TECHNICAL DATA RY A IN AL IM IC LN RE CH A PE AT TD -2- Pr D 03/00 PRELIMINARY TECHNICAL DATA PARAMETER ANALOG-TO-DIGITAL CONVERTERS ADC Resolution (all ADCs) Dynamic Range (20 Hz to 20 kHz, -60 dB Input) No Filter With A-Weighted Filter Total Harmonic Distortion + Noise Interchannel Isolation InterchannelGainMismatch Programmable Input Gain Gain Step Size Offset Error Full Scale Input Voltage At Each Pin Automatic Level Control Attack Time Resolution Attack Time Decay Time Resolution Decay Time Gain Drift InputResistance InputCapacitance Common Mode Input Volts Min AD74322A Typ 24 90 92 -85(0.0056) TBD TBD 12 3 0.5 (1.414) TBD TBD TBD TBD TBD Max Units Bits dB dB dB(%) dB dB dB dB 0 LSB Vrms (Vpp) Bits s/Bit Bits s/Bit ppm/C k pF V Test Conditions AD74322 Single Ended DIGITAL-TO-ANALOG CONVERTERS Dynamic Range (20 Hz to 20 kHz, -60 dB Input) No Filter With A-Weighted Filter Total Harmonic Distortion + Noise Interchannel Isolation InterchannelGainMismatch DCAccuracy Gain Error Interchannel Gain Mismatch Gain Drift Interchannel Crosstalk (EIAJ method) Interchannel Phase Deviation Volume Control Step Size (1023 Linear Steps) Volume Control Range (Max Attenuation) MuteAttenuation De-emphasis Gain Error Full Scale Output Voltage At Each Pin Output Resistance At Each Pin Common Mode Output Volts REFERENCE(Internal) Absolute Voltage, VREF VREF TC ADCDECIMATIONFILTER Pass Band Pass Band Ripple TransitionBand Stop Band Stop Band Attenuation GroupDelay DACINTERPOLATIONFILTER Pass Band Pass Band Ripple TransitionBand Stop Band Stop Band Attenuation GroupDelay PR D 03/00 RY A IN AL IM IC LN RE CH A PE AT TD 10 15 1.1V 90 92 -85(0.0056) TBD TBD TBD TBD TBD TBD TBD 0.098 60 -100 dB dB dB(%) dB dB(%) 0.5 (1.414) ?? 2.25 1.1 TBD 0.xxxFs 0.00xx 0.xxFs % ppm/C dB dB Degrees % dB dB +/- 0.1 dB Vrms(Vpp) ?? V V ppm/C Hz dB Hz Hz dB ms Hz dB Hz Hz dB ms Single Ended 0.xxFs 0.xxFs 70 lll/Fs nnn/Fs mmm/Fs 0.xxxFs 0.00xx 0.xxFs 0.xxFs 0.xxFs 70 lll/Fs nnn/Fs -3- mmm/Fs AD74322-SPECIFICATIONS PARAMETER LOGICINPUT VINH, Input High Voltage VINL, Input Low Voltage Input Current InputCapacitance LOGICOUTPUT VOH, Output High Voltage VOL, Output Low Voltage Three-State Leakage Current POWERSUPPLIES AVDD,DVDD2 DVDD1 POWERCONSUMPTION All Sections On ADCsOnOnly DACsOnOnly Reference On Only PowerdownMode Min (AVDD = DVDD2 = +2.5V 10%, DVDD1 = 3.0V 10%, fCLKIN = 12.288 MHz, fSAMP = 48 kHz, TA = TMIN to TMAX, unless otherwise noted) AD74322A Typ Max DVDD1 0.8 +10 10 DVDD1 0.4 +10 Units V V A pF V V A V V m A m A m A m A A Test Conditions DVDD1 - 0.8 0 -10 DVDD1 - 0.4 0 -10 2.25 2.7 2.5 3.0 2.75 3.3 TBD TBD TBD TBD TBD RY A IN AL IM IC LN RE CH A PE AT TD -4- Pr D 03/00 PRELIMINARY TECHNICAL DATA ORDERING GUIDE AD74322 Model AD74322DAR AD74322DARU AD74322AAR AD74322AARU AD74322AAR AD74322AARU -40 -40 -40 -40 -40 -40 Range C C C C C C to to to to to to +85 +85 +85 +85 +85 +85 C C C C C C Package R-16 RU-16 R-20 RU-20 R-24 RU-24 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the XX0000 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. RY A IN AL IM IC LN RE CH A PE AT TD VINN1 1 24 VOUTN1 VINN2 2 VINN1 3 VINP1 4 REFCAP 5 AGND 6 DGND 7 DVDD2 8 TOP DVDD1 9 (Not toVIEW Scale) MCLK 10 CCLK 11 CIN 12 23 VOUTN2 22 VOUTN1 21 VOUTP1 20 AVDD 19 RESET 18 SDO 17 SDFS 16 SDI 15 SCLK 14 COUT 13 CLATCH VINP2 1 VINP1 2 REFCAP 3 AGND 4 DGND 5 DVDD2 6 TOP DVDD1 7 (Not toVIEW Scale) MCLK 8 CCLK 9 CIN 10 20 VOUTP2 19 VOUTP1 18 AVDD 17 RESET VINP2 1 VINP1 2 REFCAP 3 16 VOUTP2 15 VOUTP1 14 AVDD 13 RESET 12 SDO 11 SDFS 10 SDI 9 SCLK 16 SDO 15 SDFS 14 SDI 13 SCLK 12 COUT 11 CLATCH AGND 4 DGND 5 DVDD2 6 TOP DVDD1 7 (Not toVIEW Scale) MCLK 8 Pr D 03/00 -5- AD74322 Mnemonic VIN1 VIN2 VOUT1 VOUT2 REFCAP AVDD AGND DVDD1 DVDD2 DGND MCLK SDO SDI SDFS 4-5-6 SCLK I/O I I O O I/O Function PRELIMINARY TECHNICAL DATA PIN FUNCTION DESCRIPTION (SINGLE-ENDED I/O ; NO SPI PORT) I O I I/O I I/O Analog Input - Channel 1 Analog Input - Channel 2 Analog Output - Channel 1 Analog Output - Channel 2 Internal Reference - Can also be used for connection of an external reference Analog Power Supply Connection AnalogGround/SubstrateConnection Digital Power Supply Connection (Interface) Digital Power Supply Connection (Core) DigitalGround/SubstrateConnection ExternalClockConnection ADC Serial Data Out - DSP Mode DAC Serial Data In - DSP Mode Serial Data Input Frame Sync - DSP Mode Powerdown/Reset Input Serial Clock - DSP Mode PIN FUNCTION DESCRIPTION (SINGLE-ENDED I/O WITH SPI PORT) Mnemonic VIN1 VIN2 VOUT1 VOUT2 REFCAP AVDD AGND DVDD1 DVDD2 DGND MCLK CDIN CDOUT CCLK CLATCH ASDATA DSDATA LRCLK/ BCLK RESET I/O I I O O I/O Function I I O I I O I I/O I/O I Analog Input - Channel 1 Analog Input - Channel 2 Analog Output - Channel 1 Analog Output - Channel 2 Internal Reference - Can also be used for connection of an external reference Analog Power Supply Connection Analog Ground/Substrate Connection Digital Power Supply Connection (Interface) Digital Power Supply Connection (Core) Digital Ground/Substrate Connection External Clock Connection Serial Data In on SPI Control Port Serial Data Out on SPI Control Port Serial Clock on SPI Control Port Serial Data Latch on SPI Control Port ADC Serial Data Out - I2S DAC Serial Data In - I2S Left/Right Channel Select - I2 S Bit Clock - I2S Powerdown/Reset Input RY A IN AL IM IC LN RE CH A PE AT TD -6- Pr D 03/00 PRELIMINARY TECHNICAL DATA PIN FUNCTION DESCRIPTION (DIFFERENTIAL I/O WITH SPI PORT) AD74322 Mnemonic VINP1 VINN1 VINP2 VINN2 VOUTP1 VOUTN1 VOUTP2 VOUTN2 REFCAP AVDD AGND DVDD1 DVDD2 DGND MCLK CDIN CDOUT CCLK CLATCH ASDATA DSDATA LRCLK/ BCLK RESET I/O I I I I O O O O I/O Function Analog Input - Channel 1 Positive Analog Input - Channel 1 Negative Analog Input - Channel 2 Positive Analog Input - Channel 2 Negative Analog Output - Channel 1 Positive Analog Output - Channel 1 Negative Analog Output - Channel 2 Positive Analog Output - Channel 2 Negative Internal Reference - Can also be used for connection of an external reference Analog Power Supply Connection Analog Ground/Substrate Connection Digital Power Supply Connection (Interface) Digital Power Supply Connection (Core) Digital Ground/Substrate Connection External Clock Connection Serial Data In on SPI Control Port Serial Data Out on SPI Control Port Serial Clock on SPI Control Port Serial Data Latch on SPI Control Port ADC Serial Data Out - I2S DAC Serial Data In - I2S Left/Right Channel Select - I2 S Bit Clock - I2S Powerdown/Reset Input I I O I I O I I/O I/O I RY A IN AL IM IC LN RE CH A PE AT TD Pr D 03/00 -7- AD74322 FUNCTIONAL DESCRIPTION ADCSection Reference PRELIMINARY TECHNICAL DATA The AD74322 features an on-chip reference whose nominal value is 1.125 V.A __ nF capacitor applied at the REFCAP pin is necessary to stabilise the referrence. (See Figure There are two ADC channels in the AD74322, configured as a stereo pair. Each ADC channel can be independently muted. The input pins are switched between differential inputs or four single ended inputs accordingly. The gain block can be programmed for independent left and right gains, in steps of +3dB, from 0dB to +12dB. The ADC operates at an oversampling ratio of 128 and the decimation filter reduces the output to the standard sample rates. The output maximum sample rate is 96 kHz at ASDATA. AutomaticLevelControl AnalogSigmaDeltaModulator DecimatorSection AD743xx REFCAP The digital decimation filter has a passband ripple of 0.01dB and a stopband attenuation of 70dB. The filter is an FIR type with a linear phase response. The group delay at 48kHz is ??us. Output sample rates up to 96 kHz are supported. Input Signal swing Each ADC input has an input range of 0.5 VRMS / 1.414 VP-P (SingleEnded) about a bias point equal to VREFCAP (See Figure 1.414 V P-P VREFCAP 1.414 V P-P VREFCAP Figure DACSection RY A IN AL IM IC LN RE CH A PE AT TD AD743xx VINPx 1.0 V Figure If it is required to use an external reference, because of its value or its reference tempco, the internal reference can be disabled via Control Register __ and the external reference applied at the REFCAP pin (See Figure AD743xx REFCAP VINNx EXTERNAL REFERENCE The AD74322 has two DAC channels arranged as a stereo pair, with two, fully differential voltage, analog outputs for improved noise and distortion performance. Each channel has it's own independently programmable attenuator with a maximum attenuation of 63dB, adjustable in 1dB steps. Digital inputs are via a serial data input pin and a common frame (DLRCLK) and bit (DBLCK) clock or using a `packed data' mode, both channels can be input using a single data pin. InterpolatorSection Digital Sigma Delta Modulator DAC Analog Output Filter OutputSignalswing Figure MasterClockingScheme Each ADC input has an output range of 0.5 VRMS / 1.414 VP-P (SingleEnded) about a bias point equal to VREFCAP (See Figure The update rate of the AD74322's ADC and DAC channels require an internal master clock (IMCLK) which is 256 times that sample update rate (IMCLK = 256 * FS). In order to provide some flexibility in selecting sample rates, the device has a series of three master clock pre-scalers which are programmable and allow the user to choose a range of convenient sample rates from a single external master clock. The master clock signal to the AD74322 is applied at the MCLK pin. The MCLK signal is passed through a series of two programmable MCLK pre-scalers (divider) circuits which can be selected to reduce the resulting Internal MCLK (IMCLK) frequency if required. The first MCLK prescaler provides divider ratios of /1 (pass through), /2, /3 while the second pre-scaler provides divider ratios of ./1 (pass through), /2, /4 and the third pre-scaler provides ratios of /1 (pass through), /2 and /5.. Programmable MCLK Divider Pre-Scaler 1 Pre-Scaler 2 MCLK /1 /2 /1 /2 /4 AD743xx 1.414 V P-P VREFCAP VOUTPx IMCLK 1.414 V P-P VREFCAP VOUTNx /3 Control Reg Figure -8- Pr D 03/00 PRELIMINARY TECHNICAL DATA FILTER 2.4 V 3.3 V DUAL REGULATOR 5.0 V AD74322 AVDD VDD2 VDD1 DVDD 4 AD743xx 4 DSP AGND Figure The divider ratios will allow more convenient sample rate selection from a common MCLK which may be required in many voice related applications. Example 1: fSAMP = 48 kHz and 8 kHz required 3 MCLK = 48*10 * 256 = 12.288 MHz to cater for 48 kHz fSAMP RY A IN AL IM IC LN RE CH A PE AT TD DGND DGND Figure a known state following the power-up of the device. There is also a software reset capability available by setting the RESET bit in Control Register _. This control register is accessed through the Control Port. Power Supplies and Grounds The AD74322 features three separate supplies: AVDD, DVDD1 and DVDD2. AVDD is the supply to the analog section of the device and must therefore be of sufficient quality to preserve the AD74322's performance characteristics. It is nominally a 2.4 V supply. DVDD1 is the supply for the digital interface section of the device. It is fed from the digital supply voltage of the DSP or controller to which the device is interfaced and allows the AD74322 to interface with devices operating at supplies of between 2.4 V -5% to 3.3 V + 10%. DVDD2 is the supply for the digital core of the AD74322. It is nominally a 2.4 V supply. For fSAMP = 8 kHz, it is necessary to use the /3 setting in Pre-Scaler 1, the /2 setting in Pre-Scaler 2 and pass through in Pre-Scaler 3. This results in an IMCLK = 8*103 * 256 = 2.048 MHz (= 12.288 MHz/6). Example 2: fSAMP = 48 kHz and 32 kHz required MCLK = 24.576 MHz For fSAMP = 48 kHz, it is necessary to use the /2 setting in Pre-Scaler 1 and the /1 (pass-through) setting in PreScaler 2 and pass through in Pre-Scaler 3. This results in an IMCLK = 48*103 * 256 = 12.288 MHz. For fSAMP = 32 kHz, it is necessary to use the /3 setting in Pre-Scaler 1 and the /1 (pass-through) setting in PreScaler 2 and pass through in Pre-Scaler 3. This results in an IMCLK = 32*103 * 256 = 8.192 MHz. Example 3: fSAMP = 44.1 kHz and 11.025 kHz required MCLK = 44.1*103 * 256 = 11.2896 MHz to cater for 44.1 kHz fSAMP For fSAMP = 11.025 kHz, it is necessary to use the /1 setting in PreScaler 1 and the /4 setting in Pre-Scaler 2 and pass through in Pre-Scaler 3. This results in an IMCLK = 11.025*103 * 256 = 2.8224 MHz (= 11.2896 MHz/4). SampleRates For all applications the sampling rate is defined by the internal master clock frequency (IMCLK) where IMCLK = 256 * fSAMP. Power-On Reset The AD74322 features a power-on reset circuit which Pr D ensures 03/00 all internal circuitry is reset and initialised to -9- that AD74322 M CLK (M Hz) PRELIMINARY TECHNICAL DATA Sampling Rate s (kHz) us ing Scalar (Divide r) Ratios (as s ume s 256fs ) 1 8 48 64 96 2 4 24 32 48 3 4 2 12 16 24 5 6 8 1 6 8 12 9 10 12 12 15 - 2.048 12 . 2 8 8 16.384 24.576 36.864 48 Sampling Rate fS (kHz) 8 16 11.1 22.2 32 64 44.1 88.2 48 96 Interpolator Mode 8x (Normal) 4x (Double) 8x (Normal) 4x (Double) 8x (Normal) 4x (Double) 8x (Normal) 4x (Double) 8x (Normal) 4x (Double) RY A IN AL IM IC LN RE CH A PE AT TD 24 Table MCLK (MHz) 512fS 4.096 5.6448 16.384 22.5792 24.576 768fS 6.144 8.4672 24.576 33.8688 36.864 256fS 2.048 2.8224 8.192 11.2896 12.288 Table -10- Pr D 03/00 PRELIMINARY TECHNICAL DATA INTERFACING AD74322 Data in and out of the Control Port go through a 16-bit shift register whose contents are mapped to the internal registers using the mapping scheme of Figure DataInterface The AD74322 features two separate interfaces, Control and Data, which are used to program control settings and send/receive sample data respectively. The Control interface is implemented using an SPI type protocol but transfers 16-bits per frame. The Data interface uses either a DSP or I2S protocol to transfer stereo data samples between controller and codec. The DSP compatible interface mode allows data samples to be transferred in a protocol that is supported by the serial interfaces of most fixed- and floating-point DSPs. In order to reduce peripheral requirements when interfacing the AD74322 with the host DSP, the DSP mode allows the DSP to send both data and control information to the device via the data interface. This is the default mode and requires users to only use a single DSP SPORT to both control the device and service it with data samples. ControlInterface Control of the AD74322 operation is via a set of 16 Control Registers which are programmed through the Control Port. The Control Port protocol is similar to the SPIO protocol with the exception that 16-bits of data are transferred per frame. The Control Port consists of the following pins: CCLK - Control Port Serial Clock, CLATCH - Control Port Latch or Frame signal, CDIN - Control Port Serial Data In and CDOUT Control Port Data Out. CLATCH is a framing signal that is active low. When asserted, it gates the other interface lines as being active. CCLK is used to clock input data on CDIN and clock output (readback) data on CDOUT. Figure CDIN CLATCH CCLK CDOUT RY A IN AL IM IC LN RE CH A PE AT TD DSPMode There are two modes of operation of the data interface: DSP mode and I2S mode. The default mode of the data interface is a DSP mode which combines control and data functions in a single protocol. This is to reduce the peripheral overhead required on the DSP when interfacing to the AD74322. This mode operates in a standard DSP serial format. In I2S mode the data interface streams audio data samples being sent to or received from the DACs and ADCs respectively, using the I2S serial protocol. In either mode it can be configured as either a master or slave device ensuring connectivity to the largest number of host processors. The DSP mode allows interfacing to most fixed- and floating-point DSPs as well as other processors such as RISCs etc that having serial ports that support synchronous communications. The key feature of synchronous DSP communications is that the serial data is framed by a separate Frame Sync signal. Figures AD743xx AD743xx (MASTER) LRCLK/SDIFS DSDATA/SDI BCLK/SCLK ASDATA/SDO SDOFS TFS DSP (SLAVE) DT SCLK DR RFS CONTROLLER Figure CCLK CDIN MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB CDOUT MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB CLATCH Figure Pr D 03/00 -11- AD74322 BCLK/ SCLK LRCLK/ FS DSDATA/ SDI ASDATA/ SDO PRELIMINARY TECHNICAL DATA CONTROL LEFT DAC RIGHT DAC STATUS LEFT ADC RIGHT ADC Figure TFS DSP (MASTER) DT SCLK DR RFS Figure The serial protocol uses a fixed position for data being sent to or received from the Left and Right DACs and ADCs respectively and the control words being sent to and the status words being received from the device respectively. Figure I2S (Inter IC Sound Bus) Mode RY A IN AL IM IC LN RE CH A PE AT TD AD743xx (SLAVE) LRCLK/SDIFS TFS LRCLK/SDIFS DSDATA/SDI BCLK/SCLK ASDATA/SDO DSDATA/SDI BCLK/SCLK ADSP21065L DT TCLK ASDATA/SDO SDOFS (MASTER) DR RFS AD743xx (SLAVE) RCLK Figure TFS LRCLK/SDIFS DSDATA/SDI BCLK/SCLK ASDATA/SDO The I2S bus is a three line serial bus which features a serial data line carrying both left and right (stereo) channels. The Left and Right channel information are selected by the status of the Left/Right Clock (Word Select) line. Serial data is clocked by the Bit Clock line. Figures ADSP21065L DT TCLK DR RFS RCLK (MASTER) AD743xx (SLAVE) Figure LRCLK BCLK SDATA MSB LEFT CHANNEL RIGHT CHANNEL LSB MSB LSB I2S MODE - 16 TO 24-BITS PER CHANNEL Figure -12- Pr D 03/00 PRELIMINARY TECHNICAL DATA AD74322 AD743xx AD743xx CDIN CLATCH CCLK CDOUT CDIN CLATCH CCLK CDOUT CONTROL DATA IN CONTROL DATA OUT CONTROL DATA LATCH CONTROL DATA CLOCK CCLK CDIN MSB DEV N 14 13 CDOUT MSB DEV N 14 13 RY A IN AL IM IC LN RE CH A PE AT TD Figure 12 11 10 9 8 8 7 6 5 DEV N 8 DEV 1 8 12 11 10 9 7 6 5 DEV N DEV 1 4 3 2 1 LSB DEV 1 4 3 2 1 LSB DEV 1 CLATCH Figure INTERFACING MULTIPLE DEVICES Many applications require multiple channels of input and output. The AD743xx series of devices are designed to cater for extending the number of I/O channels by cascading devices together while interfacing to a single control or data port. This reduces the overhead requirement on the controller in terms of serial ports. ControlPortCascading There are two methods of cascading the Control Ports of multiple AD743xx devices together so that all devices can be controlled from a single controller serial port. One method is to configure the multiple devices as a daisy chain of Control Ports each 16-bits wide with common Pr D 03/00 -13- AD74322 PRELIMINARY TECHNICAL DATA AD743xx AD743xx CDIN CLATCH CCLK CDOUT CDIN CLATCH CCLK CDOUT CONTROL DATA IN CONTROL DATA OUT CONTROL DATA CLOCK CONTROL DATA LATCH 1 CONTROL DATA LATCH N CCLK CDIN MSB DEV N 14 RY A IN AL IM IC LN RE CH A PE AT TD Figure 5 4 3 2 1 0 MSB 14 13 DEV N DEV 1 5 4 3 2 1 0 MSB 14 13 DEV N DEV 1 3 2 1 LSB DEV 1 CDOUT MSB DEV N 14 3 2 1 LSB DEV 1 CLATCH N CLATCH 1 Figure -14- Pr D 03/00 PRELIMINARY TECHNICAL DATA AD74322 AD743xx (SLAVE) LRCLK/ DSDATA/ SDIFS SDI BCLK/ SCLK ASDATA/ SDO AD743xx (SLAVE) LRCLK/ DSDATA/ SDIFS SDI BCLK/ SCLK ASDATA/ SDO SDOFS SDOFS TFS DSP (MASTER) DT SCLK DR RFS Clock and Latch signals. The other method involves creating a common Data In and Data Out buses where each device has a common Clock but has separate Latch signals which enable the devices on the bus at different times - either as a Time Division Multiplex (TDM) or software control. DaisyChainMode RY A IN AL IM IC LN RE CH A PE AT TD DACs (with I2S interfaces) to be interfaced to a cascade of AD743xx devices. This allows extra flexibility in choosing the number of input and out channels in the cascade. The various (potential) modes for interfacing the data ports of multiple devices are listed below: DSP Mode - Daisy Chaining In Daisy Chain Mode, the serial registers (16-bit) of each device are cascaded together by connecting the controller's Data Out to CDIN of the first device and the CDOUT of the first device to CDIN of the next device (see Figure TDMMode In this mode, sample data is passed along a daisychain of I/O registers in a similar manner that used in the present AD733xx devices. At the sample event each ADC result is placed in the I/O register and is subsequently shifted towards the DSP's Rx register. This achieved by a common SDIFS pulse which samples each device (enables each device's sample). {Drawback: as the device is stereo, we would need to send 32 bits (or perhaps more) to the I/ O register at each sample event.} TDMMode In multiplexed mode, each device is programmed with its cascade position. This allows devices to be enabled to the data buses only in their appropriate time-slot as defined by the initial frame-sync signal. In TDM Mode, each device's CDIN and CDOUT are commoned to the controller's Data Out and Data In respectively (see Figure Data Port Cascading The Data Port of the AD74322 is designed to allow multiple single or dual channel devices to be cascaded from a single DSP or controller serial port (SPORT). There is also a mode which allows stereo ADCs and Pr D 03/00 -15- AD74322 REGISTER ADDRESS 15 14 13 12 R/W RES 11 10 9 8 7 6 PRELIMINARY TECHNICAL DATA DATA FIELD 5 4 3 2 1 0 Note: Bit 15 = MSB Figure REGISTER ADDRESS 15 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 14 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 13 0 0 1 1 0 0 0 1 1 1 0 0 1 1 0 0 1 1 12 0 1 0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 1 R/W 11 RES 10 9 8 7 6 DATA FIELD 5 4 3 2 1 0 Power Settings 0 1 0 1 RY A IN AL IM IC LN RE CH A PE AT TD Reserved Reserved Reserved Reserved Clock Dividers Serial Port Control Mute Control Input/O utput Configuration ADC0 Gain Setting ADC0 Peak Level ADC1 Gain Setting ADC1 Peak Level I/O Filter Select DAC0 Gain Setting DAC1 Gain Setting REF Trim Control Test Mode Control Figure -16- Pr D 03/00 PRELIMINARY TECHNICAL DATA REG ADDRESS AD74322 Power Control PUR PUD1 PUD0 PUA3 PUA2 PUA1 PUA0 PU R/W RES RESET PURA 15 - 12 11 10 9 8 Power Up Reference Amplifier 7 Power Up Reference 6 Power Up DAC1 5 Power Up DAC0 4 Power Up ADC3 3 Power Up ADC2 2 Power Up ADC1 1 Power Up ADC0 0 Global Power Up 0000 Software Reset Table REG ADDRESS R/W RES 15 - 12 0000 11 10 9 RY A IN AL IM IC LN RE CH A PE AT TD Clock Dividers BCD2-0 Reserved MCD2-0 8 7 6 5 4 3 2 1 Master Clock Divider 0 Bit Clock Divider Serial Interface Control DDF1 DDF0 REG ADDRESS R/W RES DSTDME TPOS2 TPOS1 TPOS0 ADF1 ADF0 DSMM DSMS 15 - 12 0000 11 10 9 TDM Mode Enable 8 TDM Mode Position 2 7 TDM Mode Position 1 6 TDM Mode Position 0 5 DAC Data Format 2 4 DAC Data Format 2 3 ADC Data Format 2 2 ADC Data Format 1 1 Mixed-Mode Enable 0 Master/ Slave Mode Mute Control REG ADDRESS R/W RES DWW1 DWW0 AWW1 AWW0 DMUTE1 DMUTE0 AMUTE1 AMUTE0 15 - 12 0000 11 10 9 DAC Word Width 1 8 DAC Word Width 0 7 ADC Word Width 1 6 ADC Word Width 0 5 Mute DAC 1 4 Mute DAC 0 3 Reserved 2 Reserved 1 Mute ADC 1 0 Mute ADC 0 Pr D 03/00 -17- AD74322 REG ADDRESS R/W RES PRELIMINARY TECHNICAL DATA ADC Configuration PEAKE 9 ADC Peak Level Reading RES DLB DSLB ALB1 ALB0 INV1 INV0 SEE1 SEE0 15 - 12 0111 11 10 8 Reserved 7 Digital Loopback 6 Data SPORT Loopback 5 Analog Loopback Ch1 4 Analog Loopback Ch0 3 Invert ADC1 Inputs 2 Invert ADC0 Inputs 1 ADC1 in Single Ended Mode 0 ADC0 in Single Ended Mode REG ADDRESS R/W RES 15 - 12 0001 11 0 1 10 9 A0P9 REG ADDRESS R/W RES RY A IN AL IM IC LN RE CH A PE AT TD A0G9- 0 8 7 6 5 4 3 Reserved ADC0 Peak Readback ADC0 Gain Setting/Peak Readback 2 1 A0G1 0 A0G0 A0P0 ADC1 Gain Setting/Peak Readback A1G9- 0 15 - 12 0001 11 0 1 10 9 8 7 6 Reserved 5 4 3 2 1 A1G1 0 A1G0 A0P0 A1P9 ADC1 Peak Readback REG ADDRESS DAC0 Gain Setting R/W RES D0G9-0 11 10 9 D0G9 15 - 12 0101 8 7 6 5 4 3 2 1 0 D0G0 DAC0 Gain Setting -18- Pr D 03/00 PRELIMINARY TECHNICAL DATA REG ADDRESS AD74322 DAC1 Gain Setting D1G9-0 R/W RES 15 - 12 0110 11 10 9 D1G9 8 7 6 5 4 3 2 1 0 D1G0 DAC1 Gain Setting REG ADDRESS R/W RES BMF 15 - 12 0000 11 10 9 Blow Master Fuse RY A IN AL IM IC LN RE CH A PE AT TD Trim Control LTE LT3-0 ST3-0 8 7 6 5 4 3 2 1 0 Link Trim Enable Link Trim Software Trim REG ADDRESS Test Mode Control R/W RES TME1-0 DI3-0 AI3-0 15 - 12 0000 11 10 9 8 7 6 5 4 3 2 1 0 Test Mode Control DAC Current Settings ADC Current Settings Pr D 03/00 -19- AD74322 PRELIMINARY TECHNICAL DATA OUTLINE DIMENSIONS (STYLE: outline hd) Dimensions shown in inches and (mm). (STYLE: outline sub) RY A IN AL IM IC LN RE CH A PE AT TD -20- Pr D 03/00 PRINTED IN U.S.A. 00000000 |
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