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CXD2507AQ
CD Digital Signal Processor For the availability of this product, please contact the sales office.
Description The CXD2507AQ is a digital signal processor for CD players and is equipped with the following functions. Features * Digital PLL * EFM frame sync protection * SEC strategy-based error correction * Subcode demodulation, CRC checking * Digital spindle servo * Servo auto-sequencer * Asymmetry compensation circuit * Digital audio interface output * 16K RAM * Double-speed playback capability * New microcomputer interface circuit Absolute Maximum Ratings * Supply voltage VDD -0.3 to +7.0 * Supply voltage variation VSS - AVSS -0.3 to +0.3 VDD - AVDD -0.3 to +0.3 * Input voltage VI -0.3 to +7.0 VIN VSS - 0.3 to VDD + 0.3 * Output voltage VO -0.3 to +7.0 * Storage temperature Tstg -40 to +125 Recommended Operating Conditions * Supply voltage VDD 64 pin QFP (Plastic) -L01 -L121
V V V V V V C
* Operating temperature
Topr
4.5 to 5.5V (double-speed playback) 3.5 to 5.5V (normal-speed playback) 3.0 to 5.5V (low power consumption, special playback mode) -20 (min.) 75 (max.) C
When the internal operation of the LSI is set to double-speed mode and the crystal oscillation frequency is halved, normal-speed playback results.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E94601A11
CXD2507AQ
Pin Configuration
WFCK
SQSO
SCOR
EMPH
MUTE
SQCK
SBSO
DOUT
XTAO
DATA
XRST
SENS
EXCK
FSTT
XTSL
Vss
C4M
51 XLAT 52 CLOK 53 SEIN 54 CNIN 55 DATO 56 XLTO 57 VDD 58 CLKO 59 SPOA 60 SPOB 61 SPOC 62 SPOD 63 XLON 64 1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
XTAI
34
33 32 MNT1 31 MNT3 30 XROF 29 C2PO 28 RFCK 27 GFS 26 VDD 25 XPCK 24 XUGF 23 GTOP 22 BCK 21 PCMD 20 LRCK
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
-2-
WDCK
ASYO
LOCK
ASYE
CLTV
AVss
TEST
AVDD
MON
BIAS
ASYI
MDP
FILO
MDS
PCO
FOK
FILI
Vss
RF
MNT0
19
CXD2507AQ
Block Diagram
WDCK
PCMD
MUTE
28 29 48
19 20 21 22
39
D/A Interface
Digital OUT 30 5 Digital CLV 4 3 2 XROF LOCK MDS MDP MON
MNT0 33 MNT1 32 MNT3 31 Error corrector 16K RAM
DOUT
RFCK
C2PO
LRCK
BCK
47 46 45 44
SQCK SQSO EXCK SBSO SCOR XLON SPOA to D CLOK XLAT DATA SENS
WFCK 41 EMPH 40 GFS 27 XUGF 24 GTOP 23 EFM Demodulator SUB code processor
CPU Interface
43 64 60 53 52 51 49
59 XTSL 36 XTAO 35 XTAI 34 Clock generator Asymmetry corrector Digital PLL Servo auto sequencer 57
CLKO XLTO
56 DATO
37
38
14
16 17 18 15
25 7
8
9 12
1
54
55
ASYE
BIAS
C4M
FSTT
FILO
FILI
CLTV
XPCK
ASYO
-3-
CNIN
PCO
FOK
SEIN
ASYI
RF
CXD2507AQ
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Symbol FOK MON MDP MDS LOCK TEST FILO FILI PCO VSS AVSS CLTV AVDD RF BIAS ASYI ASYO ASYE WDCK LRCK PCMD BCK GTOP XUGF XPCK VDD GFS RFCK C2PO XROF MNT3 MNT1 MNT0 XTAI XTAO XTSL I O O O O I O I O -- -- I -- I I I O I O O O O O O O -- O O O O O O O I O I 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 -- 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 -- 1, Z, 0 -- -- Analog 1, 0 1, Z, 0 1, Z, 0 1, 0 I/O Description Focus OK input. Used for SENS output and the servo auto sequencer. Spindle motor on/off control output. Spindle motor servo control. Spindle motor servo control. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. TEST pin. Normally GND. Master PLL (slave = digital PLL) filter output. Master PLL filter input. Master PLL charge pump output. GND. Analog GND. Master VCO control voltage input. Analog power supply (+5V). EFM signal input. Constant current input of asymmetry circuit. Asymmetry comparator voltage input. EFM full-swing output (low = Vss, high = VDD). Low: asymmetry circuit off; high: asymmetry circuit on. D/A interface. Word clock f = 2Fs. D/A interface. LR clock f = Fs. D/A interface. Serial data (two's complement, MSB first). D/A interface. Bit clock. GTOP output. XUGF output. XPLCK output. Power supply (+5V). GFS output. RFCK output. C2PO output. XRAOF output. MNT3 output. MNT1 output. MNT0 output. 16.9344MHz crystal oscillation circuit input, or 33.8688MHz input. 16.9344MHz crystal oscillation circuit output. Crystal selection input. Set low when the crystal is 16.9344MHz, high when 33.8688MHz. -4-
CXD2507AQ
Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Notes)
Symbol FSTT C4M DOUT EMPH WFCK VSS SCOR SBSO EXCK SQSO SQCK MUTE SENS XRST DATA XLAT CLOK SEIN CNIN DATO XLTO VDD CLKO SPOA SPOB SPOC SPOD XLON O O O O O -- O O I O I I O I I I I I I O O -- O I I I I O
I/O 1, 0 1, 0 1, 0 1, 0 1, 0 -- 1, 0 1, 0
Description 2/3 frequency divider output for Pins 34 and 35. 4.2336MHz output. Digital Out output. Outputs high signal when the playback disc has emphasis, low signal when no emphasis. WFCK output. GND. Outputs high signal when either subcode sync S0 or S1 is detected. Sub P to W serial output. SBSO readout clock input.
1, 0
SubQ 80-bit serial output. SQSO readout clock input. High: mute; low: release
1, 0
SENS output to CPU. System reset. Reset when low. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Serial data transfer clock input from CPU. Sense input from SSP. Track jump count signal input.
1, 0 1, 0 -- 1, 0
Serial data output to SSP. Serial data latch output to SSP. Latched at the falling edge. Power supply (+5V). Serial data transfer clock output to SSP. Microcomputer extended interface (input A). Microcomputer extended interface (input B). Microcomputer extended interface (input C). Microcomputer extended interface (input D).
1, 0
Microcomputer extended interface (output).
* PCMD is two's complement output of MSB first. * GTOP is used to monitor the frame sync protection status. * XUGF is the negative pulse for the frame sync derived from the EFM signal. It is the signal before sync protection. * XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide. * GFS goes high when the frame sync and the insertion protection timing match. * RFCK is derived from the crystal accuracy. This signal has a cycle of 136. * C2PO represents the data error status. * XRAOF is generated when the 16K RAM exceeds the 4F jitter margin.
-5-
CXD2507AQ
Electrical Characteristics DC Characteristics Item
Output voltage (3) Output voltage (2) Output voltage (1) Input voltage (3) Input voltage (2) Input voltage (1)
(VDD = AVDD = 5.0V 5%, VSS = AVSS = 0V, Topr = -20 to +75C) Conditions VIH (1) VIL (1) VIH (2) Schmitt input VIL (2) 0.8VDD 0.2VDD Min. 0.7VDD 0.3VDD Typ. Max. Unit V V V V Applicable pins 1
High level input voltage Low level input voltage High level input voltage Low level input voltage
2
Input voltage
VIN (3)
Analog input
VSS
VDD
V
3
High level output voltage Low level output voltage High level output voltage Low level output voltage High level output voltage Low level output voltage
VOH (1) VOL (1) VOH (2) VOL (2) VOH (4) VOL (4) ILI ILO
IOH = -4mA IOL = 4mA IOH = -2mA IOL = 4mA IOH = -0.28mA IOL = 0.36mA VI = 0 to 5.25V VO = 0 to 5.25V
VDD - 0.8 0 VDD - 0.8 0 VDD - 0.5 0
VDD 0.4 VDD 0.4 VDD 0.4 5 5
V V V V V V A A
4
5
6
Input leak current Tri-state pin output leak current
1, 2, 3 7
Applicable pins 1 XTSL, DATA, XLAT 2 CLOK, XRST, EXCK, SQCK, MUTE, FOK, SEIN, CNIN, ASYE
3 CLTV, FILI, RF 4 MDP, PCO 5 ASYO, DOUT, FSTT, C4M, C16M, SBSO, SQSO, SCOR, EMPH, MON, LOCK, WDCK, DATO, CLKO, XLTO, SENS, MDS, LRCK, WFCK, PCMD, BCK, GTOP, XUGF, XPCK, GFS, RFCK, XROF, MNT0, MNT1, MNT3 6 FILO 7 MDS, MDP, PCO
-6-
CXD2507AQ
AC Characteristics 1) XTAI and VCOI pins (1) When using self-oscillation (Topr = -20 to +75C, VDD =AVDD = 5.0V 5%) Item Oscillation frequency Symbol fMAX Min. 7 Typ. Max. 34 Unit MHz
(2) When inputting pulses to XTAI and VCOI (Topr = -20 to +75C, VDD = AVDD = 5.0V 5%) Item High level pulse width Low level pulse width Pulse cycle Input high level Input low level Rise time, fall time Symbol Min. 13 13 26 VDD - 1.0 0.8 10 Typ. Max. 500 500 1,000 Unit ns ns ns V V ns
tWHX tWLX tCX
VIHX VILX
tR, tF
tCX tWHX tWLX VIHX VIHX x 0.9
XTAI
VDD/2
VIHX x 0.1 VILX tR tF
(3) When inputting sine waves to XTAI and VCOI pins via a capacitor (Topr = -20 to +75C, VDD = AVDD = 5.0V 5%) Item Input amplitude Symbol V1 Min. 2.0 Typ. Max. Unit
VDD + 0.3 Vp-p
-7-
CXD2507AQ
2) CLOK, DATA, XLAT, CNIN, SQCK EXCK pins (VDD = AVDD = 5.0V 5%, VSS = AVSS = 0V, Topr = -20 to +75C) Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK SQCK frequency EXCK SQCK pulse width Symbol fCK Min. Typ. Max. 0.65 750 300 300 300 750 0.65 750
1/fCX tWCK CLK tWCK
Unit MHz ns ns ns ns ns MHz ns
tWCK tSU tH tD tWL
fT
tWT
DATA XLT tSU EXCK CNIN SQCK tH tD tWL
tWT 1/fr
tWT
SBSO SQSO tSU tH
In low power consumption and special playback mode, when SL0 = SL1 = 1, the maximum operating frequency for SQCK is 300kHz and the minimum pulse width is 1.5s. Description of Functions 1. CPU Interface and Instructions * CPU interface This interface uses DATA, CLOK, and XLAT to set the modes. The interface timing chart is shown below.
750ns or more CLOK
DATA
D1
D2
D3
D0
D1
D2
D3 750ns or more
Data XLAT
Address
Registers 4 to E
Valid 300ns max
* Information on each address and the data is provided in Table 1-1. * The internal registers are initialized by a reset when XRST = 0; the initialization data is shown in Table 1-2. Note) When XLAT is low, EXCK and SQCK must be set high. -8-
CD2507 Command Table
Command D1 D3 D2 D1 -- -- -- -- -- -- -- -- 64 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 32 16 -- -- -- -- -- -- -- -- -- -- -- 8 -- -- -- -- -- -- -- -- -- 128 -- -- -- -- -- 256 -- 0 -- -- -- -- -- -- -- -- -- -- 4 -- -- -- -- -- -- -- -- --
0.36ms 0.18ms 0.09ms 0.05ms 11.6ms 5.8ms 2.9ms 1.45ms
Address Data 2 Data 3 D0 D3 D0 D1 -- -- -- 2 -- -- -- -- -- -- -- -- -- -- -- D3 D2 -- -- -- D2 D1 -- D0 -- D3 D1 D2 D0 -- -- -- 1 -- -- -- -- -- -- -- -- Data 4 D0 0 AS3 AS2 AS1 AS0
0.18ms 0.09ms 0.05ms 0.02ms
Data 1
Register name
D3 0 0 1 1 0 0 0 0 0 SL0
CPUSR
D2
4 1 0 -- 1 0 -- -- 0 -- -- -- -- -- -- -- -- -- -- -- 0 0 -- -- -- -- -- -- 1 0 Mute ATT 0 1 0 1 0 1 Don't Use CM3 CM2 CM1 CM0 SL1
CDROM
Auto sequence
0
1
5
Blind (A, E), Overflow (C)
0
1
Brake (B)
6 3276816384 8192 4096 2048 1024 512 --
KICK (D)
0
1
7
Auto sequence (N) track jump count setting
0
1
8
MODE specification
1
0
9 1 1 0 0 1 1
Function specification
1
0
DOUT DOUT WSEL MUTE ON/OFF DSPB 0 ON/OFF 0
A
Audio CTRL
1
0
-9-
Gain Gain Gain Gain MDP1 MDP0 MDS1 MDS0 DCLV TP CLVS Gain PWMmod TB
B
Serial bus CTRL
1
0
C
Servo coefficient setting
1
1
D
CLV CTRL
1
1
E
CLV mode
1
1
F
TEST mode
1
1
Values shown as "0" in the above table must be sent as "0". Table 1-1
CXD2507AQ
CXD2507 Reset Initialization Data 1 Data 2 Data 3 D0 D3 D0 D1 -- -- -- -- -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 -- -- -- -- -- -- -- -- -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- D3 D2 -- -- -- -- 0 -- -- 0 -- -- -- -- -- 0 -- -- -- -- D2 D1 -- -- -- 1 -- 0 -- -- -- D0 0 1 1 0 0 0 1 0 0 0 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 0 -- -- -- 0 0 0 -- -- -- -- -- -- -- -- -- D3 D1 D2 D0 -- -- -- 0 -- -- -- -- -- -- -- -- Data 4 D0 D3 D2 0 0 0 1 0 1 0 1 1 1 0 0 1 1 0 0 0 0 0 1 0 0 Don't Use Table 1-2 D1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1
Command D1 0 0 1 1 0 0 1 1 0 0 1 1
Address
Register name
D3
D2
4
Auto sequence
0
1
Blind (A, E), Overflow (C)
5
Brake (B)
0
1
6
KICK (D)
0
1
7
Auto sequencer (N) track jump count setting
0
1
8
MODE specification
1
0
9
Function specification
1
0
A
Audio CTRL
1
0
- 10 -
B
Serial bus CTRL
1
0
C
Servo coefficient setting
1
1
D
CLV CTRL
1
1
E
CLV mode
1
1
F
TEST mode
1
1
CXD2507AQ
CXD2507AQ
1-1. The meaning of the data for each address is explained below. $4X commands Command CANCEL FOCUS-ON 1 TRACK JUMP 10 TRACK JUMP 2N TRACK JUMP N TRACK MOVE AS3 0 0 1 1 1 1 AS2 0 1 0 0 1 1 AS1 0 1 0 1 0 1 RXF = 0 RXF = 1 AS0 0 1 RXF RXF RXF RXF FORWARD REVERSE
* When the FOCUS-ON command ($47) is canceled, $02 is sent and the auto sequence is interrupted. * When the TRACK JUMP/MOVE commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is interrupted. $5X commands Auto sequence timer setting Setting timers: A, E, C, B Command Blind (A, E), Over flow (C) Brake (B) D3 0.18ms 0.36ms D2 0.09ms 0.18ms D1 0.05ms 0.09ms D0 0.02ms 0.05ms
Ex.) D2 = D0 = 1, D3 = D1 = 0 (Initial reset) A = E = C = 0.11ms B = 0.23ms $6X commands Auto sequence timer setting Setting timer: D Command KICK (D) D3 11.6ms D2 5.8ms D1 2.9ms D0 1.45ms
Ex.) D3 = 0, D2 = D1 = D0 = 1 (Initial reset) D = 10.15ms $7X commands Auto sequence TRACK JUMP/MOVE count setting (N) Command Data 1 Data 2 Data 3 Data 4
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 Auto sequence track jump 15 14 13 12 11 10 2 2 2 2 2 2 count setting 29 28 27 26 25 24 23 22 21 20
This command is used to set N when a 2N TRACK JUMP and an N TRACK MOVE are executed for auto sequence. * The maximum track count is 65,535, but note that with 2N track jumps the maximum track jump count is determined by the mechanical limitations of the optical system. * The number of track jump is counted according to the signals input from CNIN pin. - 11 -
CXD2507AQ
$8X commands Command MODE specification D3 CDROM D2 DOUT MUTE D1 DOUT ON-OFF D0 WSEL
Command bit CDROM = 1 CDROM = 0
C2PO timing 1-3 1-3
Processing CDROM mode; average value interpolation and pre-value hold are not performed. Audio mode; average value interpolation and pre-value hold are performed. Processing
Command bit DOUT MUTE = 1 DOUT MUTE = 0 Command bit
Digital out output is muted. (DA output is not muted.) When no other mute conditions are set, digital out is not muted. Processing
DOUT ON-OFF = 1 Digital out is output from the DOUT pin. DOUT ON-OFF = 0 Digital out is not output from the DOUT pin. Command bit WSEL = 1 WSEL = 0 Sync protection window width 26 channel clock 6 channel clock Application Anti-rolling is enhanced. Sync window protection is enhanced.
In normal-speed playback, channel clock = 4.3218MHz. $9X commands Command Function specifications Command bit DSPB = 0 DSPB = 1 $AX commands Command Audio CTRL Data 1 D3 0 D2 0 D1 Mute D0 ATT Normal-speed playback Double-speed playback Data 1 D3 0 D2 DSPB ON-OFF D1 0 D0 0 D3 0 D2 0 Data 2 D1 0 D0 0
Processing
Command bit Mute = 0 Mute = 1
Meaning Mute off if other mute conditions are not set. Mute on. - 12 -
Command bit ATT = 0 ATT = 1
Meaning Attenuation off. -12dB
CXD2507AQ
$BX commands Command Serial bus CTRL D3 SL1 D2 SL0 D1 CPUSR D0 0
This command switches the method of interfacing with the CPU. With the CDL500 Series, the number of signal lines between the CPU and the DSP can be reduced in comparison with the CDL40 Series. Also, the error rate can be measured with the CPU. Command bits SL1 0 0 1 1 SL0 0 1 0 1 Processing Same interface mode as the CDL40 Series. SBSO is output from SQSO pin. In other words, subcodes P to W are read out from SQSO. Input the read clock to SQCK. SENS is output from SQSO pin. Each output signal is output from SQSO pin. Input the read clock to SQCK. (See to Timing Chart 1-4.) Processing XLON pin is high. XLON pin is low.
Command bits CPUSR = 1 CPUSR = 0 $CX commands Command Servo coefficient setting CLV CTRL ($DX) * CLVS mode gain setting: GCLVS Gain MDS1 0 0 0 0 1 1 Gain MDS0 0 0 1 1 0 0 Gain CLVS 0 1 0 1 0 1 GCLVS -12dB -6dB -6dB 0dB 0dB +6dB D3 Gain MDP1 D2 Gain MDP0
D1 Gain MDS1
D0 Gain MDS0 Gain CLVS
* CLVP mode gain setting: GMDP, GMDS Gain MDP1 0 0 1 Gain MDP0 0 1 0 GMDP -6dB 0dB +6dB - 13 - Gain MDS1 0 0 1 Gain MDS0 0 1 0 GMDS -6dB 0dB +6dB
CXD2507AQ
$DX commands Command CLV CTRL D3 DCLV PWM MD D2 TB D1 TP D0 CLVS Gain See the $CX command.
Command bit DCLV PWM MD = 1 DCLV PWM MD = 0
Explanation (See Timing Chart 1-5.) CLV PWM mode specified. Both MDS and MDP are used. CLV PWM mode specified. Ternary MDP values are output.
Command bit TB = 0 TB = 1 TP = 0 TP = 1
Explanation Bottom hold in CLVS mode at cycle of RFCK/32 Bottom hold in CLVS mode at cycle of RFCK/16 Peak hold in CLVS mode at cycle of RFCK/4 Peak hold in CLVS mode at cycle of RFCK/2
$EX commands Command CLV mode D3 CM3 D2 CM2 D1 CM1 D0 CM0
CM3 0 1 1 1 1 0 STOP KICK BRAKE CLVS CLVP CLVA
CM2 0 0 0 1 1 1
CM1 0 0 1 1 1 1
CM0 0 0 0 0 1 0
Mode STOP KICK BRAKE CLVS CLVP CLVA
Explanation See Timing Chart 1-6. See Timing Chart 1-9. See Timing Chart 1-8.
: Spindle motor stop mode : Spindle motor forward rotation mode : Spindle motor reverse rotation mode : Rough servo mode. When RF-PLL circuit lock is disengaged, this mode is used to pull the disc rotations within the RF-PLL capture range. : PLL servo mode. : Automatic CLVS/CLVP switching mode. This mode is normally used during playback.
- 14 -
Timing Chart 1-3
LRCK
WDCK
CDROM = 0 Rch 16bit C1 Pointer Lch 16bit C2 Pointer If C2 Pointer = 1, data is NG
- 15 -
C2 Pointer for lower 8bits C2 Pointer for upper 8bits Rch C2 Pointer
C2P0
CDROM = 1 C2 Pointer for lower 8bits
C2P0
C2 Pointer for upper 8bits
Lch C2 Pointer
CXD2507AQ
Timing Chart 1-4
$BC latch
Set SQCK and EXCK high during this interval. 750ns or more (1500ns or more in low power consumption mode)
XLAT
Internal signal latch
SQCK
SQSO
SPOD WFCK SCOR GFS GTOP EMPH FOK LOCK RFCK XRAOF C1F1 C1F2 C2F1
SPOA
SPOB
SPOC
C2F2
- 16 - C1 correction status No Error Single error correction Irretrievable error C2F1 C2F2 0 1 1 0 0 1 C2 correction status No Error Single error correction Irretrievable error 0 0 1
CXD2507AQ
C1F1 C1F2
0
1
1
CXD2507AQ
Timing Chart 1-5
DCLV PWM MD = 0 MDS Z n * 236(ns) n = 0 to 31 Acceleration MDP Z 132kHz 7.6s Deceleration
DCLV PWM MD = 1
MDS
Acceleration MDP
Deceleration
7.6s
n * 236(ns) n = 0 to 31
Timing Chart 1-6
DCLV PWM MD=0 STOP Z
MDS
MDP
Z
MON
L
DCLV PWM MD=1 STOP
MDS
MDP
L
MON
L
- 17 -
CXD2507AQ
Timing Chart 1-7
DCLV PWM MD=1 STOP
MDS
MDP
L
MON
L
DCLV PWM MD = 0 KICK MDS Z
MDP
H Z 7.6s
MON
H
DCLV PWM MD = 1 KICK
MDS
H
MDP
H L
MON
H
- 18 -
CXD2507AQ
Timing Chart 1-8
DCLV PWM MD = 0 BRAKE MDS Z
MDP
L
Z
MON
H
DCLV PWM MD = 1
MDS
MDP
MON
H
- 19 -
CXD2507AQ
1-2. Description of SENS Output The following signals are output from SENS, depending on the microcomputer serial register value (latching not required). Microcomputer serial register SENS value (latching not required) output $0X, 1X, 2X, 3X $4X $5X $6X $AX $EX $7X, 8X, 9X, BX, CX, DX, FX SEIN Meaning SEIN, a signal input to the CXD2507 from the SSP, is output.
XBUSY Low while the auto sequencer is in operation, high when operation terminates. FOK SEIN GFS OV64 Low Outputs the signal input to the FOK pin. Normally, FOK (from RF) is input. High for "focus OK". SEIN, a signal input to CXD2507 from the SSP, is output. High when the played back frame sync is obtained with the correct timing. Low when the EFM signal, after passing through the sync detection filter, is lengthened by 64 channel clock pulses or more. The SENS pin is fixed low.
Note that the SENS output can be read from the SQSO pin when SL1=1 and SL0=0. (See the $BX commands.) 2. Subcode Interface This section explains the subcode interface. There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read from SBSO by inputting EXCK to the CXD2507. Sub Q can be read out after the CRC check of the 80 bits of information in the subcode frame. This accomplished, after checking SCOR and CRCF, by inputting 80 clock pulses to SQCK and reading data from SQSO pin. 2-1. P to W Subcode Read Data can be read out by inputting EXCK immediately after WFCK falls. (See Fig. 2-1.) Also, SBSO can be read out from SQSO pin when SL1 = 0 and SL0 = 1. (See the $BX commands.) 2-2. 80-bit Sub Q Read Fig. 2-2 shows the peripheral block of the 80-bit Sub Q register. * First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit. * 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, the 80 bits are loaded into the parallel/serial register. When SQSO goes high 400s or more later (monostable multivibrator time constant) after the subcode is read out, the CPU determines that new data (which passed the CRC check) has been loaded. * In the CXD2507, when 80-bit data is loaded, the order of the MSB and LSB is inverted for each byte. As a result, although the sequence of bytes is the same, the bits within the bytes are now ordered LSB first. * Once the fact that the 80-bit data has been loaded is confirmed, SQCK is input so that the data can be read. In the CXD2507, the SQCK input is detected, and the retriggerable monostable multivibrator for low is reset. * The retriggerable monostable multivibrator has a time constant from 270 to 400s. When the duration of SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the S/P register is not loaded into the P/S register. * While the monostable multivibrator is being reset, data can not be loaded in the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than the monostable multivibrator time constant, the register will not be rewritten by CRCOK and others. * Fig. 2-3 shows Timing Chart. * Although a clock is input from SQCK pin to actually perform these operations, the high and low intervals for this clock should be between 750ns and 120s. - 20 -
CXD2507AQ
Timing Chart 2-1
Interrel PLL clock 4.3218 MHz
WFCK
SCOR
EXCK 400ns max SBSO S0-S1 Q R
WFCK
SCOR
EXCK
SBSO
S0-S1 Q R S T U V W S0-S1
P1
QRST
UVW
P1
P2
P3
Same
Same Subcode P.Q.R.S.T.U.V.W Read Timing
- 21 -
Block Diagram 2-2
(AFRAM)
(ASEC)
(AMIN)
ADDRS CTRL
SUBQ
SIN 80bit S/P Register
ABCDEFGH
8 8 8 8 8 8 Order Inversion 8 8
8
HGFEDCBA 80bit S/P Register
SO
LD
LD
LD
LD
LD
SUBQ
CRCC
Mono/Multi
LD
SHIFT
LD
LD
SI
- 22 -
SHIFT
SQCK
CRCF SQSO Mix CXD2507AQ
Timing Chart 2-3
1 91 95 96 97 98 1 3 2 92 93 94
2 3
WFCK Order Inversion Determined by mode L 80 Clock CRCF2
SCOR
SQSO
CRCF1
SQCK Register load forbidder
- 23 -
750ns to 120s 270 to 400s for SQCK = high ADR0 ADR1 ADR2 ADR3 CTL0 300ns max
Mono/multi (Interral)
SQCK
SQSO
CRCF
CTL1
CTL2
CTL3
CXD2507AQ
CXD2507AQ
3. Description of Other Functions 3-1. Channel Clock Regeneration by Digital PLL Circuit * The channel clock is necessary for demodulating the EFM signal regenerated by the optical system. Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is channel clock, is required. In an actual player, the fluctuation in the spindle rotation alters the width of the EFM signal pulses, making a PLL necessary for regenerating channel clock. The block diagram of this PLL is shown in Fig. 3-1. The CXD2507 has a built-in two-stage PLL as shown in the diagram. * The first-stage PLL generates a high-frequency clock needed by the second-stage digital PLL. * The second-stage PLL is a digital PLL that regenerates actual channel clock, and has a 250kHz (normal state) or more capture range. Block Diagram 3-1
OSC X'tal 1/M Phase comparator PCO
XTSL
1/N FILI
FILO
CLTV VCO
VDD
Digital PLL RFPLL
CXD2507
- 24 -
CXD2507AQ
3-2. Frame Sync Protection * In a CD player operating at normal speed, a frame sync is recorded approximately every 136s (7.35kHz). This signal is used as a reference to know which data is the data within a frame. Conversely, if the frame sync can not be recognized, the data is processed as error data because it can not be recognized what the data is. As a result, recognizing the frame sync properly is extremely important for improving playability. * There are two window widths: one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the backward protection counter is fixed to 3. In other words, when the frame sync is being played back normally and then can not be detected due to scratches, a maximum of 13 frames are inserted. If frame sync can not be detected for 13 frames or more, the window is released and the frame sync is resynchronized. In addition, immediately after the window is released and resynchronization is executed, if a proper frame sync can not be detected within 3 frames, the window is released immediately. 3-3. Error Correction * In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed-Solomon codes with a minimum distance 5. * The CXD2507 SEC strategy provides excellent playability through powerful frame sync protection and C1 and C2 error corrections. * The correction status can be monitored outside the LSI. See Table 3-2. * When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held for that data, or an average value interpolation was made.
MNT3 0 0 0 1 1 1
MNT1 0 0 1 0 0 1
MNT0 0 1 1 0 1 0
Description No C1 errors One C1 errors corrected C1 correction impossible No C2 errors One C2 errors corrected C2 correction impossible
Table 3-2
- 25 -
CXD2507AQ
Timing Chart 3-3
Normal-speed PB 400 to 500ns
RFCK
t = Dependent on error condition MNT3 C1 correction C2 correction
MNT1
MNT0
Strobe
Strobe
C4M
MNT0, 1, 3
Valid Invalid
Valid
3-4. DA Interface * The CXD2507 DA interface is as described below. This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel.
- 26 -
Timing Chart 3-4
48bit slot Normal-Speed Playback
LRCK (44.1k) 5 6 7 8 9 10 11 12 24
1
2
3
4
BCK (2.12M)
WDCK
PCMD
R0
Lch MSB (15)
L14
L13
L12
L11
L10
L9
L8
L7
L6
L5
L4
L3
L2
L1
L0
RMSB
- 27 -
24 Rch MSB L0
48bit slot Double-Speed Playback
LRCK (88.2k)
12
BCK (4.23M)
WDCK
PCMD
Lch MSB (15)
R0
CXD2507AQ
CXD2507AQ
3-5. Digital Out There are three digital out formats: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD2507 supports type 2 form 1. Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bit 0 to 3) of channel status.
Digital Out C bit 0 0 ID0 16 0 1 2 3 4 0 5 0 6 0 7 0 8 1 9 0 10 0 11 0 12 0 13 0 14 0 15 0
From sub Q ID1 COPY Emph 0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
32
48
0
176 bit0 to 3 - Sub Q control bits that matched twice with CRCOK
Table 3-5 3-6. Servo Auto Sequencer This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1 track jump, 2N track jumps, and N track move are executed automatically. SSP (servo signal processor LSI) is used in an exclusive manner during the auto sequence execution (when XBUSY = low), so that commands from the CPU are not transferred to the SSP, but they can be sent to the CXD2507. Connect the CPU, RF and SSP as shown in Fig. 3-6. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100s after that point. This is designed to prevent the transfer of erroneous data to the SSP when XBUSY changes from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low).
- 28 -
CXD2507AQ
(a) Auto Focus ($47) Focus search up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Figure. 3-7. The auto focus is executed after focus search up, and the pickup should be lowered beforehand (focus search down). In addition, blind E of register 5 is used to eliminate FZC chattering. In other words, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E. Connection diagram for using auto sequencer (example)
RF FOK FOK
DATA CXD2507 C. out SSP SENS DATA CLK XLT CNIN SENS SEIN DATO CLKO XLTO CLOK XLAT Micro-computer
Fig. 3-6.
Auto focus
Focus search up
FOK=H YES
NO
(Checks whether FZC has stayed high longer than the period of time E set in register 5) FZC = H YES NO
FZC = L YES Focus servo ON
NO
END
Fig. 3-7-(a). Auto Focus Flow Chart - 29 -
CXD2507AQ
$47latch
XLT
FOK
SEIN (FZC)
BUSY
Blind E Command for SSP $03 $08
Fig. 3-7-(b). Auto Focus Timing Chart (b) Track Jump 1, 10, and 2N-track jumps are performed respectively. Always use this when focus, tracking, and the sled servo are on. Note that tracking gain up and braking on ($17) should be sent beforehand because they are not performed. * 1-track jump When $48 ($49 for REV) is received from the CPU, an FWD (REV) 1-track jump is performed in accordance with Fig. 3-8. Set blind A and brake B with register 5. * 10-track jump When $4A ($4B for REV) is received from the CPU, an FWD (REV) 10-track jump is performed in accordance with Fig. 3-9. The principal difference between the 10-track jump and the 1-track jump is whether to kick the sled or not. In addition, after kicking the actuator, 5 tracks have been counted through CNIN, and the brake is applied to the actuator. Then, the actuator speed is found to have slowed up enough (determined by the CNIN cycle becoming longer than the overflow C set in register 5), and the tracking and sled servos are turned on. * 2N-track jump When $4C ($4D for REV) is received from the CPU, an FWD (REV) 2N-track jump is performed in accordance with Fig. 3-10. The track jump count "N" is set in register 7. Although N can be set to 216 tracks, note that the setting is actually limited by the actuator. CNIN is used for counting the number of jumps. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set in register 6. * N-track move When $4E ($4F for REV) is received from the CPU, an FWD (REV) N-track move is performed in accordance with Fig. 3-11. N can be set to a maximum of 216 tracks. CNIN is used for counting the number of jumps. This N-track move uses a method in which only the sled is moved, and is suited for moves over thousands of tracks.
- 30 -
CXD2507AQ
Track
Track kick sled servo WAIT (Blind A)
(REV kick for REV jump)
CNIN = NO YES Track REV kick WAIT (Brake B) Track, sled servo ON (FWD kick for REV jump)
END
Fig. 3-8-(a). 1-Track Jump Flow Chart
$48 (REV = $49) latch
XLT
CNIN
BUSY
Blind A Command for SSP $28 ($2C) $2C ($28)
Brake B $25
Fig. 3-8-(b). 1-Track Jump Timing Chart
- 31 -
CXD2507AQ
10 Track
Track, sled FWD kick WAIT (Blind A)
(Counts CNIN x 5) CNIN = 5 ? NO YES Track, REV kick
(Checks whether the CNIN cycle is longer than overflow C) C = Overflow ? NO YES Track, sled servo ON
END
Fig. 3-9-(a). 10-Track Jump Flow Chart
$4A (REV = $4B) latch
XLT
CNIN
BUSY
Blind A Command for SSP
CNIN 5count
Overflow C
$2A ($2F)
$2E ($2B)
$25
Fig. 3-9-(b). 10-Track Jump Timing Chart
- 32 -
CXD2507AQ
2N Track
Track, sled FWD kick WAIT (Blind A)
CNIN = N NO YES Track REV kick
C = Overflow NO YES Track servo ON
WAIT (Kick D)
Sled servo ON
END
Fig. 3-10-(a). 2N-Track Jump Flow Chart
$4C (REV = $4D) latch
XLT
CNIN
BUSY
Blind A Command for SSP $2A ($2F)
CNIN N count $2E ($2B)
Overflow $26 ($27)
Kick D $25
Fig. 3-10-(b). 2N-Track Jump Timing Chart - 33 -
CXD2507AQ
N Track move
Track servo OFF Sled FWD kick WAIT (Blind A)
CNIN = N NO YES Track, sled servo ON
END END
Fig. 3-11-(a). N-Track Move Flow Chart
$4E (REV = $4F) latch
XLT
CNIN
BUSY
Blind A Command for SSP $22 ($23)
CNIN N count $25
Fig. 3-11-(b). N-Track Move Timing Chart
- 34 -
CXD2507AQ
3-7. Digital CLV Fig. 3-12 shows the Block Diagram. Digital CLV makes PWM output in CLVS and CLVP with the MDS error and MDP error signal sampling frequency increased to 130kHz during normal speed operation. In addition, the digital spindle servo can set the gain.
Digital CLV CLVS U/D MDS Error MDP Error
Gain
0, -6dB
Measure
Measure
CLV P/S
2/1 MUX
Over Sampling Filter-1
GS (Gain) 1/2 Mux CLV S CLV P
GP (Gain)
Over Sampling Filter-2
CLV * P/S
Noise Shape
KICK, BRAKE STOP
Modulation
Mode Select
MDP
DCLVMD
MDS
Fig. 3-12. Block Diagram
- 35 -
CXD2507AQ
3-8. Asymmetry Compensation Fig. 3-13 shows the Block Diagram and Circuit Example.
ASYE
ASYO R1 RF R1
R2
R1 ASYI
R1
BIAS R1 2 = R2 5
Fig. 3-13. Example of Asymmetry Correction Application Circuit
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 36 -
CXD2507AQ
Application Circuit
to CPU
SCOR
MUTE
SQCK SUBQ QFS CLK
SENS
GND LDON
SSP
64 63 62 61 60 59 58 57 56 55 54 53 52
DATO
XLTO
RF
1 FOK 2 MON
SPOD
SPOC
SPOB
SPOA
XLON
CLKO
CLOK
DRIVER
3 MDP 4 MDS 5 LOCK
GND
6 TEST 7 FILO 8 FILI 9 PCO
XLAT
CNIN
SEIN
VDD
DATA 51 XRST 50 SENS 49 MUTE 48 SQCK 47 SQSO 46 EXCK 45 SBSO 44 SCOR 43 Vss 42 WFCK 41 EMPH 40 DOUT 39 C4M 38 FSTT 37 XTSL 36 XTAO 35 XTAI 34 GND GND GND OPEN
GND GND
10 Vss 11 AVss 12 CLTV 13 AVDD
RF
14 RF 15 BIAS 16 ASYI 17 ASYO 18 ASYE 19 WDCK
FOK LDON
XLT DATA
XRST
GND
VDD
PCMD
GTOP
XUGF
C2PO
XROF
XPCK
LRCK
BCK
GFS
VDD
RFCK
MNT3
MNT1
GND
GND
MNT0 33
MNT0 MNT1 MNT2 MNT3 GND GND
20 21 22 23 24 25 26 27 28 29 30 31 32
GTOP
XUGF
XPCK
RFCK
GND
GFS
WDCK
PCMD BCK
to D/A converter
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
C2PO
GND
EMPH MUTE
LRCK
- 37 -
C2PO
XROF
to error rate counter
GND
CXD2507AQ
Package Outline
Unit: mm
64PIN QFP(PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1
51 33
+ 0.1 0.15 - 0.05 0.15
52
32
17.9 0.4
+ 0.4 14.0 - 0.1
64
20
+ 0.2 0.1 - 0.05
1 1.0 + 0.15 0.4 - 0.1
19 + 0.35 2.75 - 0.15 0.12 M 0.8 0.2 EPOXY RESIN SOLDER/PALLADIUM PLATING COPPER /42 ALLOY 1.5g
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
64PIN QFP (PLASTIC)
24.98 0.4 20.20 MAX 51 33 0.15 0.05 0.15
52
32
14.20 MAX
19.00 0.4
64
20
+ 0.1 0.1 - 0.05
1.0
0.55 MAX
2.1 MAX 0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L121 QFP064-P-1420-AX LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING 42 ALLOY 1.5g
- 38 -
1.3 0.2
1
19
(16.4)
16.3

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