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Integrated Circuit Systems, Inc.
ICS91718
Low EMI, Spread Modulating, Clock Generator
Features: * ICS91718 is a Spread Spectrum Clock targeted for Mobile PC and LCD panel applications. Generates an EMI optimized clock signal (EMI peak reduction of 7-14 dB on 3rd-19th harmonics) through use of Spread Spectrum techniques. * ICS91718 operates with input frequencies at 14.318 - 80 MHz. * Spread modulation frequency range is 20kHz to 40kHz. * Spread percentage/type programming through I2C. Specifications: * Supply Voltages: VDD = 3.3V 0.3V * Cyc to Cyc jitter: <150ps * Output duty cycle 45/55% * Guarantees +85C operational condition * 8-pin SOIC (150 mil) package
Pin Configuration
CLKIN VDD GND **CLKOUT/FS_IN0
1 2 3 4 8 7 6 5
PD#* SCLK SDATA REF_OUT/FS_IN1**
8-pin SOIC & TSSOP
Notes: * Internal pull-up resistor ** Internal pull-down resistor
Input Select Functionality
FS_IN1 FS_IN0
0 0 1 1 0 1 0 1
MHz
14.318 in 48.00 out 14.318 in 66.66 out 48.00 in/out 66.66 in/out 48.00 in/out 66.66 in/out
SPREAD %
-1.0% down sprd -1.0% down sprd -1.0% down sprd +/-1.0% center sprd
Block Diagram
REFOUT CLKIN PLL1 Spread Spectrum Spectrum CLKOUT CLKOUT
PD# FS_IN0:1 SDATA SD SCLK
Control Logic Config. Reg.
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ICS91718
Pin Descriptions
PIN # 1 2 3 4 5 6 7 8 PIN NAME CLKIN VDD GND **CLKOUT/FS_IN0 REF_OUT/FS_IN1** SDATA SCLK PD#* PIN DESCRIPTION TYPE IN Input clock PWR Power supply, nominal 3.3V PWR Ground pin. CLKOUT modulated clock output I/O FS_IN0 latched input, selects modulation percentage/type REF_OUT, unmodulated reference clock output I/O FS_IN1 latched input, selects modulation percentage/type I/O Data pin for I2C circuitry 5V tolerant IN Clock pin of I2C circuitry 5V tolerant Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the IN crystal are stopped. The latency of the power down will not be greater than 1.8ms.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor
0500D--07/15/04
2
ICS91718
Table 1: Frequency Configuration Table (See I2C Byte 0)
FS4 FS3 FS2 FS1 FS0 Sprd Type Sprd % 0 0 0 0 0 0.80 0 0 0 0 1 1.00 DOWN 0 0 0 1 0 1.25 SPREAD 0 0 0 1 1 1.50 (-) 0 0 1 0 0 1.75 0 0 1 0 1 2.00 0 0 1 1 0 2.50 0 0 1 1 1 0.60 CENTER 0 1 0 0 0 1.00 SPREAD 0 1 0 0 1 1.25 (+/-) 0 1 0 1 0 1.50 0 1 0 1 1 2.00 0 1 1 0 0 1.25 DOWN 0 1 1 0 1 1.00 SPREAD 0 1 1 1 0 1.50 (-) 0 1 1 1 1 2.00 1 0 0 0 0 0.80 1 0 0 0 1 1.00 1 0 0 1 0 1.25 DOWN 1 0 0 1 1 1.50 SPREAD 1 0 1 0 0 1.75 (-) 1 0 1 0 1 2.00 1 0 1 1 0 2.50 1 0 1 1 1 3.00 1 1 0 0 0 0.30 1 1 0 0 1 0.40 1 1 0 1 0 0.50 CENTER 1 1 0 1 1 0.60 SPREAD 1 1 1 0 0 0.80 (+/-) 1 1 1 0 1 1.00 1 1 1 1 0 1.25 1 1 1 1 1 1.50
14in/48out
14in/66out
48in/48out 66in/66out
For 14.318 in 48.008 out default is... ..00001 For 14.318 in 66.66 out default is... ... 01101 For 48/48 and 66/66 default is... .10001 ... ...
0500D--07/15/04
3
ICS91718
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit * * * * * * * *
How to Write:
Controller (Host) Start Bit Address D4(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Byte 7 ACK Stop Bit ICS (Slave/Receiver)
How to Read:
* * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D5 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 7 Controller (host) will need to acknowledge each byte * Controller (host) will send a stop bit
How to Read:
Controller (Host) Start Bit Address D5(H) ICS (Slave/Receiver)
ACK
ACK
ACK Byte Count Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Byte 7 Stop Bit
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. 2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) 3. The input is operating at 3.3V logic levels. 4. The data byte format is 8 bit bytes. 5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. 6. At power-on, all registers are set to a default condition, as shown.
0500D--07/15/04
4
ICS91718
0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin #
-
Name
N/A N/A N/A N/A N/A N/A N/A HW/SW Control
Control Function
FS0 FS1 FS2 FS3 FS4 PD# Tri_Sate Spread Enable Spread Spectrum Control FS 2:4 Hard/Software Select
TYPE
BYTE
Affected Pin
Bit Control 0 1
PWD
RW RW RW See ROM TABLE RW RW RW Hi-Z LOW RW OFF ON RW HW SW
1 0 0 0 0 1 1 0
1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BYTE
Pin #
5 5
Name
REF_OUT REF_OUT FS_IN1 Readback FS_IN0 Readback CLK_OUT CLK_OUT Reserved Reserved
Control Function
REF_OUT ENABLE Slew Rate REF-OUT FS_IN1 Readback FS_IN0 Readback Slew Rate CLK-OUT CLK_OUT_Enable Reserved Reserved
TYPE
BYTE
Affected Pin
Bit Control 0 1
PWD
4 4
RW RW RW RW RW RW R R
TYPE
Disable Enable Nominal Fast Nominal Fast Disable Enable -
1 1 1 1 1 1 1 1
Affected Pin Pin #
x x x x x x x x
Bit Control 0
Disable Disable Disable Disable Disable Disable Disable
2
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Control Function
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
1
Enable Enable Enable Enable Enable Enable Enable
PWD
RW RW RW RW RW RW RW
1 1 1 1 1 1 1 1
0500D--07/15/04
5
ICS91718
3
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BYTE
Pin #
X
Name
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Control Function
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
TYPE
BYTE
Affected Pin
Bit Control 0 1
PWD
X X X x X X
X
RW Disable Enable RW Disable Enable Not RW Freerun Freerun Not RW Freerun Freerun Not RW Freerun Freerun RW Disable Enable RW Disable Enable RW Disable Enable
TYPE
1 1 1 1 1 1 1 1
Affected Pin Pin #
X X X X X X X X
Bit Control 0
Disable Disable Disable Disable Disable Disable Disable Disable
4
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BYTE
Name
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Control Function
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
1
Enable Enable Enable Enable Enable Enable Enable Enable
PWD
RW RW RW RW RW RW RW RW
TYPE
1 1 1 1 1 1 1 1
Affected Pin Pin #
X X X X X X X X
Bit Control 0
Disable Disable Disable Disable
5
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Control Function
RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
1
Enable Enable Enable Enable
PWD
RW RW RW RW
1 1 1 1 1 1 1 1
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6
ICS91718
6
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BYTE
Pin #
X X X X X X X X
Name
Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0
Control Function
(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
TYPE
BYTE
Affected Pin
Bit Control 0
-
1
-
PWD
R R R R R R R R
TYPE
1 1 1 1 1 1 1 1
Affected Pin Pin #
X X X X X X X X
Bit Control 0
-
7
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BYTE
Name
DEVICE ID7 DEVICE ID6 DEVICE ID5 DEVICE ID4 DEVICE ID3 DEVICE ID2 DEVICE ID1 DEVICE ID0
Control Function
(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
1
-
PWD
R R R R R R R R
TYPE
0 0 0 0 0 0 0 1
Affected Pin Pin #
X X X X X X X X
Bit Control 0
-
8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name
Byte Count7 Byte Count6 Byte Count5 Byte Count4 Byte Count3 Byte Count2 Byte Count1 Byte Count0
Control Function
(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
1
-
PWD
R R R R R R R R
0 0 0 0 0 1 1 1
0500D--07/15/04
7
ICS91718
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Voltage on any pin with respect to GND . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . Operating Temperature . . . . . . . . . . . . . . . . . . Ambient Operating Temperature under Bias . Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 3.3 V -0.5 to +7.0 V -55C to +125C 0C to +85C -55 to +125 C 0.5 W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 85C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Supply Current Powerdown Current Pin Inductance Pin Capacitance1 Transition time1 Settling time1 Clk Stabilization1 Delay 1
1
SYMBOL CONDITIONS V IH V IL V IN = VDD IIH V IN = 0 V; Inputs with no pull-up resistors I IL1 f IN = 14.318MHz IDD f IN = 66.66MHz IDD3.3PD Lpin CIN Logic Inputs COUT Output pin capacitance Ttrans To 1st crossing of target frequency Ts From 1st crossing to 1% target frequency TSTAB From VDD = 3.3 V to 1% target frequency t PZH,t PZL Output enable delay (all outputs)
MIN TYP 2 V SS - 0.3 -5 -5 27 42 3
MAX UNITS VDD + 0.3 V 0.8 V 5 A A 35 mA 50 mA mA 5 7 nH 5 pF 6 pF 3 ms 3 ms 3 10 ms ns
1 1
Guaranteed by design, not 100% tested in production.
AC Electrical Characteristics
TA = 0 - 70C; Supply Voltage V DD = 3.3 V 0.3V PARAMETER FIN f OUT tR tF IOD tID tJCYC
0500D--07/15/04
DESCRIPTION Input Frequency Output Frequency Output Rise Time Output Fall Time Output Duty Cycle Input Duty Cycle Jitter, Cycle-to-Cycle
TEST CONDITION Input Clock Spread Off 15 pF load, 0.8V - 2.4V 15 pF load, 2.4 - 0.8V 15 pf load
MIN 14.318 14.318 0.5 0.5 45 45
TYP
MAX 80 80 1 1 55 55 250
UNITS MHz MHz ns ns % % ps
8
ICS91718
Electrical Characteristics - CLOCK_OUT
TA = 0 - 85C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Current Source Output Impedance Output High Voltage Output Low Voltage Rise Time Fall Time Duty Cycle Jitter, Cycle to cycle
1 2
SYMBOL Zo1 VOH3 VOL3 tr3 tf3 dt3 tjcyc-cyc 1
CONDITIONS V O = Vx IOH = -1 mA IOL = 1 mA VOL = 0.41V, VOH = 0.86V VOH = 0.86V VOL = 0.41V VT = 50% VT = 50%
MIN 3000 2.4 0.5 0.5 45
TYP
MAX UNITS V 0.4 1 1 ns ns % ps
51
55 250
Guaranteed by design, not 100% tested in production. IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - REF
TA = 0 - 85C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Accumulated Jitter Jitter
1
SYMBOL FO1 RDSP11 V OH1 V OL1 I OH1 I OL1 tr11 tf11 dt11 t jlongterm t jcyc-cyc 1 I OH = -1 mA
CONDITIONS V O = VDD*(0.5) I OL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V V OL @MIN = 1.95 V, VOL @MAX = 0.4 V V OL = 0.4 V, V OH = 2.4 V V OH = 2.4 V, VOL = 0.4 V V T = 1.5 V V T = 1.5 V 10us. V T = 1.5 V
MIN 20 2.4 -29 29 0.5 0.5 45
TYP
MAX UNITS MHz 60 0.4 -23 27 1 1 55 2 500 V V mA mA ns ns % ns ps
Guaranteed by design, not 100% tested in production.
0500D--07/15/04
9
ICS91718
N
C
L
INDEX AREA
E
H
12 D
h x 45 A A1 SEATING PLANE .10 (.004)
150 mil (Narrow Body) SOIC In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A 1.35 1.75 .0532 .0688 A1 0.10 0.25 .0040 .0098 B 0.33 0.51 .013 .020 C 0.19 0.25 .0075 .0098 D SEE VARIATIONS SEE VARIATIONS E 3.80 4.00 .1497 .1574 e 0.050 BASIC 1.27 BASIC H 5.80 6.20 .2284 .2440 h 0.25 0.50 .010 .020 L 0.40 1.27 .016 .050 N SEE VARIATIONS SEE VARIATIONS a 0 8 0 8 VARIATIONS N 8 D mm. MIN 4.80 MAX 5.00 D (inch) MIN MAX .1890 .1968
e
B
150mil Body, .50mil pitch
Reference Doc.: JEDEC Publication 95, MS-012 10-0030
Ordering Information
ICS91718yMLF-T
Example:
ICS XXXX y M LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type M = SOIC Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0500D--07/15/04
10
ICS91718
N
c
4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil)
L
(25.6 mil) In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0 8 -.004
SYMBOL A A1 A2 b c D E E1 e L N a aaa VARIATIONS N
INDEX AREA
E1
E
12 D
In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 SEE VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 SEE VARIATIONS 0 8 -0.10
A2 A1
A
D mm. MIN 2.90 MAX 3.10 MIN .114
D (inch) MAX .122
-Ce
b SEATING PLANE
8
Reference Doc.: JEDEC Publication 95, MO-153
aaa C
10-0035
Ordering Information
ICS91718yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0500D--07/15/04
11

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