View ICS9219_26350.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS9219
Direct RambusTM Clock Generator Lite
General Description
ICS9219 is a High-speed clock generator providing 400 or 533 MHz differential clock source for direct Rambus memory system. ICS9219 takes a crystal as an input reference source, and produces the differential output clock required for the Rambus channel. ICS9219 provides a solution for a broad range of Direct Rambus memory applications. ICS9219 can be used in single or dual Rambus channels. An additional LVCMOS output, which provides a reference clock at the crystal frequency for the other system blocks is also included.
Features
* * * * * * Compatible with all Direct RambusTM based ICs Provides differential clock source for direct Rambus memory system with 1GHz data transfer rate capability Cycle to Cycle jitter is less than 100ps 3.3V + 4% supply LVCMOS REF clock @ crystal frequency Output edge rate control to minimize EMI
Block Diagram
FS0 X1 X2
Pin Configuration
VDDT GND X2 X1 VDD REF GND FS1* 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FS0* VDD GND BUSCLKT BUSCLKC GND VDD FS2*
PLL
REF
VDDT FS1 FS2
Control Logic
16-Pin 173 mil TSSOP * Pins have 60K internal pull-up to VDD
Table 1. PLL Multiplier Selection and Output Frequency FS0 0 1 Mult 16 21.332 BUSCLK1 400.00 533.30
Notes: 1 Output frequencies are based on 25MHz XTAL Input multipliers are also applicable to spread spectrum modulated input clocks. 2 Default muliplier value at power up.
0931B--10/25/04
ICS9219
Xtal OSC
BUSCLKT BUSCLKC
ICS9219
Pin Descriptions
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 PIN NAME VDDT GND X2 X1 VDD REF GND FS1* FS2* VDD GND BUSCLKC BUSCLKT PIN TYPE PWR/IN PWR OUT IN PWR OUT PWR IN IN PWR PWR OUT OUT DESCRIPTION Power supply, nominal 3.3V/Test mode Ground pin. Crystal output (14MHz to 25MHz) Crystal input (14MHz to 25MHz) Power supply, nominal 3.3V Reference of Input Ground pin. Frequency select pin. Real-time frequency select pin with internal 120Kohm pull-up resistor (check SMBus HW/SW setting for priority). Power supply, nominal 3.3V Ground pin. Output clock connected to the Rambus channel. This output is the complement of BUSCLK. Output clock connected to the Rambus channel. This output is the true component of BUSCLK. Ground pin. Power supply, nominal 3.3V Frequency select pin.
14 GND PWR 15 VDD PWR 16 FS0* IN * Pins have 60K internal pull-up to VDD
Table 2: Function Table FS(2:0) INPUT VDDT MULT FS2 FS1 FS0 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 0 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 X X X X X X 16 21.33 16 21.33 -
MODE NORMAL NORMAL NORMAL NORMAL TEST TEST TEST TEST TEST TEST
BUSCLKT INPUT x MULT INPUT x MULT INPUT x MULT INPUT x MULT BUSCLKT/2 BUSCLKT/4 X1 X1 X1/2 X1/4
BUSCLKC BUSCLKC BUSCLKC BUSCLKC BUSCLKC BUSCLKC/2 BUSCLKC/4 X1(INVERT) X1(INVERT) X1(INVERT)/2 X1(INVERT)/4
REF INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT
0931B--10/25/04
2
ICS9219
Absolute Maximum Ratings over operating free-air temperature
Supply voltage range, VDD or VDDT (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4 V Input voltage range,VI, at any input terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to V DD + 0.5 V Output voltage range, VO, at any output terminal (BUSCLKT/C) . . . . . . . . . . . . . . . . . . . . -0.5 V to V DD + 0.5 V ESD rating (MIL-STD 883C, Method 3015) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 2 kV, Machine Model >200 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the GND terminals.
Recommended Operating Conditions
Supply voltage, VDD Low-level input voltage, VIL High-level input voltage, VIH Internal pullup resistance Input frequency at crystal input Low-level output current, IOL High-level output current, IOH Input capacitance (CMOS), CL Operating free-air temperature FS (2:0) X1, X2 0 MIN 3 FS (2:0) FS (2:0) FS (2:0) 0.65 x VDD 90 14.0625 BUSCLKT/C REF BUSCLKT/C REF NOM 3.3 MAX 3.6 0.35 x VDD 150 26 16 10 -16 -10 15 15 85 UNIT V V k MHz mA mA pF C
25
Timing Requirements
Clock cycle time, t(CYCLE) Input slew rate, SR State transition latency (VDDX or S0 to CLKs - normal mode), t(STL) MIN 2.5 0.5 MAX 3.7 4 3 UNIT ns V/ns ms
Crystal Specifications
Frequency Frequency tolerance (at 25C) 3C) Equivalent resistance (CL = 10 pF) Temperature drift (-10C to 75C) Drive level Motional inductance Insulation resistance Spurious attenuation ratio (at frequency 500 kHz) Overtone spurious
0931B--10/25/04
MIN 14.0625 -15
0.01 20.7 500 3 8
MAX 26 15 100 10 1500 25.3
UNIT MHz ppm ppm mH M dB dB
3
ICS9219
Electrical Characteristics over Recommended Operating Free-Air Temperature
PARAMETER VX VCOS VIK RI IIH Differential crossing-point output voltage Peak-to-peak output voltage swing, single ended Input clamp voltage Input resistance High-level input current X1, X2 X2 FS0 FS1, FS2 IIL Low-level input current X2 FS0 FS1, FS2 High-level output voltage BUSCLKT/C, REF TEST CO NDITIO NS* See Figures 1 and 2 VOH - VOL VDD = 3V VDD = 3.3V VDD = 3.3V VDD = 3.6V VDD = 3.6V VDD = 3.6V VDD = 3.6V VDD = 3.6V See Figure 1 VOH VDD = min to max VDD = 3V VOL Low-level output voltage High-level output current Low-level output current BUSCLKT/C, REF BUSCLKT/C, REF BUSCLKT/C, REF VDD = min to max VDD = 3V VDD = 3.135V VDD = 3.3V VDD = 3.465V VDD = 3.135V VDD = 3.3V VDD = 3.465V r OH r OL CO IDD IDDL IDD (NORMA L) High-level dynamic output resistance 4 Low-level dynamic output resistance4 BUSCLKT, O utput capacitance BUSCLKC, REF Static supply current Static supply current Supply current in normal state IOL IOH IOH = -1 mA IOH = -16 mA IOH = 1 mA IOH = 16 mA VO = 1V VO = 1.65V VO = 3.135V VO = 1.95V VO = 1.65V VO = 0.9V 12 12 -21 43 VDD 0.1V 2.2 1 0.05 0.25 -50 -50 -15 69 69 30 25 17 36 40 40 3 O utputs high or low (VDDT = 0V) O utputs high or low (VDDT = 0V) 400 MHz 533MHz 84 91 6.5 50 100 120 pF mA mA mA mA mA 0.1 0.5 -32 mA V 2.5 See Figure 1 II = -18 mA V I = VO VO = 2V VI = VDD VI = VDD VO = 0V VI = 0V VI = 0V -30 -10 >50 27 10 10 -5.7 -100 -50 2.1 V MIN 1.25 0.4 TYP** 1.6 0.6 MAX 1.85 0.7 -1.2 UNIT V V V k mA mA mA mA
See Figure 1
IO - 14.5 mA to IO - 16.5 mA IO - 14.5 mA to IO - 16.5 mA
* VDD refers to any of the following: VDD, VDDT. ** All typical values are at VDD = 3.3V, T A 25C.
4
r O = VO/IO. This is defined at the output terminals, not at the measurement point of figure 1.
0931B--10/25/04
4
ICS9219
Switching Characteristics over Recommended Operating Free-Air Temperature Range.
PARAMETER t(CYCLE) tJ tJL DC tDC,ERR tCR, tDF tRF tCYCLE(L) t(CJ) t(CJ10) DC(2) tCRL, tCFL Clock cycle time (BUSCLKT/C) Total jitter over 1, 2, 3, 4, 5 or 6 clock cycles Long-term jitter 400 MHz 533 MHz 400 MHz 533 MHz 400 MHz 533 MHz See Figure 3 See Figure 4 See Figure 5 See Figure 6 See Figure 7 See Figure 7 80 See Figure 8 Measured at 50% REF REF See Figure 7 fmod = 50 kHz fmod = 8 MHz -20 -0.2 -1.3 t(CJ) 47% 50 0.8 0.1 43% 51 30 30 120 250 50 TEST CONDITIONS* MIN 1.8 42 33 TYP** MAX 3.7 50 50 300 300 53% 50 50 400 100 142.2 0.2 1.3 t(CJ) 53% 1 -3 ns dB ps UNIT ns ps ps
Output duty cycle over 10,000 cycles Output cycle-to-cycle duty cycle error
Output rise and fall times (measured at BUSCLKT/C 20%-80% of output voltage) Difference between rise and fall times on a single device (20% 80%) |tCR - tCF| Clock cycle time (REF) REF cycle jitter REF 10-cycle jitter Output duty cycle Output rise and fall times (measured at 20%-80% of output voltage) PLL loop bandwidth
ps ps ns ns ns
0931B--10/25/04
5
ICS9219
Measurement Point RT RS Differential Driver CF RS CF RP RP ZCH CMID ZCH RT CMID
Measurement Point
Figure 1. Example System Clock Driver Equivalent Circuit
CLK
Vx+ Vx,nom Vx-
CLKB
Figure 2. Crossing-point Voltage
CLK CLKB t4CYCLE, i t4CYCLE, i+1 tJ = t4CYCLE, i - t4CYCLE, i+1 over 10,000 consecutive cycles
Figure 3. Short-term jitter
CLK
CLKB tCYCLE,i tCYCLE,i+1 tJ = tCYCLE,i - tCYCLE, i+1 over 10,000 consecutive cycles
Figure 4. Cycle-to-cycle jitter
0931B--10/25/04
6
ICS9219
CLK CLKB tPWtCYCLE DC = (tPW+ / tCYCLE) tPW+
Figure 5. Duty Cycle
CLK
Cycle (i)
Cycle (i+1)
CLKB
tPW- (i) tCYCLE (i)
tPW+ (i)
tPW- (i+1) tCYCLE (i+1)
tPW+ (i+1)
tDC,ERR = tPW+(i) - tPW+(i+1) and tPW-(i) - tPW-(i+1)
Figure 6. Cycle-to-cycle Duty Cycle Error
VH 80% V(t) 20% VL tF tR
Figure 7. Input and Output Voltage Waveforms
REF
T
Figure 8. REF Jitter
0931B--10/25/04
7
ICS9219
N
c
L
INDEX AREA
E1
E
12 D
4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) (25.6 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 6.40 BASIC 0.252 BASIC E E1 4.30 4.50 .169 .177 0.65 BASIC 0.0256 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N 0 8 0 8 aaa -0.10 -.004 VARIATIONS
A2 A1
A
-Ce
b SEATING PLANE
N 16
D mm. MIN 4.90 MAX 5.10 MIN .193
D (inch) MAX .201
Ref erence Doc.: JEDEC Publication 95, MO-153 10-0035
aaa C
Ordering Information
ICS9219yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0931B--10/25/04
8

▲Up To Search▲

Price & Availability of ICS9219

	To Download ICS9219 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .