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SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
PRELIMINARY
Some of contents are described for general products and are subject to change without notice.
DESCRIPTION
The M5M4V16G50DFP is a 2-bank x 262,144-word x 32-bit Synchronous GRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V16G50DFP can operate at frequencies of 100+ MHz. The BLOCK WRITE and WRITE-PER-BIT functions provide improved performance in graphic memory systems.
FEATURES
- Single 3.3v0.3v power supply - Clock frequencies of 125 MHz - Fully synchronous operation referenced to clock rising edge - Dual bank operation controlled by A10(Bank Address) - Internal pipelined operation: column address can be changed every clock cycle - Programmable /CAS Latency (LVTTL: 2 and 3) - Programmable Burst Length (1/2/4/8 and Full Page) - Programmable Burst Type (Sequential / Interleave) - Byte control using DQM0 - DQM3 signals in both read and write cycles - Persistent Write-Per-Bit (WPB) function - 8 Column Block Write (BW) function - Auto Precharge / All bank precharge controlled by A9 - Auto Refresh and Self Refresh Capability - 2048 refresh cycles /32ms - LVTTL Interface - 100 pin QFP package with 0.65mm lead pitch
Max. Frequency M5M4V16G50DFP - 8 M5M4V16G50DFP- 10 M5M4V16G50DFP- 12 125MHz 100MHz 83MHz CLK Access Time 7ns 8ns 10ns
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
CLK CKE /CS /RAS /CAS /WE DSF A0-10 A0-9 A0-7 A10 DQ0-31 DQM0-3 Vdd VddQ Vss VssQ
: Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Special Function Enable : Address Input : Row Address inputs : Column Address inputs : Bank Address : Data I/O : Output Disable/ Write Mask : Power Supply : Power Supply for Output : Ground : Ground for Output
MITSUBISHI ELECTRIC
14 VDD 15 VSS 16 DQ20 17 DQ21 18 VSSQ 19 DQ22 20 DQ23 21 VDDQ 22 DQM0 23 DQM2 24 /WE 25 /CAS 26 /RAS 27 /CS 28 A10 29 A8 30
10 11
DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ
12 13
DQ29 VSSQ DQ30 DQ31 VSS NC NC NC NC NC NC NC NC NC NC VDD DQ0 DQ1 VSSQ DQ2
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
1 2 3 4 5 6 7 8 9
80 DQ28 VDDQ 79 DQ27 78 DQ26 77 VSSQ 76 DQ25 75 DQ24 74 VDDQ 73 DQ15 72 71 DQ14 70 VSSQ 69 DQ13 68 DQ12 67 VDDQ 66 VSS 65 VDD 64 DQ11 63 DQ10 62 VSSQ 61 DQ9 60 DQ8 59 VDDQ 58 NC 57 DQM3 56 DQM1 55 CLK 54 CKE 53 DSF 52 NC 51 A9
100 Pin QFP 14.0 x 20.0 mm2 0.65 mm pitch
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
A7 A6 A5 A4 VSS NC NC NC NC NC NC NC NC NC NC VDD A3 A2 A1 A0
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
BLOCK DIAGRAM
DQ0-31
DQM0-3
I/O Buffer
Color Register Mask Register
Memory Array Bank #0
Memory Array Bank #1
Mode Register Control Circuitry
Address Buffer Clock Buffer
Control Signal Buffer
A0-9
A10
/CS
/RAS
/CAS
/WE
DSF
CLK
CKE
Type Designation Code
This rule is applied only to Synchronous DRAM family.
M 5M 4 V 16 G 5 0 D FP - 8
Cycle Time (min.) 8: 8ns, 10: 10ns, 12: 12ns Package Type FP: QFP Process Generation Function 0: Random Column, 1: 2N-rule Organization 2 n 5: x32 Synchronous Graphics RAM Density 16:16M bits Interface V:LVTTL Memory Style (DRAM) Use, Recommended Operating Conditions, etc Mitsubishi Main Designation
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
PIN FUNCTION
CLK Input Master Clock: All other inputs are referenced to the rising edge of CLK. Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is stopped. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. Chip Select: When /CS is high, any command means No Operation. Combination of /RAS, /CAS, /WE, and DSF defines basic commands. A0-9 specify the Row / Column Address in conjunction with BA. The Row Address is specified by A0-9. The Column Address is specified by A0-7. A9 is also used to indicate precharge option. When A9 is high at a read / write command, an auto precharge is performed. When A9 is high at a precharge command, both banks are precharged. Bank Address: A10 (BA) specifies the bank to which a command is applied. A10 (BA) must be set with ACT, PRE, READ, WRITE commands. Data In/Data out are referenced to the rising edge of CLK. These pins are used for input mask pins for Write-Per-Bit and column/byte mask inputs for Block Writes. Input/Output Byte Mask: When DQM0-3 are high during a write, data for the current cycle is masked. When DQM0-3 are high during a read, output data is disabled at the next cycle. DQM0 controls byte 0 (DQ7-0), DQM1 controls byte 1 (DQ15-8), DQM2 controls byte 2 (DQ23-16), and DQM3 controls byte 3 (DQ31-24). Reference voltage for all inputs. Power Supply for the memory array and peripheral circuitry. VddQ and VssQ are supplied to the Output Buffers only.
CKE
Input
/CS /RAS, /CAS, / WE, and DSF
Input Input
A0-9
Input
A10
Input
DQ0-31
Input / Output
DQM0 DQM3
Input
VREF Vdd, Vss VddQ, VssQ
Input Power Supply Power Supply
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
BASIC FUNCTIONS
The M5M4V16G50DFP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS, /WE, and DSF at CLK rising edge. In addition to 3 signals, /CS ,CKE and A9 are used as chip select, refresh option, and precharge option, respectively. For a more detailed definition of commands, please see the command truth table.
CLK /CS /RAS /CAS /WE DSF CKE A9
Chip Select : L=select, H=deselect Command Command Command Command Refresh Option @refresh command Precharge Option @precharge or read/write command define basic commands
Activate (ACT) [/CS, /RAS, DSF = L, /CAS, /WE = H] ACT command activates a row in an idle bank indicated by A10 (BA) and row address selected by A0 - A9. Activate with WPB enable (ACTWPB) [/CS, /RAS = L, /CAS, /WE, DSF = H] This command is the same as Activate except that Write-Per-Bit (WPB) is enabled. The Mask Register's contents are used as the WPB data. Read (READ) [/CS, /CAS, DSF = L, /RAS, /WE = H] READ command starts burst read from the active bank indicated by A10 (BA). First output data appears after /CAS latency. When A9 = H at this command, the bank is deactivated after the burst read (auto-precharge, READA). Write (WRITE) [/CS, /CAS, /WE, DSF = L, /RAS = H] WRITE command starts burst write to the active bank indicated by A10 (BA). Total data length to be written is set by burst length. When A9 = H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA). Precharge (PRE) [/CS, /RAS, /WE, DSF = L, /CAS = H] PRE command deactivates the active bank indicated by A10 (BA). This command also terminates burst read /write operation. When A9 = H at this command, both banks are deactivated (precharge all, PREA).
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
BASIC FUNCTIONS (continued)
Auto-Refresh (REFA) [/CS, /RAS, /CAS, DSF = L, /WE, CKE = H] REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically. Both banks must be precharged before this command can begin. Self-Refresh (REFS) [/CS, /RAS, /CAS, DSF, CKE = L, /WE = H] REFS command starts self-refresh cycle. The self-refresh cycle will continue while CKE remains low. When CKE goes high, self-refresh is exited. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically. Both banks must be precharged before this command can begin. Burst Terminate (TERM) [/CS, /WE, DSF = L, /RAS, /CAS = H] TERM command stops the current burst operation. During read cycles, burst data stops after CAS latency is met. No Operation (NOP) [/CS, DSF = L, /RAS, /CAS, /WE = H] NOP command does not perform any operation on the SGRAM. Mode Register Set (MRS) [/CS, /WE, /RAS, /CAS, DSF = L] MRS command loads the mode register that defines how the device operates. The address pins, A0 A10, are used as input pins for the mode register data. This command must be issued after power-on to initialize the SGRAM. The mode register can only be set when both banks are idle. During the two cycles following this command, the SGRAM cannot accept any other commands. Special Register Set (SRS) [/CS, /WE, /RAS, /CAS = L, DSF = H] SRS command sets the color and mask registers. During the two cycles following this command, the SGRAM cannot accept any other commands. Masked Block Write (BW) [/CS, /CAS, /WE = L, /RAS, DSF = H] BW command starts the 8 column Block Write function. Burst Length = 1 is assumed. Write data comes from the color register and column address mask data is applied on the DQs. When A9 = H at this command, the bank is deactivated after the burst write (auto-precharge, BWA).
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
COMMAND TRUTH TABLE
COMMAND Deselect No Operation Row Address Entry & Bank Activate Row Address Entry & Bank Activate Single Bank Precharge Precharge All Banks Column Address Entry & Write Column Address Entry & Write with AutoPrecharge Column Address Entry & Masked Block Write Masked Block Write with Auto-Precharge Column Address Entry & Read Column Address Entry & Read with AutoPrecharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register Set Special Register Set MNEMONIC DESEL NOP ACT ACTWPB CKE n-1 H H H H H H H CKE n X X X X X X X /CS /RAS /CAS /WE H L L L L L L X H L L L L H X H H H H H L X H H H L L L DSF A10 X L L X X BA BA BA X BA A9 X X Row Row L H L A0-8 X X Add. Add. X X Col.
H L L L
PRE PREA WRITE
WRITEA
H
X
L
H
L
L
L
BA
H
Col.
BW
H
X
L
H
L
L
H
BA
L
Col.
BWA
H
X
L
H
L
L
H L
BA
H
Col.
READ
H
X
L
H
L
H
BA
L
Col.
READA REFA REFS REFSX TERM MRS SRS
H H H L L H H H
X H L H H X X X
L L L H L L L L
H L L X H H L L
L L L X H H L L
H H H X H L L L
L L L X L L L H
BA X X X X X
H X X X X X
Col. X X X X X
OPCODE OPCODE
H=High Level, L=Low Level, BA=Bank Address, Col.=Column Address (A0-A7) Row Add.=Row Address (A0-A9), X=Don't Care, n=CLK cycle number
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
FUNCTION TRUTH TABLE
Current State /CS /RAS /CAS /WE DSF IDLE H L L L L L L L L L L L L L L L ROW ACTIVE H L L L L L L L L L L L X H H H H H H H L L L L L L L L X H H H H H L L L L L L X H H H L L L L H H H H L L L L X H H L L L H H H L L L X H L L H H L L H H L L H H L L X H L H L L H H L H L L X L H L H L L H L H H L H L H L X L L L L X X X X X BA, CA, A9 BA, CA, A9 BA, CA, A9 BA, RA BA, RA X BA, A9 X X Op-Code, Mode-Add Op-Code, Mode-Add X X BA BA, CA, A9 BA, CA, A9 BA, CA, A9 BA, RA BA, RA BA, A9 X Op-Code, Mode-Add Op-Code, Mode-Add Address Command DESEL NOP Undefined TERM Undefined
READ / READA
Action NOP NOP ILLEGAL ILLEGAL*2 ILLEGAL ILLEGAL*2
WRITE / WRITEA ILLEGAL*2
BW / BWA ACT ACTWPB Undefined PRE / PREA Undefined REFA SRS MRS DESEL NOP TERM READ / READA WRITE / WRITEA BW / BWA ACT ACTWPB PRE / PREA REFA SRS MRS
ILLEGAL*2
Bank Active; Latch RA; No Mask Bank Active; Latch RA; Use Mask
ILLEGAL NOP*4 ILLEGAL Auto-Refresh*5 Special Register Set*5 Mode Register Set*5 NOP NOP NOP Begin Read; Latch CA; Determine Auto-Precharge Begin Write; Latch CA; Determine Auto-Precharge Block Write; Latch CA; Determine Auto-Precharge Bank Active / ILLEGAL*2 Bank Active / ILLEGAL*2 Precharge / Precharge All ILLEGAL Special RegisteSet *5 ILLEGAL
H L H L L H L
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
FUNCTION TRUTH TABLE(continued)
Current State /CS /RAS /CAS /WE DSF READ H L L L X H H H X H H L X H L H X L L L X X BA BA, CA, A9 Address Command DESEL NOP TERM Action NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst
Terminate Burst, Latch CA, READ / READA Begin New Read, Determine Auto-Precharge*3 WRITE / WRITEA Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 Terminate Burst, Latch CA, Block Write, Determine AutoPrecharge*3 Bank Active / ILLEGAL*2 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst
L
H
L
L
L
BA, CA, A9
L L L L L L L WRITE H L L L
H L L L L L L X H H H
L H H H L L L X H H L
L H H L H L L X H L H
H L L L L H L X L L L
BA, CA, A9 BA, RA BA, RA BA, A9 X Op-Code, Mode-Add Op-Code, Mode-Add X X BA BA, CA, A9
BW / BWA ACT ACTWPB PRE / PREA REFA SRS MRS DESEL NOP TERM
Terminate Burst, Latch CA, READ / READA Begin Read, Determine AutoPrecharge*3 WRITE / WRITEA BW / BWA ACTWPB ACT PRE / PREA REFA SRS MRS Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 Terminate Burst, Latch CA, Block Write, Determine AutoPrecharge*3 Bank Active / ILLEGAL*2 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL ILLEGAL
L
H
L
L
L
BA, CA, A89
L L L L L L L
H L L L L L L
L H H H L L L
L H H L H L L
L L L L L H L
BA, CA, A9 BA, RA BA, RA BA, A9 X Op-Code, Mode-Add Op-Code, Mode-Add
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
FUNCTION TRUTH TABLE (continued)
Current State /CS /RAS /CAS /WE READ with AUTO PRECHARGE H L L L L L L L L L L L WRITE with AUTO PRECHARGE H L L L L L L L L L L L X H H H H H L L L L L L X H H H H H L L L L L L X H H L L L H H H L L L X H H L L L H H H L L L X H L H L L H H L H L L X H L H L L H H L H L L DSF X L L L L H L H L L H L X L L L L H L H L L H L X X BA BA, CA, A9 BA, CA, A9 BA, CA, A9 BA, RA BA, RA BA, A9 X Op-Code, Mode-Add Op-Code, Mode-Add X X BA BA, CA, A9 BA, CA, A9 BA, CA, A9 BA, RA BA, RA BA, A9 X Op-Code, Mode-Add Op-Code, Mode-Add Address Command DESEL NOP TERM Action NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL
READ / READA ILLEGAL WRITE / WRITEA BW / BWA ACT ACTWPB PRE / PREA REFA SRS MRS DESEL NOP TERM ILLEGAL ILLEGAL Bank Active / ILLEGAL*2 Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL
READ / READA ILLEGAL WRITE / WRITEA BW / BWA ACT ACTWPB PRE / PREA REFA SRS MRS ILLEGAL ILLEGAL Bank Active / ILLEGAL*2 Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL ILLEGAL
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
FUNCTION TRUTH TABLE (continued)
Current State /CS PRE CHARGING H L L L L L L L L L L L ROW ACTIVATING H L L L L L L L L L L L /RAS /CAS /WE DSF X H H H H H L L L L L L X H H H H H L L L L L L X H H L L L H H H L L L X H H L L L H H H L L L X H L H L L H H L H L L X H L H L L H H L H L L X L L L L H L L L L H L X L L L L H L H L L H L X X BA BA, CA, A9 BA, CA, A9 BA, CA, A9 BA, RA BA, RA BA, A9 X Op-Code, Mode-Add Op-Code, Mode-Add X X BA BA, CA, A9 BA, CA, A9 BA, CA, A9 BA, RA BA, RA BA, A9 X Op-Code, Mode-Add Op-Code, Mode-Add Address Command DESEL NOP TERM Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL*2
READ / READA ILLEGAL*2
WRITE / WRITEA ILLEGAL*2
BW / BWA ACT ACTWPB PRE / PREA REFA SRS MRS DESEL NOP TERM
ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 NOP*4 (Idle after tRP) ILLEGAL ILLEGAL ILLEGAL NOP (Row Active after tRCD) NOP (Row Active after tRCD) ILLEGAL*2
READ / READA ILLEGAL*2
WRITE / WRITEA ILLEGAL*2
BW / BWA ACT ACTWPB PRE / PREA REFA SRS MRS
ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL ILLEGAL
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
FUNCTION TRUTH TABLE (continued)
Current State /CS WRITE RECOVERING H L L L L L L L L L L L REFRESHING H L L L L L L L L L L L /RAS /CAS /WE DSF X H H H H H L L L L L L X H H H H H L L L L L L X H H L L L H H H L L L X H H L L L H H H L L L X H L H L L H H L H L L X H L H L L H H L H L L X L L L L H L H L L H L X L L L L H L L L L H L X X BA BA, CA, A9 BA, CA, A9 BA, CA, A9 BA, RA BA, RA BA, A9 X Op-Code, Mode-Add Op-Code, Mode-Add X X BA BA, CA, A9 BA, CA, A9 BA, CA, A9 BA, RA BA, RA BA, A9 X Op-Code, Mode-Add Op-Code, Mode-Add Address Command DESEL NOP TERM NOP NOP ILLEGAL*2 Action
READ / READA ILLEGAL*2
WRITE / WRITEA ILLEGAL*2
BW / BWA ACT ACTWPB PRE / PREA REFA SRS MRS DESEL NOP TERM
ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tRC) NOP (Idle after tRC) ILLEGAL
READ / READA ILLEGAL
WRITE / WRITEA ILLEGAL
BW / BWA ACT ACT PRE / PREA REFA SRS MRS
ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
FUNCTION TRUTH TABLE (continued)
Current State MODE REGISTER SETTING /CS /RAS /CAS /WE DSF H L L L L L L L L L L L X H H H H H L L L L L L X H H L L L H H H L L L X H L H L L H H L H L L X L L L L H L H L L H L X X BA BA, CA, A9 BA, CA, A9 BA, CA, A9 BA, RA BA, RA BA, A9 X Op-Code, Mode-Add Op-Code, Mode-Add Address Command DESEL NOP TERM Action NOP (Idle after tRSC) NOP (Idle after tRSC) ILLEGAL
READ / READA ILLEGAL
WRITE / WRITEA ILLEGAL
BW / BWA ACT ACTWPB PRE / PREA REFA SRS MRS
ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and/or data-integrity are not guaranteed.
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
FUNCTION TRUTH TABLE for CKE
Current State SELFREFRESH*1 CKE CKE n-1 H L L L L L L POWER DOWN H L L ALL BANKS IDLE*2 H H H H H H H L ANY STATE other than listed above H H L L n X H H H H H L X H L H L L L L L L X H L H L /CS X H L L L L X X X X X L H L L L L X X X X X /RAS /CAS /WE DSF Add X X H H H L X X X X X L X H H H L X X X X X X X H H L X X X X X X L X H H L X X X X X X X X H L X X X X X X X H X H L X X X X X X X X X X X X X X X X X X L X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self-Refresh (Idle after tRC) Exit Self-Refresh (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP (Maintain Self-Refresh) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State =Power Down Refer to Function Truth Table Begin CLK Suspend at Next Cycle*3 Exit CLK Suspend at Next Cycle*3 Maintain CLK Suspend Action
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously . A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command.
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SGRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQM0-3 high and NOP condition at the inputs. 2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 500s. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SGRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when both banks are in idle state. After tRSC from a MRS command, the SGRAM is ready for new command.
CLK /CS /RAS /CAS A10 A9 0 0 A8 A7 0 0 A6 A5 A4 A3 A2 A1 A0 /WE LTMODE BT BL DSF A10, A9 -A0
V
CL 000 001 010 011 100 101 110 111 A10 A9 0 0 1 0 A8 0 0 A7 0 0 -
CAS LATENCY LVTTL Reserved Reserved 2 3 Reserved Reserved Reserved Reserved BURST TYPE
BL 000 001 010 011 100 101 110 111 0 1
BURST LENGTH BT= 0 1 2 4 8 Reserved Reserved Reserved Full Page BT= 1 Reserved Reserved 4 8 Reserved Reserved Reserved Reserved
Operating Mode Normal Operation Burst Read and Single Write All Others are Reserved
SEQUENTIAL INTERLEAVED
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
SPECIAL REGISTER
The Mask Register and Color Register can be loaded by setting the special register (SRS). If CR and MR are both high, data in the Mask and Color Registers will be unknown.After tRSC from a SRS command, the SGRAM is ready for new command.
CLK /CS /RAS /CAS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 /WE 0 0 0 0 CR MR 0 0 0 0 0 DSF A10, A9 -A0
V
MR Mask Register 0 1
Operation No Load Operation Load Mask
CR Color Register 0 1
Operation No Load Operation Load Color
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
CLK Command Address DQ CL= 3 BL= 4
Read Y Q0 Q1 Q2 Q3 Write Y D0 D1 D2 D3
/CAS Latency
Burst Length Burst Type
Burst Length
Initial Address BL A2 0 0 0 0 1 1 1 1 A1 A0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 8 0 1 0 1 0 1 4 0 1 0 2 1 1 0 2 3 0 3 0 1 0 1 1 2 4 5 6 7 0 1 5 6 7 0 1 2 6 7 0 1 2 3 7 0 1 2 3 0 0 1 2 3 1 2 3 4 0 1 2 3 1 2 3 4 2 3 4 5 Sequential 3 4 5 6 4 5 6 7 5 6 7 0
Column Addressing Interleaved 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 0 3 2 5 4 7 6 1 0 3 2 1 0 2 3 0 1 6 7 4 5 2 3 0 1 3 2 1 0 7 6 5 4 3 2 1 0 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
NOTE: FULL PAGE BURST is an extension of the above tables of Sequential Addressing with the length being 256.
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
OPERATIONAL DESCRIPTION
BANK ACTIVATE The SGRAM has two independent banks. Each bank is activated by the ACT command with the bank address (A10/BA). A row is indicated by the row address A9-0. The minimum activation interval between one bank and the other bank is tRRD.
PRECHARGE The PRE command deactivates the bank indicated by A10/BA. When both banks are active, the precharge all command (PREA, PRE + A9=H) is available to deactivate them at the same time. After tRP from the precharge, an ACT command can be issued. Bank Activation and Precharge All (BL=4, CL=3)
CLK Command A0-8 A9 A10 DQ
ACT tRRD Xa tRCD Xa 0 Xb 1 0 0 Qa0 Qa1 Qa2 Qa3 1 Xb 1 Xb Y ACT READ tRAS PRE tRP Xb ACT
Precharge all
READ After tRCD from the bank activation, a READ command can be issued. 1st output data is available after the /CAS Latency from the READ, followed by (BL -1) consecutive data when the Burst Length is BL. The start address is specified by A7-0, and the address sequence of burst data is defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous output data (in case of BL=4) by interleaving the dual banks. When A9 is high at a READ command, the auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited until the internal precharge is complete. The internal precharge start timing depends on /CAS Latency. The next ACT command can be issued after tRP from the internal precharge timing.
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
Dual Bank Interleaving READ (BL=4, CL=3)
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
CLK Command A0-8 A9 A10 DQ
/CAS latency ACT tRCD Xa Xa 0 Y 0 0 Xb Xb 1 Qa0 Y 0 1 Qa1 0 0 Qa2 Qa3 Qb0 Qb1 Qb2 READ ACT READ PRE
Burst Length
READ with Auto-Precharge (BL=4, CL=3)
CLK Command A0-8 A9 A10 DQ
ACT tRCD Xa Xa 0 Y 1 0 Qa0 Qa1 Qa2 Qa3 READ tRP Xa Xa 0 ACT
Internal precharge begins
READ Auto-Precharge Timing (BL=4)
CLK Command CL=3 CL=2 DQ DQ
Qa0 ACT READ Qa0 Qa1 Qa1 Qa2 Qa2 Qa3 Qa3
Internal Precharge Start Timing
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SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM WRITE After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set in the same cycle as the WRITE. The following (BL -1) data is written into the RAM, when the Burst Length is BL. The start address is specified by A7-0, and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous output data (in case of BL=4) by interleaving the dual banks. When A9 is high at a WRITE command, the auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited until the internal precharge is complete. The internal precharge begins at tWR after the last input datacycle. The next ACT command can be issued after tRP from the internal precharge timing.
Dual Bank Interleaving WRITE (BL=4)
CLK Command A0-8 A9 A10 DQ
ACT tRCD Xa Xa 0 Y 0 0 Da0 Xb Xb 1 Da1 Da2 Da3 Write ACT tRCD Y tWR 0 1 Db0 0 0 Db1 Db2 Db3 Write PRE
Burst Length
WRITE with Auto-Precharge (BL=4)
CLK Command A0-8 A9 A10 DQ
ACT tRCD Xa Xa 0 Y 1 0
tWR
Write tRP
ACT Xa Xa 0 Da1 Da2 Da3
Da0
Internal precharge begins
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM BURST INTERRUPTION [ Read Interrupted by Read ] Burst read operation can be interrupted by new read of the same or the other bank. M5M4V16G50DFP allows random column access. READ to READ interval is minimum 1 CLK. Read Interrupted by Read (BL=4, CL=3)
CLK Command A0-8 A9 A10 DQ
READ READ Yi 0 0 Yj 0 0 READ Yk 0 1 Qai0 Qaj0 READ Yl 0 0 Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3
[ Read Interrupted by Write ] Burst read operation can be interrupted by write of the same or the other bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQM0 - 3 to prevent bus contention. The output is disabled automatically 2 cycles after WRITE assertion. Read Interrupted by Write (BL=4, CL=3)
CLK Command A0-8 A9 A10 DQM0-3 Q D
Qai0 Daj0 Daj1 Daj2 Daj3 READ Yi 0 0 Write Yj 0 0
DQM0-3 control
Write control
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SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM [ Read Interrupted by Precharge ] Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is minimum 1 CLK. A PRE command disables the data output depending on the /CAS Latency. The figure below shows examples of when the dataout is terminated.
Read Interrupted by Precharge (BL=4)
CLK
Command
READ
PRE
DQ
Q0
Q1
Q2
Q3
Command
READ
PRE
CL=3
DQ Q0 Q1 Q2
Command
READ
PRE
DQ
Q0
Command
READ
PRE
DQ
Q0
Q1
Q2
Q3
Command
READ
PRE
CL=2
DQ Q0 Q1 Q2
Command
READ
PRE
DQ
Q0
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
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M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM [ Read Interrupted by Burst Terminate ] Similarly to the precharge, burst terminate command can interrupt burst read operation and disable the data output. READ to TERM interval is minimum 1 CLK. The figure below shows examples when the dataout is terminated.
Read Interrupted by Burst Terminate (BL=4)
CLK
Command
READ
TERM
DQ
Q0
Q1
Q2
Q3
Command
READ
TERM
CL=3
DQ Q0 Q1 Q2
Command
READ TERM
DQ
Q0
Command
READ
TERM
DQ
Q0
Q1
Q2
Q3
Command
READ
TERM
CL=2
DQ Q0 Q1 Q2
Command
READ
TERM
DQ
Q0
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SGRAM (Rev. 0.0) Jan'97 Preliminary
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M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM [ Write Interrupted by Write ] Burst write operation can be interrupted by new write of the same or the other bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. Write Interrupted by Write (BL=4)
CLK Command A0-8 A9 A10 DQ
Write Write Yi 0 0 Dai0 Yj 0 0 Daj0 Daj1 Write Yk 0 1 Write Yl 0 0 Dal1 Dal2 Dal3
Dbk0 Dbk1 Dbk2 Dal0
[ Write Interrupted by Read ] Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=3)
CLK Command A0-8 A9 A10 DQM0-3 DQ
Dai0 Qaj0 Qaj1 Dak0 Dak1 Qbl0 Write READ Yi 0 0 Yj 0 0 Write Yk 0 0 READ Yl 0 1
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM [ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank. Random column access is allowed.
Write Interrupted by Precharge (BL=4)
CLK Command A0-8 A89 A10 DQM0-3 DQ
Dai0 Dai1 Write Yi 0 0 0 0 PRE
tWR
ACT tRP Xb Xb 0
[ Write Interrupted by Burst Terminate ] Burst terminate command can terminate burst write operation. In this case, the write recovery time is not required and the bank remains active. The figure below shows the case that 3 words of data are written. Random column access is allowed. WRITE to TERM interval is minimum 1 CLK. Write Interrupted by Burst Terminate (BL=4)
CLK Command A0-8 A9 A10 DQM0-3 DQ
Dai0 Dai1 Dai2 Write Yi 0 0 TERM
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM AUTO REFRESH Single cycle of auto-refresh is initiated with REFA (/CS= /RAS= /CAS= DSF= L, /WE= /CKE= H) command. The refresh address is generated internally. 2048 REFA cycles within 32ms refresh 16Mbit memory cells. The auto-refresh is performed on each bank alternately (ping-pong refresh). Before performing an auto-refresh, both banks must be in the idle state. Additional commands must not be supplied to the device before tRC from the REFA command.
Auto-Refresh
CLK /CS NOP or DESLECT /RAS /CAS /WE DSF CKE A0-9 A10 minimum tRC
Auto Refresh on Bank 0
Auto Refresh on Bank 1
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SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= DSF= L, /WE= H, CKE= L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the selfrefresh mode, CKE is asynchronous and the only enabled input (but asynchronous), all other inputs including CLK are disabled and ignored, and power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE (REFSX). After tRC from REFSX both banks are in the idle state and a new command can be issued after tRC, but DESEL or NOP commands must be asserted until then.
Self-Refresh
CLK
Stable CLK
/CS /RAS /CAS /WE DSF CKE
NOP
new command
A0-9 A10
X 0
Self Refresh Entry
Self Refresh Exit
minimum tRC for recovery
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM CLK SUSPEND CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle, but a command at the following cycle is ignored.
ext.CLK
CKE
int.CLK
Power Down by CKE
CLK CKE Command
PRE NOP NOP Standby Power Down
NOP NOP NOP
NOP NOP
CKE Command
ACT NOP NOP
Active Power Down
NOP NOP NOP
NOP NOP
DQ Suspend by CKE
CLK CKE Command
Write READ
DQ
D0
D1
D2
D3
Q0
Q1
Q2
Q3
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SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM DQM0 - 3 CONTROL DQM0 - 3 is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQM0 - 3 masks input data. DQM0 - 3 to write mask latency is 0. During reads, DQM0 - 3 forces output to Hi-Z. DQM0 - 3 to output Hi-Z latency is 2. DQM0 masks DQ0-7, DQM1 masks DQ8-15, DQM2 masks DQ16-23, DQM3 masks DQ24-031.
DQM0 - 3 Function
CLK Command DQM0
Write READ
DQ(0-7)
D0
D2
D3
Q0
Q1
Q3
masked by DQM0=High DQM1
disabled by DQM0=High
DQ(8-15)
D0
D1
D3
Q0
Q2
Q3
masked by DQM1=High DQM2
disabled by DQM1=High
DQ(16-23)
D0
D1
D2
D3
Q0
Q1
Q3
masked by DQM2=High DQM3
disabled by DQM2=High
DQ(24-31)
D0
D1
D2
D3
Q1
Q2
Q3
masked by DQM3=High
disabled by DQM3=High
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
ABSOLUTE MAXIMUM RATINGS
Symbol Vdd VddQ VI VO IO Pd Topr Tstg Parameter Supply Voltage Supply Voltage for Output Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Ta = 25 C Conditions with respect to Vss with respect to VssQ with respect to Vss with respect to VssQ Ratings -0.5 ~ 4.6 -0.5 ~ 4.6 -0.5 ~ 4.6 -0.5 ~ 4.6 50 1000 0 ~ 70 -65 ~ 150 Unit V V V V mA mW C C
RECOMMENDED OPERATING CONDITIONS
(Ta=0 ~ 70C, unless otherwise noted)
Limits Symbol Vdd Vss VddQ VssQ VIH*1 VIL*2 Parameter Min. Supply Voltage Supply Voltage Supply Voltage for Output Supply Voltage for Output High-Level Input Voltage all inputs Low-Level Input Voltage all inputs 3.0 0 3.0 0 2.0 -0.3 Typ. 3.3 0 3.3 0 Max. 3.6 0 3.6 0 VddQ+0.3 0.8 V V V V V V Unit
NOTES: 1. VIH (max) = 5.5V for pulse width less than 10ns. 2. VIL (min) = -1.0V for pulse width less than 10ns.
CAPACITANCE
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Symbol CI(A) CI(C) CI(K) CI/O Parameter Input Capacitance, address pin Input Capacitance, control pin Input Capacitance, CLK pin Input Capacitance, I/O pin VI=Vss f=1MHz Vi=25mVrms Test Condition Limits (max.) 5 5 5 7 Unit pF pF pF pF
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Limits(max) Symbol Parameter Test Conditions -8 Icc1s*1 operating current, single bank tRC=min, tCLK=min, BL=1, CL=3 Icc1d*1 operating current, dual bank Icc2h Icc2l Icc3 Icc4*1 Icc5 Icc6 Icc7 standby current, CKE=H standby current, CKE=L active standby current burst current auto-refresh current self-refresh current operating current, block write tRC=min, tCLK=min, BL=1, CL=3 both banks idle, tCLK=min, CKE=H both banks idle, tCLK=min, CKE=L both banks active, tCLK=min, CKE=H tCLK=min, BL=4, CL=3, 1 bank idle tRC=min, tCLK=min CKE <0.2v tCLK=min -10 -12 mA mA mA mA mA mA mA mA mA Unit
TBD TBD TBD TBD TBD TBD TBD TBD TBD
NOTES: 1. Icc (max) is specified at the output open condition.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Limits Symbol Parameter Test Conditions Min. VOH (DC) High-Level Output Voltage (DC) VOL (DC) Low-Level Output Voltage (DC) IOZ Off-state Output Current Input Current IOH=-2mA IOL= 2mA Q floating VO=0 ~ VddQ VIH = 0 ~ VddQ+0.3V -10 -10 2.4 0.4 10 10 Max. V V A A Unit
II
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3v, Vss = VssQ = 0v, unless otherwise noted) Input Pulse Levels : 0.8V to 2.0V Input Timing Measurement Level : 1.4V
Limits Symbol Parameter Min. tCLK CLK cycle time CL=2 CL=3 tCH tCL tT tIS tIH tRC tRCD tRAS tRP tWR tRRD tRSC tPDE tREF tBWC CLK High pulse width CLK Low pulse width Transition time of CLK Input Setup time (all inputs) Input Hold time (all inputs) Row Cycle time Row to Column Delay Row Active time Row Precharge time Write Recovery time Act to Act Delay time Mode Register Set Cycle time Power Down Exit time Refresh Interval time Block Write Cycle time 16 8 12 8 3 3 1 2.5 1 96 24 70 30 8 30 16 8 32 20 10 10000 10 -8 Max. Min. 15 10 3.5 3.5 1 2.5 1 100 30 70 30 10 30 20 12 32 24 12 10000 10 -10 Max. Min. 18 12 4 4 1 3 1.5 120 36 84 36 12 36 24 15 32 10000 10 -12 Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns Unit
tBPL Block Write to Precharge
CLK
1.4V
Signal
1.4V
Any AC timing is referenced to the input signal crossing through 1.4V.
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
SWITCHING CHARACTERISTICS
(Ta=0 ~ 70C, Vdd = VddQ = 3.3 0.3v, Vss = VssQ = 0v, unless otherwise noted)
Limits Symbol Parameter Min. CL=2 tAC Access time from CLK CL=3 tOH Output Hold time from CLK Delay time, output low impedance from CLK Delay time, output high impedance from CLK 3 7 3 8 3 10 ns ns -8 Max. 9 Min. -10 Max. 11 Min. -12 Max. 14 ns Unit
tOLZ
0
0
0 8
ns
tOHZ
3
7
3
3
8
ns
Output Load Condition
VTT=1.4V 50* VREF =1.4V DQ VOUT 50pF Output Timing Measurement Reference Point 1.4V CLK 1.4V
CLK
1.4V
DQ
tAC tOH
tOHZ
1.4V
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