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| CUSTOMER P ROCUREMENT S PECIFICA TION Z86E21 CMOS Z8(R) OTP MICROCONTROLLER GENERAL DESCRIPTION The Z86E21 microcontroller (MCU) introduces the next level of sophistication to single-chip architecture. The Z86E21 is a member of the Z8 single-chip microcontroller family with 8 Kbytes of EPROM and 236 bytes of general purpose RAM. The Z86E21 is a pin compatible, One-Time-Programmable (OTP) version of the Z86C21. The Z86E21 contains 8 Kbytes of EPROM memory in place of the 8 Kbyte of ROM on the Z86C21. The MCU is housed in a 40-pin DIP, 44-pin Leaded ChipCarrier, or a 44-pin Quad Flat Pack, and is manufactured in CMOS technology. The ROMless pin option is available on the 44-pin versions only. The MCU can address both external memory and preprogrammed ROM which enables this Z8 microcomputer to be used in high volume applications or where code flexibility is required. Zilog's CMOS microcontroller offers fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion along with low cost and low power consumption. The Z86E21 architecture is based on Zilog's 8-bit microcontroller core. The device offers a flexible I/O scheme, an efficient register and address space structure, multiplexed capabilities between address/data, I/O, and a number of ancillary features that are useful in many industrial and advanced scientific applications. The device applications demand powerful I/O capabilities. The Z86E21 fulfills this with 32-pin dedicated to input and output. These lines are grouped into four ports. Each port consists of eight lines, and is configurable under software control to provide timing, status signals, serial or parallel I/O with or without handshake, and an address/data bus for interfacing external memory. There are three basic address spaces available to support this wide range of configuration: Program Memory, Data Memory and 236 General-Purpose registers. To unburden the program from coping with real-time problems such as counting/timing and serial data communication, the Z86E21 offers two on-chip counter/timers with a large number of user selectable modes, and an asynchronous receiver/transmitter (UART) (see Functional Block Description). In ROM Protect Mode, the instructions LDC, LDCI, LDE and LDEI are disabled when reading address locations %0000 to %1FFF. Notes: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS PRODUCT RECOMMENDATIONS Zilog recommends the following programming equipment for use with this One-Time-Programmable product: Recommended Revision Level Hardware Software B 1.5 1.1 3.7 Device Z86E21 Z86E21 Z86E21 Zilog Support Tool Z86C1200ZEM ICEBOX TM Emulator* (*Does not support 4K/8K option.) Data I/O 3900 Programmer* (*Does not support option bits.) Data I/O Unisite Programmer* (*Does not support option bits.) Some non-Zilog programmers may have different programming waveforms, voltages and timings and not all programmers may meet the programming requirements of Zilog's One-Time-Programmable products. DC-2964-10 If difficulty is encountered in programming a Zilog OTP product, please contact your local Zilog sales office. 1 GENERAL DESCRIPTION (Continued) Output Input Vcc GND XTAL /AS /DS R//W /RESET Port 3 Machine Timing and Instruction Control UART ALU Counter/ Timers (2) FLAGS Prg. Memory 8192 x 8-Bit Interrupt Control Register Pointer Register File 256 x 8-Bit Program Counter Port 2 Port 0 Port 1 4 I/O (Bit Programmable) 4 8 Address/Data or I/O (Byte Programmable) Address or I/O (Nibble Programmable) Functional Block Diagram 2 PIN DESCRIPTION Standard Mode VCC XTAL2 XTAL1 P37 P30 /RESET R//W /DS /AS P35 GND P32 P00 P01 P02 P03 P04 P05 P06 P07 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 P36 P31 P27 P26 P25 P24 P23 P22 P21 P20 P33 P34 P17 P16 P15 P14 P13 P12 P11 P10 Z86E21 DIP 31 30 29 28 27 26 25 24 23 22 21 40-Lead DIP Pin Assignments 40-Lead DIP Pin Identification Pin # 1 2 3 4 5 6 7 8 9 10 Symbol V CC XTAL2 XTAL1 P37 P30 /RESET R//W /DS /AS P35 Function Power Supply Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3 pin 7 Port 3 pin 0 Reset Read/Write Data Strobe Address Strobe Port 3 pin 5 Direction Input Output Input Output Input Input Output Output Output Output Pin # 11 12 13-20 21-28 29 30 31-38 39 40 Symbol GND P32 P00-P07 P10-P17 P34 P33 P20-P27 P31 P36 Function Ground, GND Port 3 pin 2 Port 0 pin 0,1,2,3,4,5,6,7 Port 1 pin 0,1,2,3,4,5,6,7 Port 3 pin 4 Port 3 pin 3 Port 2 pin 0,1,2,3,4,5,6,7 Port 3 pin 1 Port 3 pin 6 Direction Input Input In/Output In/Output Output Input In/Output Input Output 3 PIN DESCRIPTION (Continued) Standard Mode XTAL1 XTAL2 VCC P30 P37 P36 P31 P27 P26 P25 N/C 6 /RESET R//W /DS /AS P35 GND P32 P00 P01 P02 R//RL 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 N/C P24 P23 P22 P21 P20 P33 P34 P17 P16 P15 Z86E21 PLCC 34 33 32 31 30 29 P03 P04 P05 P06 P07 P10 P11 P12 P13 44-Lead PLCC Pin Assignments 44-Lead PLCC Pin Identification Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 Symbol VCC XTAL2 XTAL1 P37 P30 N/C /RESET R//W /DS /AS P35 GND P32 Function Power Supply Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3 pin 7 Port 3 pin 0 Not Connected Reset Read/Write Data Strobe Address Strobe Port 3 pin 5 Ground, GND Port 3 pin 2 Direction Input Output Input Output Input Input Input Output Output Output Output Input Input Pin # 14-16 17 18-22 23-27 28 29-31 32 33 34-38 39 40-42 43 44 Symbol P00-P02 R//RL P03-P07 P10-P14 N/C P15-P17 P34 P33 P20-P24 N/C P25-P27 P31 P36 Function Port 0 pin 0,1,2 ROM/ROMless control Port 0 pin 3,4,5,6,7 Port 1 pin 0,1,2,3,4 Not Connected Port 1 pin 5,6,7 Port 3 pin 4 Port 3 pin 3 Port 2 pin 0,1,2,3,4 Not Connected Port 2 pin 5,6,7 Port 3 pin 1 Port 3 pin 6 Direction In/Output Input In/Output In/Output Input In/Output Output Input In/Output Input In/Output Input Output 4 P14 N/C XTAL1 XTAL2 GND VCC P30 P37 P36 P31 P27 P26 33 32 31 30 29 28 27 26 25 24 23 /RESET R//W /DS /AS P35 GND P32 P00 P01 P02 R//RL 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 GND P24 P23 P22 P21 P20 P33 P34 P17 P16 P15 P25 Z86E21 QFP 18 17 16 15 14 13 12 GND P03 P04 P05 P06 P07 P10 P11 P12 P13 44-Lead QFP Pin Assignments 44-Lead QFP Pin Identification Pin # 1-5 6 7-14 15 16 17-21 22 23-25 26 27 28 29 30 Symbol P03-P07 GND P10-P17 P34 P33 P20-P24 GND P25-P27 P31 P36 GND VCC XTAL2 Function Port 0 pin 3,4,5,6,7 Ground, GND Port 1 pin 0,1,2,3,4,5,6,7 Port 3 pin 4 Port 3 pin 3 Port 2 pin 0,1,2,3,4 Ground, GND Port 2 pin 5,6,7 Port 3 pin 1 Port 3 pin 6 Ground, GND Power Supply Crystal, Oscillator Clock Direction In/Output Input In/Output Output Input In/Output Input In/Output Input Output Input Input Output Pin # 31 32 33 34 35 36 37 38 39 40 41-43 44 Symbol XTAL1 P37 P30 /RESET R//W /DS /AS P35 GND P32 P00-P02 R//RL Function Crystal, Oscillator Clock Port 3 pin 7 Port 3 pin 0 Reset Read/Write Data Strobe Address Strobe Port 3 pin 5 Ground, GND Port 3 pin 2 Port 0 pin 0,1,2 ROM/ROMless control Direction Input Output Input Input Output Output Output Output Input Input In/Output Input P14 5 ABSOLUTE MAXIMUM RATINGS Symbol Description VCC TSTG TA Supply Voltage* Storage Temp Oper Ambient Temp Min -0.3 -65 Max Units +7.0 +150 V C C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. Notes: * Voltages on all pins with respect to GND. 13.0 V Maximum on P30-P33. See Ordering Information STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Test Load Diagram). From Output Under Test +5V 2.1 k 150 pF 9.1 k Test Load Diagram 6 DC CHARACTERISTICS T A = 0C to +70C Min Max 7 13 VCC 0.8 VCC 0.8 0.4 3.8 -0.03 -10 -10 VCC 0.8 10 10 -50 50 60 15 20 20 20 3.8 -0.03 -10 -10 T A = -40C to +105C Min Max 7 13 VCC 0.8 VCC 0.8 0.4 VCC 0.8 10 10 -50 50 60 15 20 20 20 25 35 5 10 5 5 Sym. Parameter Max Input Voltage Max Input Voltage Clock Input High Voltage Clock Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Reset Input High Voltage Reset Input Low Voltage Input Leakage Output Leakage Reset Input Current Supply Current Standby Current Standby Current Typical @ 25C Units V V V V V V V V V V A A A mA mA mA mA A A Conditions IIN 250 A P30-P33 Only Driven by External Clock Generator Driven by External Clock Generator VCH VCL VIH VIL VOH VOL VRH VRl IIL IOL IIR ICC ICC1 ICC2 3.8 -0.03 2.0 -0.3 2.4 3.8 -0.03 2.0 -0.3 2.4 IOH = -2.0 mA IOL = +2.0 mA 0V V IN +5.25V 0V V IN +5.25V VCC= +5.25V, VRL = 0V @ 12 MHz @ 16 MHz HALT Mode VIN = OV, VCC @ 12 MHz HALT Mode VIN = OV, VCC @ 16 MHz STOP Mode VIN = OV, VCC @ 12 MHz STOP Mode VIN = OV, VCC @ 16 MHz Notes: I CC2 requires loading TMR (%F1H) with any value prior to STOP execution. Use this sequence: LD TMR,#00 NOP 7 AC CHARACTERISTICS External I/O or Memory Read or Write Timing Diagram R//W 13 12 Port 0, /DM 16 19 3 Port 1 A 1 7 -A 2 0 D 7 - D IN 0 9 /AS 8 4 5 6 18 11 /DS (Read) 17 10 Port 1 A 7 -A 0 14 D - D OUT 7 0 15 7 /DS (Write) External I/O or Memory Read/Write Timing 8 AC CHARACTERISTICS External I/O or Memory Read and Write Timing Table TA = 0C to 70C T A = -40C to 105C 12 MHz 16 MHz 12 MHz 16 MHz Max Min Max Min Max Min Max Min Units Notes 35 45 220 55 0 185 110 130 0 45 55 30 35 35 35 255 55 75 50 40 60 30 0 35 30 20 30 25 30 200 65 75 50 35 0 135 80 75 0 65 45 33 50 35 55 310 45 60 30 20 30 180 55 0 185 110 130 0 50 35 25 35 25 35 230 35 45 250 40 0 135 80 75 25 35 180 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns [2,3] [2,3] [1,2,3] [2,3] [1,2,3] [1,2,3] [1,2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [1,2,3] [2,3] [1,2,3] [2,3] No Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 TdA(AS) TdAS(A) TdAS(DR) TwAS TdAZ(DS) TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TdDI(DS) TdDM(AS) Parameter Address Valid to /AS Rise Delay /AS Rise to Address Float Delay /AS Rise to Read Data Req'd Valid /AS Low Width Address Float to /DS Fall /DS (Read) Low Width /DS (Write) Low Width /DS Fall to Read Data Req'd Valid Read Data to /DS Rise Hold Time /DS Rise to Address Active Delay /DS Rise to /AS Fall Delay R//W Valid to /AS Rise Delay /DS Rise to R//W Not Valid Write Data Valid to /DS Fall (Write) Delay /DS Rise to Write Data Not Valid Delay Address Valid to Read Data Req'd Valid /AS Rise to /DS Fall Delay Data Input Setup to /DS Rise /DM Valid to /AS Fall Delay Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] See clock cycle dependent characteristics table. Standard Test Load All timing references use 2.0V for a logic 1 and 0.8V for a logic 0. Clock Dependent Formulas Number 1 2 3 4 6 7 8 10 11 12 13 14 15 16 17 18 19 Symbol TdA(AS) TdAS(A) TdAS(DR) TwAS TwDSR TwDSW TdDSR(DR) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TsDI(DS) TdDM(AS) Equation 0.40TpC + 0.32 0.59TpC - 3.25 2.38TpC + 6.14 0.66TpC - 1.65 2.33TpC - 10.56 1.27TpC + 1.67 1.97TpC - 42.5 0.8TpC 0.59TpC - 3.14 0.4TpC 0.8TpC - 15 0.4TpC 0.88TpC - 19 4TpC - 20 0.91TpC - 10.7 0.8TpC - 10 0.9TpC - 26.3 9 AC CHARACTERISTICS Additional Timing Diagram 1 3 Clock 2 2 3 T IN 4 IRQ N 5 Additional Timing AC CHARACTERISTICS Additional Timing Table TA = 0C to 70C T A = -40C to 105C 12 MHz 16 MHz 12 MHz 16 MHz Max Min Max Min Max Min Max Min Units Notes 83 37 75 3TpC 8TpC 100 70 3TpC 3TpC 1000 15 62.5 1000 10 21 50 3TpC 8TpC 100 50 3TpC 3TpC 83 37 75 3TpC 8TpC 100 70 3TpC 3TpC 1000 15 62.5 1000 10 21 50 3TpC 8TpC 100 50 3TpC 3TpC ns ns ns ns [1] [1] [1] [2] [2] [2] [2] [2,4] [2,5] [2,3] No Symbol 1 2 3 4 5 6 7 8A 8B 9 TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin,TfTin TwIL TwIL TwIH Parameter Input Clock Period Clock Input Rise & Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise & Fall Times Interrupt Request Input Low Times Interrupt Request Input Low Times Interrupt Request Input High Times ns ns Notes: [1] Clock timing references use 3.8V for a logic 1 and 0.8V for a logic 0. [2] Timing references use 2.0V for a logic 1 and 0.8V for a logic 0. [3] Interrupt references request via Port 3. [4] Interrupt request via Port 3 (P31-P33). [5] Interrupt request via Port 30. 10 AC CHARACTERISTICS Handshake Timing Diagrams Data In Data In Valid Next Data In Valid 1 3 2 /DAV (Input) 4 Delayed DAV 5 6 RDY (Output) Delayed RDY Input Handshake Timing Data Out Data Out Valid Next Data Out Valid 7 /DAV (Output) 8 10 9 Delayed DAV 11 RDY (Input) Delayed RDY Output Handshake Timing 11 AC CHARACTERISTICS Handshake Timing Table TA = 0C to 70C 12 MHz 16 MHz Max Min Max Min 0 145 110 115 115 0 TpC 0 115 110 115 110 115 0 115 110 115 0 TpC 0 115 110 115 0 145 110 115 115 0 TpC 0 115 TA = -40C to 105C 12 MHz 16 MHz Max Min Max Min 0 145 110 115 115 0 TpC 0 145 110 115 115 No 1 2 3 4 5 6 7 8 9 10 11 Symbol TsDI(DAV) ThDI(DAV) TwDAV TdDAVI(RDY) TdDAVId(RDY) TdDO(DAV) TcLDAV0(RDY) TcLDAV0(RDY) TdRDY0(DAV) TwRDY TdRDY0d(DAV) Parameter Data In Setup Time Data In Hold Time Data Available Width DAV Fall to RDY Fall Delay DAV Rise to RDY Rise Delay RDY Rise to DAV Fall Delay Data Out to DAV Fall Delay DAV Fall to RDY Fall Delay RDY Fall to DAV Rise Delay RDY Width RDY Rise to DAV Fall Delay Data Direction IN IN IN IN IN IN OUT OUT OUT OUT OUT (c) 1995 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com 12 |
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