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| PRELIMINARY WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM PRELIMINAR YP RODUCT S PECIFICA TION Z86E61/E63 CMOS Z8(R) 16K/32K EPROM MICROCONTROLLER FEATURES s s s s s s s s s s s 8-Bit CMOS Microcontroller 40-Pin DIP, 44-Pin PLCC Style Packages 4.5V to 5.5V Operating Range Clock Speeds: 16 and 20 MHz s s s High Voltage Protection on High Voltage Inputs RAM and EPROM Protect EPROM: 16 Kbytes Z86E61 32 Kbytes Z86E63 256 Bytes Register File - 236 Bytes of General-Purpose RAM - 16 Bytes of Control and Status Registers - 4 Bytes for Ports Two Programmable 8-Bit Counter/Timers Each with 6-Bit Programmable Prescaler Six Vectored, Priority Interrupts from Eight Different Sources On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, or External Clock Drive s Low Power Consumption: 275 mW (max) Fast Instruction Pointer: 1.0 ms @ 12 MHz Two Standby Modes: STOP and HALT 32 Input/Output Lines s s Full-Duplex UART All Digital Inputs are TTL Levels Auto Latches s GENERAL DESCRIPTION The Z86E61/E63 microcontrollers are members of the Z8(R) single-chip microcontroller family with 16K/32 Kbytes of EPROM and 236 bytes of general-purpose RAM. Offered in 40-pin DIP or 44-pin PLCC package styles, these devices are pin-compatible EPROM versions of the Z86C61/ 63. The ROMless pin option is available on the 44-pin versions only. With 4 Kbytes of ROM and 236 bytes of general-purpose RAM, the Z86E61/E63 offers fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion. For applications demanding powerful I/O capabilities, the Z86E61/E63 offers 32 pins dedicated to input and output. These lines are grouped into four ports. Each port consists of eight lines, and is configurable under software control to provide timing, status signals, serial or parallel I/O with or without handshake, and an address/data bus for interfacing external memory. The Z86E61/E63 can address both external memory and preprogrammed ROM, making it well suited for highvolume applications or where code flexibility is required. 1 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM GENERAL DESCRIPTION (Continued) There are three basic address spaces available to support this configuration: Program Memory, Data Memory, and 236 general-purpose registers. To unburden the system from coping with real-time tasks such as counting/timing and serial data communication, the Z86E61/E63 offers two on-chip counter/timers with a large number of user selectable modes (Figure 1). Notes: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS Output Input Vcc GND XTAL /AS /DS R//W /RESET Port 3 Machine Timing and Instruction Control UART ALU Counter/ Timers (2) FLAGS Prg. Memory 16K/32K Register Pointer Register File 256 x 8-Bit Program Counter Interrupt Control Port 2 Port 0 Port 1 4 I/O (Bit Programmable) 4 8 Address/Data or I/O (Byte Programmable) Address or I/O (Nibble Programmable) Figure 1. Z86E61/E63 Functional Block Diagram 2 PRELIMINARY WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM PIN DESCRIPTION Standard Mode Table 1. 40-Pin DIP Pin Identification VCC XTAL2 XTAL1 P37 P30 /RESET R//W /DS /AS P35 GND P32 P00 P01 P02 P03 P04 P05 P06 P07 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 P36 P31 P27 P26 P25 P24 P23 P22 P21 P20 P33 P34 P17 P16 P15 P14 P13 P12 P11 P10 Standard Mode Pin # Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13-20 21-28 29 30 31-38 39 40 VCC XTAL2 XTAL1 P37 P30 /RESET R//W /DS /AS P35 GND P32 P07-P00 P17-P10 P34 P33 P27-P20 P31 P36 Function Power Supply Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3, Pin 7 Port 3, Pin 0 Reset Read/Write Data Strobe Address Strobe Port 3, Pin 5 Direction Input Output Input Output Input Input Output Output Output Output Z86E61 /E63 DIP 31 30 29 28 27 26 25 24 23 22 21 Ground Input Port 3, Pin 2 Input Port 0, Pins 0,1,2,3,4,5,6,7 In/Output Port 1, Pins 0,1,2,3,4,5,6,7 In/Output Port 3, Pin 4 Output Port 3, Pin 3 Input Port 2, Pins 0,1,2,3,4,5,6,7 In/Output Port 3, Pin 1 Input Port 3, Pin 6 Output Figure 2. 40-Pin DIP Pin Configuration 3 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM PIN DESCRIPTION (Continued) Standard Mode XTAL1 XTAL2 VCC P30 P37 P36 P31 P27 P26 P25 N/C 6 /RESET R//W /DS /AS P35 GND P32 P00 P01 P02 R//RL 7 8 9 10 11 12 13 14 15 16 17 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 NC P24 P23 P22 P21 P20 P33 P34 P17 P16 P15 Z86E61/E63 PLCC 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 P03 P04 P05 P06 P07 P10 P12 P13 P14 P11 N/C Figure 3. 44-Pin PLCC Pin Configuration Table 2. 44-Pin PLCC Pin Identification Standard Mode Pin # Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 VCC XTAL2 XTAL1 P37 P30 N/C /RESET R//W /DS /AS P35 GND P32 Function Power Supply Crystal, Osc. Clock Crystal, Osc. Clock Port 3, Pin 7 Port 3, Pin 0 Not Connected Reset Read/Write Data Strobe Address Strobe Port 3, Pin 5 Ground Port 3, Pin 2 Direction Input Output Input Output Input Input Input Output Output Output Output Input Input Standard Mode Pin # Symbol 14-16 17 18-22 23-27 28 29-31 32 33 34-38 39 40-42 43 44 P02-P00 R//RL P07-P03 P10-P14 N/C P17-P15 P34 P33 P24-P20 N/C P27-P25 P31 P36 Function Port 0, Pins 0,1,2 ROM/ROMless control Port 0, Pins 3,4,5,6,7 Port 1, Pins 0,1,2,3,4 Not Connected Port 1, Pins 5,6,7 Port 3, Pin 4 Port 3, Pin 3 Port 2, Pins 0,1,2,3,4 Not Connected Port 2, Pins 5,6,7 Port 3, Pin 1 Port 3, Pin 6 Direction In/Output Input In/Output In/Output Input In/Output Output Input In/Output Input In/Output Input Output 4 PRELIMINARY WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM PIN DESCRIPTION EPROM Mode VCC XTAL2 XTAL1 N/C /CE /RESET N/C N/C N/C N/C GND EPM A0 A1 A2 A3 A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Table 3. 40-Pin DIP Pin Identification 40 39 38 37 36 35 34 33 32 N/C /OE /PGM A14 A13 A12 A11 A10 A9 A8 VPP N/C D7 D6 D5 D4 D3 D2 D1 D0 EPROM Mode Pin # Symbol 1 2 3 4 5 6 7-10 11 12 13-20 21-28 29 30 31-37 38 39 40 VCC XTAL2 XTAL1 N/C /CE /RESET N/C GND EPM A7-A0 D7-D0 N/C VPP A14-A8 /PGM /OE N/C Function Power Supply Crystal, Osc. Clock Crystal, Osc. Clock Not Connected Chip Enable Reset Not Connected Ground EPROM Prog Mode Address 0,1,2,3,4,5,6,7 Data 0,1,2,3,4,5,6,7 Not Connected Prog Voltage Address 8,9,10,11,12,13,14 Prog Mode Output Enable Not Connected Direction Input Output Input Input Input Input Input Input Input Input In/Output Input Input Input Input Input Input Z86E61 /E63 DIP 31 30 29 28 27 26 25 24 23 22 21 Figure 4. 40-Pin DIP Pin Configuration 5 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM PIN DESCRIPTION (Continued) EPROM Mode XTAL2 XTAL1 /PGM VCC A14 A13 39 38 37 36 35 /CE 6 /RESET N/C N/C N/C N/C GND EPM A0 A1 A2 N/C 7 8 9 10 11 12 13 14 15 16 17 5 4 3 2 1 44 43 42 41 40 N/C A12 A11 A10 A9 A8 VPP N/C D7 D6 D5 Z86E61/E63 PLCC /OE N/C N/C N/C 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 Figure 5. 44-Pin PLCC Pin Configuration Table 4. 44-Pin PLCC Pin Identification EPROM Mode Pin # Symbol 1 2 3 4 5 6 7 8-11 12 13 14-16 17 VCC XTAL2 XTAL1 N/C /CE N/C /RESET N/C GND EPM A0-A2 N/C Function Power Supply Crystal, Osc. Clock Crystal, Osc. Clock Not Connected Chip Enable Not Connected Reset Not Connected Ground EPROM Prog Mode Address 0,1,2 Not Connected Direction Input Input Input Input Input Input Input Input Input Input Input Input EPROM Mode Pin # Symbol 18-22 23-27 28 29-31 32 33 34-38 39 40-41 42 43 44 A7-A3 D4-D0 N/C D7-D5 N/C V PP A12-A8 N/C A13-A14 /PGM /OE N/C Function Address 3,4,5,6,7 Data 0,1,2,3,4 Not Connected Data 5,6,7 Not Connected Prog Voltage Address 8,9,10,11,12 Not Connected Address 13, 14 Prog Mode Output Enable Not Connected Direction Input In/Output Input In/Output Input Input Input Input Input Input Input Input 6 N/C D0 D1 D2 D3 D4 A3 A4 A5 A6 A7 PRELIMINARY WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM PIN FUNCTIONS ROMless (input, active Low). Connecting this pin to GND disables the internal ROM and forces the device to function as a Z86C91 ROMless Z8 (see the Z86C91 product specification for more information). When left unconnected or pulled High to VCC, the device functions as a normal Z86E61/E63 EPROM version. Note: This pin is only available on the 44-pin versions of the Z86E61/E63. /DS (output, active Low). Data Strobe is activated once for each external memory transfer. For a READ operation, data must be available prior to the trailing edge of /DS. For WRITE operations, the falling edge of /DS indicates that output data is valid. /AS (output, active Low). Address Strobe is pulsed once at the beginning of each machine cycle. Address output is through Port 1 for all external programs. Memory address transfers are valid at the trailing edge of /AS. Under program control, /AS can be placed in the highimpedance state along with Ports 0 and 1, Data Strobe, and Read/Write. XTAL2, XTAL1 Crystal 2, Crystal 1 (time-based input and output, respectively). These pins connect a parallelresonant crystal, ceramic resonator, LC, or any external single-phase clock to the on-chip oscillator and buffer. R//W (output, write Low). The Read/Write signal is Low when the MCU is writing to the external program or data memory. /RESET (input, active Low). To avoid asynchronous and noisy reset problems, the Z86E61/E63 is equipped with a reset filter of four external clocks (4TpC). If the external /RESET signal is less than 4TpC in duration, no reset occurs. On the fifth clock after the /RESET is detected, an internal RST signal is latched and held for an internal register count of 18 external clocks, or for the duration of the external /RESET, whichever is longer. During the reset cycle, /DS is held active Low while /AS cycles at a rate of TpC/2. When /RESET is deactivated, program execution begins at location 000C (HEX). Power-up reset time must be held low for 50 ms, or until VCC is stable, whichever is longer. Port 0 (P07-P00). Port 0 is an 8-bit, nibble programmable, bidirectional, TTL compatible port. These eight I/O lines can be configured under software control as a nibble I/O port, or as an address port for interfacing external memory. When used as an I/O port, Port 0 may be placed under handshake control. In this configuration, Port 3, lines P32 and P35 are used as the handshake control /DAV0 and RDY0 (Data Available and Ready). Handshake signal assignment is dictated by the I/O direction of the upper nibble P07-P04. The lower nibble must have the same direction as the upper nibble to be under handshake control. For external memory references, Port 0 can provide address bits A11-A8 (lower nibble) or A15-A8 (lower and upper nibbles) depending on the required address space. If the address range requires 12 bits or less, the upper nibble of Port 0 can be programmed independently as I/O while the lower nibble is used for addressing. If one or both nibbles are needed for I/O operation, they must be configured by writing to the Port 0 Mode register. In ROMless mode, after a hardware reset, Port 0 lines are defined as address lines A15-A8, and extended timing is set to accommodate slow memory access. The initialization routine can include reconfiguration to eliminate this extended timing mode (Figure 8). Port 1 (P17-P10). Port 1 is an 8-bit, byte programmable, bidirectional, TTL compatible port. It has multiplexed Address (A7-A0) and Data (D7-D0) ports. For Z86E61/E63, these eight I/O lines can be programmed as input or output lines or are configured under software control as an address/data port for interfacing external memory. When used as an I/O port, Port 1 can be placed under handshake control. In this configuration, Port 3 lines, P33 and P34, are used as the handshake controls RDY1 and /DAV1. Memory locations greater than 16384 (E61) or 32768 (E63) are referenced through Port 1. To interface external memory, Port 1 must be programmed for the multiplexed Address/ Data mode. If more than 256 external locations are required, Port 0 must output the additional lines. Port 1 can be placed in high-impedance state along with Port 0, /AS, /DS, and R//W, allowing the MCU to share common resources in multiprocessor and DMA applications. Data transfers are controlled by assigning P33 as a Bus Acknowledge input, and P34 as a Bus Request output (Figure 9). 7 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM PIN FUNCTIONS (Continued) 4 Port 0 (I/O) Z86E61 /E63 MCU 4 Handshake Controls /DAV0 and RDY0 (P32 and P35) OEN PAD Out TTL Level Shifter In Auto Latch R 500 k Figure 6. Port 0 Configuration 8 PRELIMINARY WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM 8 Z86E61 /E63 MCU Port 1 (AD7-AD0) Handshake Controls /DAV1 and RDY1 (P33 and P34) OEN PAD Out TTL Level Shifter In Auto Latch R 500 k Figure 7. Port 1 Configuration 9 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM PIN FUNCTIONS (Continued) Port 2 (P27-P20). Port 2 is an 8-bit, bit programmable, bidirectional, CMOS compatible port. Each of these eight I/O lines can be independently programmed as an input or output, or globally as an open-drain output. Port 2 is always available for I/O operation. When used as an I/O port, Port 2 can be placed under handshake control. In this configuration, Port 3 lines P31 and P36 are used as the handshake control lines /DAV2 and RDY2. The handshake signal assignment for Port 3 lines, P31 and P36, is dictated by the direction (input or output) assigned to P27 (Figure 8 and Table 5). Z86E61 /E63 MCU Port 2 (I/O) Handshake Controls /DAV2 and RDY2 (P31 and P36) Open-Drain OEN PAD Out TTL Level Shifter In Auto Latch R 500 k Figure 8. Port 2 Configuration 10 PRELIMINARY Port 3 (P37-P30). Port 3 is an 8-bit, CMOS compatible fourfixed input and four-fixed output port. These eight I/O lines have four-fixed (P33-P30) input and four-fixed (P37-P34) WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM output ports. Port 3, when used as serial I/O, is programmed as serial in and serial out, respectively (Figure 9). Z86E61 /E63 MCU Port 3 (I/O or Control) Figure 9. Port 3 Configuration Port 3 is configured under software control to provide the following control functions: handshake for Ports 0 and 2 (/DAV and RDY); four external interrupt request signals (IRQ3-IRQ0); timer input and output signals (TIN and TOUT), Data Memory Select (/DM) and EPROM control signals (P30 = /CE, P31 = /OE, P32 = EPM and P33 = VPP ). Table 5. Port 3 Pin Assignments Pin P30 P31 P32 P33 P34 P35 P36 P37 T0 T1 I/O IN IN IN IN OUT OUT OUT OUT CTC1 TIN Int. IRQ3 IRQ2 IRQ0 IRQ1 P0 HS P1 HS P2 HS D/R D/R D/R R/D R/D TOUT IRQ4 IRQ5 R/D Serial Out DM UART Serial In Ext EPROM /CE /OE EPM VPP Notes: HS = Handshake Signals D = Data Available R = Ready 11 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM UART OPERATION Port 3 lines, P37 and P30, are programmed as serial I/O lines for full-duplex serial asynchronous receiver/transmitter operation. The bit rate is controlled by Counter/ Timer0. The Z86E61/E63 automatically adds a start bit and two stop bits to transmitted data (Figure 10). Odd parity is also available as an option. Eight data bits are always transmitted, regardless of parity selection. If parity is enabled, the eighth bit is the odd parity bit. An interrupt request (IRQ4) is generated on all transmitted characters. Received data must have a start bit, eight data bits, and at least one stop bit. If parity is on, bit 7 of the received data is replaced by a parity error flag. Received characters generate the IRQ3 interrupt request. Transmitted Data (No Parity) SP SP D7 D6 D5 D4 D3 D2 D1 D0 ST Start Bit Eight Data Bits Two Stop Bits Received Data (No Parity) SP D7 D6 D5 D4 D3 D2 D1 D0 ST Start Bit Eight Data Bits One Stop Bit Transmitted Data (With Parity) SP SP P D6 D5 D4 D3 D2 D1 D0 ST Start Bit Seven Data Bits Odd Parity Two Stop Bits Received Data (With Parity) SP P D6 D5 D4 D3 D2 D1 D0 ST Start Bit Seven Data Bits Parity Error Flag One Stop Bit Figure 10. Serial Data Formats Auto Latch. The Auto Latch puts valid CMOS levels on all CMOS inputs that are not externally driven. This reduces excessive supply current flow in the input buffer when it is not driven by any source. Note: P33-P30 inputs differ from the Z86C61/C63 in that there is no clamping diode to VCC because of the EPROM high voltage detection circuits. Exceeding the VIH maximum specification during standard operating mode may cause the device to enter EPROM mode ADDRESS SPACE Program Memory. The Z86E61/E63 can address 48 Kbytes (E61) or 32 Kbytes (E63) of external program memory (Figure 11). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond to the six available interrupts. For EPROM mode, byte 13 to byte 16383 (E61) or 32767 (E63) consists of on-chip EPROM. At addresses 16384 (E61) or 32768 (E63) and above, the Z86E61/E63 executes external program memory fetches. In ROMless mode, the Z86E61/E63 can address up to 64 Kbytes of program memory. Program execution begins at external location 000C (HEX) after a reset. 12 PRELIMINARY 65535 16384 (E61) 32768 (E63) 16383 (E61) 32767 (E63) External ROM and RAM WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM On-Chip PROM access registers directly or indirectly through an 8-bit address field. The Z86E61/E63 also allows short 4-bit register addressing using the Register Pointer (Figure 14). In the 4-bit mode, the Register File is divided into 16 working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working register group. Stack. The Z86E61/E63 has a 16-bit Stack Pointer (R255R254) used for external stacks that reside anywhere in the data memory for the ROMless mode, but only from 16384 (E61) or 32768 (E63) to 65535 in the EPROM mode. An 8-bit Stack Pointer (R255) is used for the internal stack that resides within the 236 general-purpose registers (R239R4). The high byte of the Stack Pointer (SPH Bits 15-8) can be use as a general purpose register when using internal stack only. 65535 Location of First Byte of Instruction Executed After RESET 12 11 10 9 8 IRQ5 IRQ5 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQ0 IRQ0 Interrupt Vector (Lower Byte) 7 6 5 Interrupt Vector (Upper Byte) 4 3 2 1 0 Figure 11. Program Memory Configuration External Data Memory Data Memory (/DM). The EPROM version can address up to 48 Kbytes (E61) or 32 Kbytes (E63) of external data memory space beginning at location 16384 (E61) or 32768 (E63). The ROMless version can address up to 64 Kbytes of external data memory. External data memory may be included with, or separated from, the external program memory space. /DM, an optional I/O function that can be programmed to appear on pin P34, is used to distinguish between data and program memory space (Figure 12). The state of the /DM signal is controlled by the type instruction being executed. An LDC opcode references PROGRAM (/DM inactive) memory, and an LDE instruction references DATA (/DM active Low) memory. Register File. The register file consists of four I/O port registers, 236 general-purpose registers, and 16 control and status registers (Figure 13). The instructions can 32768 (E63) 16384 (E61) 16383 (E61) 32767 (E63) Not Addressable 0 Figure 12. Data Memory Configuration 13 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM ADDRESS SPACE (Continued) LOCATION R255 R254 R253 R252 R251 R250 R249 R248 R247 R246 R245 R244 R243 R242 R241 R240 R239 General-Purpose Registers 00 IDENTIFIERS Stack Pointer (Bits 7-0) Stack Pointer (Bits 15-8) Register Pointer Program Control Flags Interrupt Mask Register Interrupt Request Register Interrupt Priority Register Ports 0-1 Mode Port 3 Mode Port 2 Mode T0 Prescaler Timer/Counter0 T1 Prescaler Timer/Counter1 Timer Mode Serial I/O SPL SPH RP FLAGS IMR FF r7 r6 r5 r4 r3 r2 r1 r0 R253 (Register Pointer) The upper nibble of the register file address provided by the register pointer specifies the active working-register group. IRQ F0 Register Group F * * * * * * * * R15 to R0 IPR P01M P3M P2M PRE0 T0 PRE1 T1 TMR SIO * * * * * * 2F 20 1F Specified Working Register Group The lower nibble of the register file address provided by the instruction points to the specified register. Register Group 1 10 0F R15 to R0 R15 to R4 R3 to R0 Register Group 0 I/O Ports R4 R3 R2 R1 R0 Port 3 Port 2 Port 1 Port 0 P3 P2 P1 P0 Figure 14. Register Pointer Figure 13. Register File 14 PRELIMINARY WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM FUNCTIONAL DESCRIPTION Counter/Timers. There are two 8-bit programmable counter/timers (T0-T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler is driven by internal or external clock sources; however, the T0 prescaler is driven by the internal clock only (Figure 15). The 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. When both the counters and prescalers reach the end of the count, a timer interrupt request, IRQ4 (T0) or IRQ5 (T1), is generated. The counter is programmed to start, stop, restart to continue, or restart from the initial value. The counters can also be programmed to stop upon reaching zero (single pass mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode). The counter, but not the prescalers, are read at any time without disturbing their value or count mode. The clock source for T1 is user-definable and is either the internal microprocessor clock divided-by-four, or an external signal input through Port 3. The Timer Mode register configures the external timer input (P31) as an external clock, a trigger input that can be retriggerable or non-retriggerable, or as a gate input for the internal clock. Port 3 line P36 also serves as a timer output (TOUT) through which T0, T1, or the internal clock can be output. The counter/timers are cascaded by connecting the T0 output to the input of T1. Internal Data Bus Write OSC PRE0 Initial Value Register Write T0 Initial Value Register Read T0 Current Value Register /2 6-Bit Down Counter 8-bit Down Counter /4 Internal Clock IRQ4 Serial I/O Clock /2 TOUT P36 External Clock Clock Logic /4 6-Bit Down Counter 8-Bit Down Counter IRQ5 Internal Clock Gated Clock Triggered Clock PRE1 Initial Value Register Write Write T1 Initial Value Register Read T1 Current Value Register Tin P31 Internal Data Bus Figure 15. Counter/Timers Block Diagram 15 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM FUNCTIONAL DESCRIPTION (Continued) Interrupts. The Z86E61/E63 has six different interrupts from eight different sources. The interrupts are maskable and prioritized. The eight sources are divided as follows: four sources are claimed by Port 3 lines P33-P30, one in Serial Out, one in Serial In, and two in the counter/timers (Figure 16). The Interrupt Mask Register globally or individually enables or disables the six interrupt requests. When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority register (refer to Table 5). All Z86E61/E63 interrupts are vectored through locations in the program memory. When an interrupt machine cycle is activated, an interrupt request is granted. Thus, this disables all of the subsequent interrupts, saves the Program Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked and the Interrupt Request register is polled to determine which of the interrupt requests need service. Software initialized interrupts are supported by setting the appropriate bit in the Interrupt Request Register (IRQ). Internal interrupt requests are sampled on the falling edge of the last cycle of every instruction, and the interrupt request must be valid 5TpC before the falling edge of the last clock cycle of the currently executing instruction. For the ROMless mode, when the device samples a valid interrupt request, the next 48 (external) clock cycles are used to prioritize the interrupt, and push the two PC bytes and the FLAG register on the stack. The following nine cycles are used to fetch the interrupt vector from external memory. The first byte of the interrupt service routine is fetched beginning on the 58th TpC cycle following the internal sample point, which corresponds to the 63rd TpC cycle following the external interrupt sample point. IRQ0 - IRQ5 IRQ IMR 6 Global Interrupt Enable IPR Interrupt Request PRIORITY LOGIC Vector Select Figure 16. Interrupt Block Diagram 16 PRELIMINARY Clock. The Z86E61/E63 on-chip oscillator has a high gain, parallel resonant amplifier for connection to a crystal, LC, ceramic resonator, or any suitable external clock source (XTAL1 = Input, XTAL2 = Output). The crystal should be AT cut, 1 MHz to 16 MHz max; series resistance WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM (RS) is less than or equal to 100 Ohms. The crystal should be connected across XTAL1 and XTAL2 using the recommended capacitors (10 pF < CL < 100 pF) from each pin to ground (Figure 17). Note: Actual capacitor value specified by crystal manufacturer. XTAL1 C1 Pin 11 XTAL2 C2 Pin 11 Ceramic Resonator or Crystal C2 Pin 11 LC Clock C1 Pin 11 L XTAL1 XTAL1 XTAL2 XTAL2 External Clock Figure 17. Oscillator Configuration HALT. Turns off the internal CPU clock but not the XTAL oscillation. The counter/timers and external interrupts IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The devices are recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt service routine, the program continues from the instruction after the HALT. STOP. This instruction turns off the internal clock and external crystal oscillation, and reduces the standby current to 5 A (typical) or less. The STOP mode is terminated by a reset, which causes the processor to restart the application program at address 000C (HEX). In order to enter STOP (or HALT) mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user must execute a NOP (opcode = OFFH) immediately before the appropriate SLEEP instruction. i.e., FF NOP 6F STOP or FF NOP 7F HALT ; clear the pipeline ; enter STOP mode ; clear the pipeline ; enter HALT mode PROGRAMMING Z86E61/E63 User Modes The Z86E61/E63 uses separate AC timing cycles for the different User Modes available. Table 6 shows the Z86E61/ E63 User Modes. Table 7 shows the timing of the programming waveforms. User MODE 1 EPROM Read The Z86E61/E63 EPROM read cycle is provided so that the user may read the Z86E61/E63 as a standard 27128 (E61) or 27256 (E63) EPROM. This is accomplished by driving the /EPM pin (P32) to VH and activating /CE and /OE. /PGM remains inactive. This mode is not valid after execution of an EPROM protect cycle. Timing for the EPROM read cycle is shown in Figure 18. User MODE 2 EPROM Program The Z86E61/E63 Program function conforms to the Intelligent programming algorithm. The device is programmed with VCC at 6.0V and VPP = 12.5V. Programming pulses are applied in 1 ms increments to a maximum of 25 pulses before proper verification. After verification, a programming pulse of three times the duration of the cycles necessary to program the device is issued to ensure proper programming. After all addresses are programmed, a final data comparison is executed and the programming cycle is complete. Timing for the Z86E61/E63 programming cycle is shown in Figure 18. 17 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM PROGRAMMING (Continued) User Mode 3: PROM Verify The Program Verify cycle is used as part of the intelligent programming algorithm to insure data integrity under worst-case conditions. It differs from the EPROM Read cycle in that VPP is active and VCC must be driven to 6.0V. Timing is shown in Figure 18. User Modes 4 and 5: EPROM and RAM Protect To extend program security, EPROM and RAM protect cycles are provided for the Z86E61/E63. Execution of the EPROM protect cycle prohibits proper execution of the EPROM Read, EPROM Verify, and EPROM programming cycles. Execution of the RAM protect cycle disables accesses to the upper 128 bytes of register memory (excluding mode and configuration registers), but first the user's program must set bit 6 of the IMR (R251). Timing is shown in Figures 20 and 21. User Modes. Table 6 shows the programming voltage of each mode of the Z86E61/E63. Table 6. OTP Programming Table User/Test Mode Device Pin No. User Modes EPROM Read Program Program Verify EPROM Protect RAM Protect P33 VPP V IH VPP VPP VPP VPP P32 EPM VH X X VH X Device Pins P30 P31 /CE /OE VIL VIL VIL VH VH VIL V IH VIL V IH V IH P20 /PGM V IH VIL V IH VIL VIL Port 1 CNFG Data Out In Out XX XX ADDR Addr Addr Addr XX XX VCC 5.0V 6.0V 6.0V 6.0V 6.0V Notes: VPP = 12.0V 0.5V VH = 12.0V 0.5V VIH = 5V VIL = 0V XX = Irrelevant IPP during programming = 40 mA maximum. ICC during programming, verify, or read = 40 mA maximum. Z86E63 Signal Description for EPROM Program/Read The following signals are required to correctly program or read the Z86E63 device. ADDR. The address must remain stable throughout the program read cycle. DATA. The I/O data bus must be stable during programming (/OE High, /PGM Low, VPP High). During read the data bus outputs data. XCLK. A clock is required to clock the /RESET signal into the registers before programming. A constant clock can be applied, or the XCLK input can be toggled a minimum of 12 cycles before any programming or verify function begins. The maximum clock frequency to be applied when in the EPROM mode is 12 MHz. /RESET. The reset input can be held to a constant Low or High value throughout normal programming. It must be held High to program the EPROM protect option bit. Also, any time the /RESET input changes state the XCLK must be clocked a minimum of 12 times to clock the /RESET through the reset filter. /OE. When the device is placed in EPROM mode, the /OE input also serves as the precharge for the sense amp. The precharge signal should be Low for the first half of the stable address and High for the second half. The PRECHG signal is inverted from the /OE signal so the /OE should be High on the first half and Low on the second half, or stable address. The EPROM output data should be sampled during the second half of stable address. The access time of the EPROM is defined in later sections. This two part calculation of access time is required because this is a precharged sense amp with a precharge clock. 18 PRELIMINARY Table 7. Timing of Programming Waveforms Parameters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name Address Setup Time Data Setup Time V PP Setup V CC Setup Time Chip Enable Setup Time Program Pulse Width Data Hold Time /OE Setup Time Data Access Time Data Output Float Time Overprogram Pulse Width EPM Setup Time /PGM Setup Time Address to /OE Setup Time Option Program Pulse Width Min 2 2 2 2 2 0.95 2 2 200 100 2.85 2 2 2 78 Max WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM Units s s s s s ms s s ns ns ms s s s ms VIH Address VIL VIH Data VIL VH VPP VIL VH EPM VIL 12 0 Min Address Stable Address Stable Invalid 9 Valid Invalid Valid 5.5V VCC 4.5V VIH /CE VIL VIH 0 Min /OE VIL VIH 16 16 /PGM VIL 3 Figure 18. EPROM Read 19 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM PROGRAMMING (Continued) VIH Address VIL VIH Data VIL 1 Address Stable Data Stable 2 9 Data Out Valid 10 VH VPP VIH 3 VH EPM VIL 6V VCC 4.5V VIH /CE VIL 5 4 7 VIH /OE VIL VIH /PGM VIL 6 11 Program Cycle Verify Cycle 8 16 Figure 19. EPROM Program and Verify 20 PRELIMINARY WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM VIH Address VIL VIH Data VIL VH VPP VIH 3 Address 003 6V VCC 4.5V 4 VH /CE VIH /OE VH VIH VH EPM VIH VIL 12 5 14 VIH 12 VIH /PGM VIL 15 15 ROM Protect Programming RAM Protect Programming Figure 20. Programming EPROM, RAM Protect and 4K Size Selection 21 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM PROGRAMMING (Continued) VIH Address VIL VIH Data VIL VH VPP VIH 3 Address 008 6V VCC 4.5V 4 VH /CE VIH /OE VH VIH VH EPM VIH VIL 12 5 14 VIH 12 VIH /PGM VIL 15 15 ROM Protect Programming RAM Protect Programming Figure 21. Programming EPROM, RAM Protect and 16K Size Selection 22 PRELIMINARY WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM Start Addr = First Location Vcc = 6.0V Vpp = 12.5V N=0 Program 1 ms Pulse Increment N Yes N = 25 ? No Fail Verify One Byte Pass Prog. One Pulse 3xN ms Duration Fail Verify Byte Pass Increment Address No Last Addr ? Yes Vcc = Vpp = 4.5V Verify All Bytes Pass Vcc = Vpp = 5.5V Fail Device Failed Verify All Bytes Pass Device Passed Fail Figure 22. Intelligent Programming Flowchart 23 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM ABSOLUTE MAXIMUM RATINGS Symbol VCC TSTG TA Description Supply Voltage* Storage Temp Oper Ambient Temp Min -0.3 -65 Max + 7.0 +150 Units V C C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. Notes: * Voltages on all pins with respect to GND. See Ordering Information STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Figure 23). From Output Under T est I 150 pF Figure 23. Test Load Diagram 24 PRELIMINARY WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM DC CHARACTERISTICS TA = 0C to +70C Min Max 7 13 VCC+ 0.3 0.8 VCC+ 0.3 0.8 0.4 3.8 -0.3 -10 -10 VCC+ 0.3 0.8 10 10 -50 50 60 15 20 20 20 25 35 5 10 5 5 Typical @ 25C Sym Parameter Max Input Voltage Max Input Voltage Clock Input High Voltage Clock Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Reset Input High Voltage Reset Input Low Voltage Input Leakage Output Leakage Reset Input Current Supply Current Standby Current Standby Current Units V V V V V V V V V V A A A mA mA mA mA A A Conditions IIN 250 A P33-P30 Only Driven by External Clock Generator Driven by External Clock Generator V CH V CL V IH V IL V OH V OL V RH V Rl IIL IOL IIR ICC ICC1 ICC2 3.8 -0.3 2.0 -0.3 2.4 IOH = -2.0 mA IOL = +2.0 mA 0V VIN + 5.25V 0V VIN + 5.25V V CC= + 5.25V, VRL = 0V @ 16 MHz @ 20 MHz HALT Mode VIN = 0V, VCC @ 16 MHz HALT Mode V IN = 0V, VCC @ 20 MHz STOP Mode VIN = 0V, VCC @ 16 MHz STOP Mode VIN = 0V, VCC @ 20 MHz Notes: I CC2 requires loading TMR (%F1H) with any value prior to STOP execution. Use this sequence: LD TMR,#00 NOP STOP 25 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM AC CHARACTERISTICS External I/O or Memory Read or Write Timing Diagram R//W 13 12 Port 0, /DM 16 18 3 Port 1 1 A7 - A0 2 D7 - D0 IN 9 /AS 8 4 5 6 11 /DS (Read) 17 10 Port 1 A7 - A0 14 D7 - D0 OUT 15 7 /DS (Write) 17 Figure 24. External I/O or Memory Read/Write Timing 26 PRELIMINARY WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM AC CHARACTERISTICS External I/O or Memory Read and Write Timing Table TA = 0C to +70C 16 MHz 20 MHz Min Max Min Max 20 30 180 35 0 135 80 75 0 35 30 20 30 25 30 200 40 30 48 36 0 48 36 32 36 40 40 200 36 0 130 75 100 26 28 160 No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Symbol TdA(AS) TdAS(A) TdAS(DR) TwAS TdAZ(DS) TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TdDM(AS) Parameter Address Valid to /AS Rise Delay /AS Rise to Address Float Delay /AS Rise to Read Data Req'd Valid /AS Low Width Address Float to /DS Fall /DS (Read) Low Width /DS (Write) Low Width /DS Fall to Read Data Req'd Valid Read Data to /DS Rise Hold Time /DS Rise to Address Active Delay /DS Rise to /AS Fall Delay R//W Valid to /AS Rise Delay /DS Rise to R//W Not Valid Write Data Valid to /DS Fall (Write) Delay /DS Rise to Write Data Not Valid Delay Address Valid to Read Data Req'd Valid /AS Rise to /DS Fall Delay /DM Valid to /AS Fall Delay Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes [2,3] [2,3] [1,2,3] [2,3] [1,2,3] [1,2,3] [1,2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [2,3] [1,2,3] [2,3] [2,3] Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] See clock cycle dependent characteristics table. Standard Test Load All timing references use 2.0 V for a logic 1 and 0.8 V for a logic 0. Clock Dependent Formulas Number 1 2 3 4 6 7 8 10 11 12 13 14 15 16 17 18 Symbol TdA(AS) TdAS(A) TdAS(DR) TwAS TwDSR TwDSW TdDSR(DR) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TdDM(AS) Equation 0.40 TpC + 0.32 0.59 TpC - 3.25 2.83 TpC + 6.14 0.66 TpC - 1.65 2.33 TpC - 10.56 1.27 TpC + 1.67 1.97 TpC - 42.5 0.8 TpC 0.59 TpC - 3.14 0.4 TpC 0.8 TpC - 15 0.4 sTpC 0.88 TpC - 19 4 TpC - 20 0.91 TpC - 10.7 0.9 TpC - 26.3 27 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM AC CHARACTERISTICS Additional Timing Diagram 1 3 Clock 2 7 7 2 3 TIN 4 6 5 IRQN 8 9 Figure 25. Additional Timing AC CHARACTERISTICS Additional Timing Table TA = 0C to +70C 16 MHz 20 MHz Min Max Min Max 62.5 21 50 5TpC 8TpC 100 70 5TpC 5TpC 1000 10 50 37 75 5TpC 8TpC 100 50 5TpC 5TpC 1000 15 No 1 2 3 4 5 6 7 8A 8B 9 Symbol TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin,TfTin TwIL TwIL TwIH Parameter Input Clock Period Clock Input Rise & Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise & Fall Times Interrupt Request Input Low Times Interrupt Request Input Low Times Interrupt Request Input High Times Units ns ns ns ns Notes [1] [1] [1] [2] [2] [2] [2] [2,4] [2,5] [2,3] ns ns Notes: [1] Clock timing references use 3.8V for a logic 1 and 0.8V for a logic 0. [2] Timing references use 2.0V for a logic 1 and 0.8V for a logic 0. [3] Interrupt references request through Port 3. [4] Interrupt request through Port 3 (P33-P31). [5] Interrupt request through Port 30. 28 PRELIMINARY WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM AC CHARACTERISTICS Handshake Timing Diagrams Data In Data In Valid Next Data In Valid 1 3 2 /DAV (Input) 4 Delayed DAV 5 6 RDY (Output) Delayed RDY Figure 26. Input Handshake Timing Data Out Data Out Valid Next Data Out Valid 7 /DAV (Output) 8 10 9 Delayed DAV 11 RDY (Input) Delayed RDY Figure 27. Output Handshake Timing 29 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM AC CHARACTERISTICS Handshake Timing Table TA = 0C to +70C 16 MHz 20 MHz Min Max Min Max 0 145 110 115 115 0 TpC 0 115 110 115 110 115 0 115 0 TpC 0 145 110 115 115 No 1 2 3 4 5 6 7 8 9 10 11 Symbol TsDI(DAV) ThDI(DAV) TwDAV TdDAVI(RDY) TdDAVId(RDY) TdRDY0(DAV) TdD0(DAV) TdDAV0(RDY) TdRDY0(DAV) TwRDY TdRDY0d(DAV) Parameter Data In Setup Time Data In Hold Time Data Available Width DAV Fall to RDY Fall Delay DAV Rise to RDY Rise Delay RDY Rise to DAV Fall Delay Data Out to DAV Fall Delay DAV Fall to RDY Fall Delay RDY Fall to DAV Rise Delay RDY Width RDY Rise to DAV Fall Delay Data Direction IN IN IN IN IN IN OUT OUT OUT OUT OUT 30 PRELIMINARY WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM Z8 CONTROL REGISTER DIAGRAMS R240 SIO D7 D6 D5 D4 D3 D2 D1 D0 R243 PRE1 D7 D6 D5 D4 D3 D2 D1 D0 Serial Data (D0 = LSB) Count Mode 0 T1 Single Pass 1 T1 Modulo N Clock Source 1 T1 Internal 0 T1 External Timing Input (TIN) Mode Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) Figure 28. Serial I/O Register (F0H: Read/Write) R241 TMR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 No Function Load T0 Disable T0 Count Enable T0 Count No Function Load T1 Disable T1 Count Enable T1 Count Figure 31. Prescaler 1 Register (F3H: Write Only) R244 T0 D7 D6 D5 D4 D3 D2 D1 D0 TIN Modes 00 External Clock Input 01 Gate Input 10 Trigger Input (Non-retriggerable) 11 Trigger Input (Retriggerable) TOUT Modes 00 Not Used 01 T0 Out 10 T1 Out 11 Internal Clock Out T0 Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) T0 Current Value (When Read) Figure 32. Counter/Timer 0 Register (F4H: Read/Write) R245 PRE0 Figure 29. Timer Mode Register (F1H: Read/Write) R242 T1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Count Mode 0 T0 Single Pass 1 T0 Modulo N Reserved (Must be 0) Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) T1 Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) T1 Current Value (When Read) Figure 33. Prescaler 0 Register (F5H: Write Only) Figure 30. Counter/Timer 1 Register (F2H: Read/Write) 31 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM Z8 CONTROL REGISTER DIAGRAMS (Continued) R246 P2M D7 D6 D5 D4 D3 D2 D1 D0 R248 P01M D7 D6 D5 D4 D3 D2 D1 D0 P20 - P27 I/O Definition 0 Defines Bit as Output 1 Defines Bit as Input P00 - P00 Mode 00 Output 01 Input 1X A11 - A8 Stack Selection 0 External 1 Internal P17 - P10 Mode 00 Byte Output 01 Byte Input 10 AD7 - AD0 11 High-Impedance AD7 - DA0, /AS, /DS, /R//W, A11 - A8, A15 - A12, If Selected Reserved (Must be 0) Figure 34. Port 2 Mode Register (F6H: Write Only) R247 P3M D7 D6 D5 D4 D3 D2 D1 D0 0 Port 2 Pull-Ups Open Drain 1 Port 2 Pull-Ups Active Reserved (Must be 0) 0 P32 = Input P35 = Output 1 P32 = /DAV0/RDY0 P35 = RDY0//DAV0 P33 = Input P34 = Output 01 P33 = Input 10 P34 = /DM 11 P33 = /DAV1/RDY1 P34 = RDY1//DAV1 R249 IPR P07 - P04 Mode 00 Output 01 Input 1X A 15 - A12 00 Figure 36. Port 0 and 1 Mode Register (F8H: Write Only) 0 P31 = Input (TIN) P36 = Output (TOUT) 1 P31 = /DAV2/RDY2 P36 = RDY2//DAV2 0 1 P30 = Input P37 = Output P30 = Serial In P37 = Serial Out D7 D6 D5 D4 D3 D2 D1 D0 0 Parity Off 1 Parity On Interrupt Group Priority Reserved = 000 C > A > B = 001 A > B > C = 010 A > C > B = 011 B > C > A = 100 C > B > A = 101 B > A > C = 110 Reserved = 111 IRQ1, IRQ4 Priority (Group C) 0 IRQ1 > IRQ4 1 IRQ4 > IRQ1 IRQ0, IRQ2 Priority (Group B) 0 IRQ2 > IRQ0 1 IRQ0 > IRQ2 IRQ3, IRQ5 Priority (Group A) 0 IRQ5 > IRQ3 1 IRQ3 > IRQ5 Reserved (Must be 0) Figure 35. Port 3 Mode Register (F7H: Write Only) Figure 37. Interrupt Priority Register (F9H: Write Only) 32 PRELIMINARY R250 IRQ D7 D6 D5 D4 D3 D2 D1 D0 R253 RP D7 D6 D5 D4 D3 D2 D1 D0 WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM IRQ0 = P32 IRQ1 = P33 IRQ2 = P31 IRQ3 = P30 IRQ4 = T0 IRQ5 = T1 Input (D0 = IRQ0) Input Input Input, Serial Input Serial Output 0 Reserved (Must be 0) r4 r5 r6 r7 Register Pointer Reserved (Must be 0) Figure 38. Interrupt Request Register (FA H: Read/Write) Figure 41. Register Pointer Register (FDH : Read/Write) R251 IMR D7 D6 D5 D4 D3 D2 D1 D0 R254 SPH D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 Enables IRQ5-IRQ0 (D0 = IRQ0) Enables RAM Protect Enables Interrupts Stack Pointer Upper Byte (SP15 - SP8) Figure 39. Interrupt Mask Register (FB H: Read/Write) R255 SPL R252 FLAGS D7 D6 D5 D4 D3 D2 D1 D0 Figure 42. Stack Pointer Register (FE H: Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 User Flag F1 User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag Stack Pointer Lower Byte (SP7 - SP0) Figure 43. Stack Pointer Register (FFH : Read/Write) Figure 40. Flag Register (FC H: Read/Write) 33 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM DC CHARACTERISTICS Supply Current I CC (mA) 40 A B 30 C 20 10 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Legend: A - Vcc = 5.6V B - Vcc = 5.0V C - Vcc = 4.4V Figure 44. Typical ICC vs Frequency 34 PRELIMINARY WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM DC CHARACTERISTICS Standby Current I CC1 (mA) 12 A 10 B C 8 6 4 2 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz) Legend: A - Vcc = 5.6V B - Vcc = 5.0V C - Vcc = 4.4V Figure 45. Typical ICC1 vs Frequency 35 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM INSTRUCTION SET NOTATION Addressing Modes. The following notation is used to describe the addressing modes and instruction operations as shown in the instruction summary. Symbol IRR Irr X DA RA IM R r IR Ir RR Meaning Indirect register pair or indirect working register pair address Indirect working register pair only Indexed address Direct address Relative address Immediate Register or working register address Working register address only Indirect register or indirect working register address Indirect working register address only Register pair or working register pair address Flags. Control register (R252) contains the following six flags: Symbol C Z S V D H Meaning Carry flag Zero flag Sign flag Overflow flag Decimal-adjust flag Half-carry flag Affected flags are indicated by: 0 1 * x Clear to zero Set to one Set to clear according to operation Unaffected Undefined Symbols. The following symbols are used in describing the instruction set. Symbol dst src cc @ SP PC FLAGS RP IMR Meaning Destination location or contents Source location or contents Condition Code Indirect address prefix Stack Pointer Program Counter Flag Register (Control Register 252) Register Pointer (R253) Interrupt Mask Register (R251) 36 PRELIMINARY WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM CONDITION CODES Value 1000 0111 1111 0110 1110 1101 0101 0100 1100 0110 1110 1001 0001 1010 0010 1111 0111 1011 0011 0000 Mnemonic C NC Z NZ PL MI OV NOV EQ NE GE LT GT LE UGE ULT UGT ULE F Meaning Always True Carry No Carry Zero Not Zero Plus Minus Overflow No Overflow Equal Not Equal Greater Than or Equal Less than Greater Than Less Than or Equal Unsigned Greater Than or Equal Unsigned Less Than Unsigned Greater Than Unsigned Less Than or Equal Never True (Always False) Flags Set C=1 C=0 Z=1 Z=0 S=0 S=1 V=1 V=0 Z=1 Z=0 (S XOR V) = 0 (S XOR V) = 1 [Z OR (S XOR V)] = 0 [Z OR (S XOR V)] = 1 C=0 C=1 (C = 0 AND Z = 0) = 1 (C OR Z) = 1 37 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM INSTRUCTION FORMATS OPC CCF, DI, EI, IRET, NOP, RCF, RET, SCF OPC dst One-Byte Instructions OPC MODE OR 1110 dst/src dst/src CLR, CPL, DA, DEC, DECW, INC, INCW, POP, PUSH, RL, RLC, RR, RRC, SRA, SWAP JP, CALL (Indirect) OPC src dst MODE OR OR 1110 1110 src dst ADC, ADD, AND, CP, LD, OR, SBC, SUB, TCM, TM, XOR OPC dst OR 1110 dst OPC dst MODE OR 1110 dst ADC, ADD, AND, CP, LD, OR, SBC, SUB, TCM, TM, XOR OPC VALUE SRP VALUE MODE OPC dst MODE src ADC, ADD, AND, CP, OR, SBC, SUB, TCM, TM, XOR LD, LDE, LDEI, LDC, LDCI MODE dst/src src dst OPC OR OR 1110 1110 src dst LD MODE dst/src OPC src/dst OPC x LD ADDRESS dst/src OPC OR 1110 src LD cc DAU dst OPC LD DAL OPC JP src/dst VALUE OPC dst/CC RA OPC DJNZ, JR DAU DAL CALL FFH 6FH 7FH STOP/HALT Two-Byte Instructions Three-Byte Instructions INSTRUCTION SUMMARY Note: Assignment of a value is indicated by the symbol " ". For example: dst dst + src indicates that the source data is added to the destination data and the result is stored in the destination location. The notation "addr (n)" is used to refer to bit (n) of a given operand location. For example: dst (7) refers to bit 7 of the destination operand. 38 PRELIMINARY WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM INSTRUCTION SUMMARY Address Opcode Mode Byte dst src (Hex) DA IRR 1[ ] 0[ ] 5[ ] D6 D4 Address Opcode Mode Byte dst src (Hex) r R IR INCW dst dstdst + 1 IRET FLAGS@SP; SPSP + 1 PC@SP; SPSP + 2; IMR(7)1 JP cc, dst if cc is true, PCdst JR cc, dst if cc is true, PCPC + dst Range: +127, -128 LD dst, src dstsrc DA IRR RA RR IR rE r=0-F 20 21 A0 A1 BF Instruction and Operation ADC dst, src dstdst + src +C ADD dst, src dstdst + src AND dst, src dstdst AND src CALL dst SPSP - 2 @SPPC, PCdst CCF CNOT C CLR dst dst0 COM dst dstNOT dst CP dst, src dst - src DA dst dstDA dst DEC dst dstdst - 1 DECW dst dstdst - 1 DI IMR(7)0 DJNZr, dst rr - 1 if r 0 PCPC + dst Range: +127, -128 EI IMR(7)1 HALT Flags Affected C Z S V DH TTTT0T Instruction and Operation INC dst dstdst + 1 Flags Affected C Z S V DH TTT-- TTTT0T - TT0 --- - TTT-- - - - T T T T TT EF R IR R IR R IR R IR RR IR B0 B1 60 61 A[ ] 40 41 00 01 80 81 8F RA rA r=0-F T- - - ---- - - cD c=0-F 30 cB c=0-F - - - - -- TT0 - - - - -- TTTT-- TTTX-- - TTT-TTT-- r r R r X r Ir R R R IR IR Im R r X r Ir r R IR IM IM R Irr Irr - - - --- rC r8 r9 r=0-F C7 D7 E3 F3 E4 E5 E6 E7 F5 C2 C3 - - - - -- LDC dst, src dstsrc 9F 7F --LDCI dst, src dstsrc rr + 1; rrrr + 1 r Ir - - - - --- 39 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM INSTRUCTION SUMMARY (Continued) Address Opcode Mode Byte dst src (Hex) FF R IR R IR 4[ ] 50 51 70 71 CF AF Address Mode dst src Opcode Byte (Hex) 6F R IR 7 4 3 0 Instruction and Operation NOP OR dst, src dstdst OR src POP dst dst@SP; SPSP + 1 PUSH src SPSP - 1; @SPsrc RCF C0 RET PC@SP; SPSP + 2 RL dst C 7 0 Flags Affected C Z S V DH ---- Instruction and Operation STOP SUB dst, src dstdstsrc SWAP dst Flags Affected C Z S V DH 1[ [ [ [ -1[ TT0 2[ ] F0 F1 - - - XTTX-- - - - - -TCM dst, src (NOT dst) AND src TM dst, src dst AND src XOR dst, src dstdst XOR src 6[ ] TT0 -- 0- - - --- 7[ ] B[ ] - TT0 --- TT0 R IR R IR 7 0 90 91 10 11 E0 E1 C0 C1 3[ ] DF TTTT-- RLC dst C TTTT-- These instructions have an identical set of addressing modes, which are encoded for brevity. The first opcode nibble is found in the instruction set table above. The second nibble is expressed symbolically by a `[ ]' in this table, and its value is found in the following table to the left of the applicable addressing mode pair. For example, the opcode of an ADC instruction using the addressing modes r (destination) and Ir (source) is 13. RR dst C 7 0 R IR R IR 7 0 TTTT-- RRC dst C TTTT-- Address Mode dst src r r Ir R IR IM Lower Opcode Nibble [2] [3] [4] [5] [6] SBC dst, src dstdstsrcC SCF C1 SRA dst C 7 0 TTTT1T r R R 1- - - --- R IR D0 D1 TTT0 R IR Im 31 --- IM [7] SRP dst RPsrc 40 PRELIMINARY WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM OPCODE MAP Lower Nibble (Hex) 0 0 6.5 DEC R1 6.5 RLC R1 6.5 INC R1 8.0 JP IRR1 8.5 DA R1 10.5 POP R1 6.5 COM R1 10/12.1 PUSH R2 10.5 DECW RR1 6.5 RL R1 10.5 INCW RR1 6.5 CLR R1 6.5 RRC R1 6.5 SRA R1 6.5 RR R1 8.5 SWAP R1 1 6.5 DEC IR1 6.5 RLC IR1 6.5 INC IR1 6.1 SRP IM 8.5 DA IR1 10.5 POP IR1 6.5 COM IR1 12/14.1 PUSH IR2 10.5 DECW IR1 6.5 RL IR1 10.5 INCW IR1 6.5 CLR IR1 6.5 RRC IR1 6.5 SRA IR1 6.5 RR IR1 8.5 SWAP IR1 2 2 6.5 ADD r1, r2 6.5 ADC r1, r2 6.5 SUB r1, r2 6.5 SBC r1, r2 6.5 OR r1, r2 6.5 AND r1, r2 6.5 TCM r1, r2 6.5 TM r1, r2 12.0 LDE r1, Irr2 12.0 LDE r2, Irr1 6.5 CP r1, r2 6.5 XOR r1, r2 12.0 LDC r1, Irr2 12.0 LDC r1, Irr2 3 6.5 ADD r1, Ir2 6.5 ADC r1, Ir2 6.5 SUB r1, Ir2 6.5 SBC r1, Ir2 6.5 OR r1, Ir2 6.5 AND r1, Ir2 6.5 TCM r1, Ir2 6.5 TM r1, Ir2 18.0 LDEI Ir1, Irr2 18.0 LDEI Ir2, Irr1 6.5 CP r1, Ir2 6.5 XOR r1, Ir2 18.0 LDCI Ir1, Irr2 18.0 LDCI Ir1, Irr2 6.5 LD r1, IR2 6.5 LD Ir1, r2 4 10.5 ADD R2, R1 10.5 ADC R2, R1 10.5 SUB R2, R1 10.5 SBC R2, R1 10.5 OR R2, R1 10.5 AND R2, R1 10.5 TCM R2, R1 10.5 TM R2, R1 5 10.5 ADD IR2, R1 10.5 ADC IR2, R1 10.5 SUB IR2, R1 10.5 SBC IR2, R1 10.5 OR IR2, R1 10.5 AND IR2, R1 10.5 TCM IR2, R1 10.5 TM IR2, R1 6 10.5 ADD R1, IM 10.5 ADC R1, IM 10.5 SUB R1, IM 10.5 SBC R1, IM 10.5 OR R1, IM 10.5 AND R1, IM 10.5 TCM R1, IM 10.5 TM R1, IM 7 8 9 A B C D 12.10.0 JP cc, DA E 6.5 INC r1 F 1 2 3 4 5 6 Upper Nibble (Hex) 7 6.5 10.5 LD ADD IR1, IM r1, R2 10.5 ADC IR1, IM 10.5 SUB IR1, IM 10.5 SBC IR1, IM 10.5 OR IR1, IM 10.5 AND IR1, IM 10.5 TCM IR1, IM 10.5 TM IR1, IM 12/10.5 12/10.0 6.5 6.5 LD JR DJNZ LD r2, R1 r1, RA cc, RA r1, IM 6.0 STOP 7.0 HALT 6.1 DI 6.1 EI 8 9 A B C D E F 10.5 10.5 10.5 10.5 CP CP CP CP R2, R1 IR2, R1 R1, IM IR1, IM 10.5 10.5 10.5 10.5 XOR XOR XOR XOR R2, R1 IR2, R1 R1, IM IR1, IM 10.5 LD r1,x,R2 10.5 20.0 20.0 LD CALL CALL* r2,x,R1 DA IRR1 10.5 10.5 10.5 10.5 LD LD LD LD R2, R1 IR2, R1 R1, IM IR1, IM 10.5 LD R2, IR1 3 2 3 1 14.0 RET 16.0 IRET 6.5 RCF 6.5 SCF 6.5 CCF 6.0 NOP Bytes per Instruction Lower Opcode Nibble Pipeline Cycles 4 Execution Cycles Upper Opcode Nibble Legend: R = 8-bit Address r = 4-bit Address R1 or r1 = Dst Address R2 or r2 = Src Address Sequence: Opcode, First Operand, Second Operand Note: Blank areas not defined. *2-byte instruction appears as a 3-byte instruction A 10.5 CP R1, R2 Mnemonic First Operand Second Operand 41 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM PACKAGE INFORMATION 40-Pin DIP Package Diagram 44-Pin PLCC Package Diagram 42 PRELIMINARY WITH Z86E61/E63 Z8(R) MCU 16K/32K EPROM 44-Pin QFP Package Diagram 43 PRELIMINARY WITH 16K/32K Z86E61/E63 Z8(R) MCU EPROM ORDERING INFORMATION Z86E61 16 MHz 40-Pin DIP Z86E6116PSC 44-Pin QFP Z86E6116FEC 44-Pin PLCC Z86E6116VSC 20 MHz 40-Pin DIP Z86E6120PSC 44-Pin PLCC Z86E6120VSC Z86E63 16 MHz 40-Pin DIP Z86E6316PSC 44-Pin PLCC Z86E6316VSC 20 MHz 40-Pin DIP Z86E6320PSC 44-Pin PLCC Z86E6320VSC For fast results, contact your local Zilog sales office for assistance in ordering the part desired. CODES Preferred Package P = Plastic DIP V = Plastic Chip Carrier Temperature S = 0C to +70C Speeds 12 = 16 MHz 16 = 20 MHz Environmental C = Plastic Standard Example: Z 86E61 16 P S C is an Z86E61, 16 MHz, DIP 0C to +70C, Plastic Standard Flow , Environmental Flow T emperature Package Speed Product Number Zilog Prefix 44 |
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