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PRELIMINARY PRODUCT SPECIFICATION
1
Z86L79/L80
LOW-VOLTAGE MICROCONTROLLER
FEATURES
Part Z86L79 Z86L80 ROM (KB) 4 8 RAM* (Bytes) 237 237
s
1
Five Priority Interrupts Low Voltage Detection and Standby Mode Watch-Dog/Power-On Reset Circuits Two Independent Comparators with Programmable Interrupt Polarity On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock Drive Mask Selectable 200 kOhm Pull-Ups on Ports 0, 2, 3 - All Eight Port 2 Bits at One Time or Not - Pull-Ups Automatically Disabled Upon Selecting Individual Pins as Outputs. Maskable SingleTrip Point Inputs on P00 Through P03. Permanently Enabled WDT Option (Maskable) 28-Pin DIP and SOIC Packages
I/O 24 24
Voltage Range 2.0V to 3.9V 2.0V to 3.9V
s s s
Note: *General-Purpose s
Three Standby Modes (Typical) - STOP - 2 A - HALT - 0.8 mA - Low Voltage Standby (s
s
s s
s s s
GENERAL DESCRIPTION
The Z86L79/L80 family of IR (InfraRed) Controllers are ROM-based members of the Z8(R) MCU single-chip microcontroller family with 237 bytes of general-purpose RAM. The only differentiating factor between these two versions is the availability of ROM. Zilog's CMOS microcontrollers offer fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, automated pulse generation/reception, and easy hardware/software system expansion along with cost-effective and low power consumption. The Z86L7X architecture is based on Zilog's 8-bit microcontroller core with an Expanded Register File to allow access to register mapped peripherals, I/O circuits, and powerful counter/timer circuitry. The Z8(R) MCU offers a flexible I/O scheme, an efficient register and address space structure, and a number of ancillary features that are useful in many consumer, automotive, computer peripheral, and battery operated hand-held applications.
DS97LVO0601
PRELIMINARY
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Z86L79/80 Low-Voltage Microcontroller
Zilog
GENERAL DESCRIPTION (Continued)
Z8(R) applications demand powerful I/O capabilities. The Z86L79/80 fulfills this with two package options with 24 pins of dedicated input and output. These lines are grouped into three ports. Each port consists of eight lines and is configurable under software control to provide timing, status signals, and parallel I/O. There are three basic address spaces available to support a wide range of configurations: Program Memory, Register File, and Expanded Register File. The Register File is composed of 256 bytes of RAM. It includes four I/O port registers, ten control and status registers, and the rest are general purpose registers. The Expanded Register File consists of three register groups. To unburden the program from coping with such real-time problems as generating complex waveforms or receiving and demodulating complex waveform/pulses, the Z86L7X family offers a new intelligent counter/timer architecture with 8-bit and 16-bit counter/timers (Figure 1). Also included are a large number of user-selectable modes, and two on-board comparators to process analog signals with separate reference voltages (Figure 2). Notes: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS
HI16 8
LO16 8
16-Bit T16 124 8 8 SCLK Clock Divider TC16H 16 8 TC16L And/Or Logic HI8 8 Input Glitch Filter Edge Detect Circuit 8-Bit T8 8 TC8H 8 TC8L LO8 8
Timer 16
Timer 8/16
Timer 8
Figure 1. Counter/Timer Block Diagram
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DS97LVO0601
Zilog
Z86L79/80 Low-Voltage Microcontroller
P00 P01 P02 P03 P04 P05 P06 P07 P20 P21 P22 P23 P24 P25 P26 P27
Register File 256 x 8-Bit Port 3 Register Bus Internal Address Bus ROM 4K/8K x 8 Internal Data Bus Z8 Core Two Analog Comparators Interrupt Control Port 2 Expanded Register File Expanded Register Bus Machine Timing & Instruction Control
Pref1 P31 P32 P33 P34 P35 P36 P37
1
Port 0
I/O Bit Programmable
XTAL2 XTAL1
Power Counter/Timer 16 16-Bit
VDD VSS
Counter/Timer 8 8-Bit
Figure 2. Functional Block Diagram
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Zilog
PIN DESCRIPTION
P24 P25 P26 P27 P03 P04 P05 P06 VDD XTAL2 XTAL1 P31 P32 P00
1
28
Z86L79/80 DIP
14
15
P23 P22 P21 P20 P02 P01 P37 PREF1 VSS P36 P35 P34 P33 P07
P24 P25 P26 P27 P03 P04 P05 P06 VDD XTAL2 XTAL1 P31 P32 P00
1
28
Z86L79/80 SOIC
14
15
P23 P22 P21 P20 P02 P01 P37 Pref1 VSS P36 P35 P34 P33 P07
Figure 3. 28-Pin DIP Pin Assignments Figure 4. 28-Pin SOIC Pin Assignments
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Zilog Table 1. Pin Identification 28-Pin DIP & SOIC 14 23 24 5 6 7 8 15 25 26 27 28 1 2 3 4 21 12 13 16 17 18 19 22 11 10 9 20 Symbol P00 P01 P02 P03 P04 P05 P06 P07 P20 P21 P22 P23 P24 P25 P26 P27 Pref1 P31 P32 P33 P34 P35 P36 P37 XTAL1 XTAL2 VDD VSS Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input Input Output Output Output Output Input Output
Z86L79/80 Low-Voltage Microcontroller
Description Port 0 is Nibble Programmable.
1
Port 0 can be configured as a 0.4 VDD single-trip point
Port 2 pins are individually configurable as input or output.
Analog Ref Input IRQ2/Modulator input IRQ0 IRQ1 T8 output T16 output T8/T16 output Crystal, Oscillator Clock Crystal, Oscillator Clock Power Supply Ground
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ABSOLUTE MAXIMUM RATINGS
Sym VCC TSTG TA Description Supply Voltage (*) Storage Temp. Oper. Ambient Temp. Min -0.3 -65 Max +7.0 +150 Units V C C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability.
Notes: * Voltage on all pins with respect to GND. See Ordering Information.
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Figure 5).
From Output Under T est
I
150 pF
Figure 5. Test Load Diagram
CAPACITANCE
TA = 25C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND. Parameter Input capacitance Output capacitance I/O capacitance Max 12 pF 12 pF 12 pF
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Z86L79/80 Low-Voltage Microcontroller
DC CHARACTERISTICS
TA = 0C to +70C Sym Parameter Max Input Voltage VCH Clock Input High Voltage Clock Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output High Voltage (P36, P37) Output Low Voltage Output Low Voltage Output Low Voltage (P20-P22, P36, P00, P01, P07) Comparator Input Offset Voltage Input Leakage Output Leakage Reset Input Current Supply Current VCC 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 0.9 VCC 0.9 VCC VSS - 0.3 VSS- 0.3 0.7 VCC 0.7 VCC VSS - 0.3 VSS - 0.3 VCC - 0.4 VCC - 0.4 VCC - .8 VCC - .8 0.4 0.4 0.8 0.8 0.8 0.8 25 25 1 1 1 1 -45 -55 10 15 100 300 3 5 2 4 8 10 0.2 0.1 0.3 0.3 0.3 0.5 10 10 <1 <1 <1 <1 -20 -30 4 10 10 10 1 4 0.8 2.5 1 2 Min Max 7 7 VCC + 0.3 VCC + 0.3 0.2 VCC 0.2 VCC VCC + 0.3 VCC + 0.3 0.2 VCC 0.2 VCC 1.3 2.5 0.5 0.9 1.7 3.7 Typical @ 25C Units V V V Conditions IIN <250 A IIN <250 A Driven by External Clock Generator Driven by External Clock Generator Notes
1
VCL
V V V V V V V V V V V V V V V V mV mV A A A A A A mA mA A A mA mA mA mA A A
VIH VIL VOH1 VOH2 VOL1 VOL2 VOL2
IOH = -0.5 mA IOH = -0.5 mA IOH = -7 mA IOH = -7 mA IOL = 1.0 mA IOL = 1.0 mA IOL = 2.0 mA IOL = 2.0 mA IOL = 10 mA IOL = 10 mA 2 O/P only 9 10
VOFFSET IIL IOL IIR ICC
-1 -1 -1 -1
VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC VIN = OV, VCC
ICC1
Standby Current
ICC2
Standby Current
@ 8.0 MHz 4, 5 @ 8.0 MHz @ 32 kHz 4,5,11,12 @ 32 kHz HALT Mode 4,5 VIN = OV, VCC 4,5 @ 8.0 MHz Clock Divide-by16 @ 8.0 MHz STOP Mode 6,8 VIN = OV, VCC WDT is not Running
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DC CHARACTERISTICS (Continued)
TA = 0C to +70C Sym ICC2 Parameter VCC 2.0V 3.9V Input Common Mode Voltage Range Power-On Reset VCC Low Voltage Protection 2.0V 3.9V 2.0V 3.9V 0 0 7.5 2.5 Min Max 500 800 VCC-1.0V VCC-1.0V 75 20 2.15 13 7 1.7 Typical @ 25C 310 600 Units A A V V ms ms V Conditions STOP Mode VIN = OV, VCC WDT is Running Notes 6,8
VICR TPOR VLV
12
8 MHz max Ext. CLK Freq
7
Notes: 1. GND = 0V 2. 2.0V to 3.9V 3. All outputs unloaded, I/O pins floating, inputs at rail. 4. CL1 = CL2 = 100 pF 5. Same as note [4] except inputs at V CC. 6. The VLV increases as the temperature decreases. 7. Oscillator stopped. 8. Two outputs at a time, independent to other outputs. 9. One at a time. 10. 32 kHz clock driver input. 11. WDT not running. 12. For analog comparator, inputs when analog comparators are enabled.
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Zilog
Z86L79/80 Low-Voltage Microcontroller
AC CHARACTERISTICS
Additional Timing Diagram
1
1 3
Clock
2 7 7 2 3
T
IN
4 6 5
IRQ N
8 9
Clock Setup
11
Stop Mode Recovery Source
10
Figure 6. Additional Timing
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AC CHARACTERISTICS
Additional Timing Table TA = 0C to +70C No 1 2 3 4 5 6 7 8A 8B 9 10 Symbol TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin,TfTin TwIL TwIL TwIH Twsm Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise and Fall Timers Interrupt Request Low Time Int. Request Low Time Interrupt Request Input High Time Stop-Mode Recovery Width Spec Oscillator Start-up Time Watch-Dog Timer Delay Time (5 ms) 15 ms 25 ms 100 ms VCC 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V Min 121 121 Max DC DC 25 25 Units ns ns ns ns ns ns ns ns Notes 1 1 1 1 1 1
37 37 100 70 3TpC 3TpC 8TpC 8TpC 100 100 100 70 3TpC 3TpC 3TpC 3TpC 12 12 5TpC 5TpC 5TpC 5TpC 75 20 150 40 300 80 1200 320
ns ns ns ns
ns ns
11 12
Tost Twdt
12 5 25 10 50 20 225 80
ms ms ms ms ms ms ms ms
1 1 1 1 1 1 1,2 1,2 1,3 1,3 1,2 1,2 8 8 7 7 4 4 D0 = 0 [5] D1 = 0 [5] D0 = 1 [5] D0 = 1 [5] D0 = 0 [5] D0 = 0 [5]
Notes: 1. Timing Reference uses 0.9 VCC for a logic 1 and 0.1 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31). 3. Interrupt request through Port 3 (P30). 4. SMR - D5 = 0 5. Reg. WDTMR 6. 2.0V to 3.9V 7. Reg. SMR - D5 = 0 8. Reg. SMR - D5 = 1
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Z86L79/80 Low-Voltage Microcontroller
AC CHARACTERISTICS
Handshake Timing Diagram
1
Data In Data In Valid
2 1 3
Next Data In Valid
/DAV (Input)
4
Delayed DAV
5
6
RDY (Output)
Delayed RDY
Figure 7. Port I/O with Input Handshake Timing
Data Out
Data Out Valid
Next Data Out Valid
7
/DAV (Output)
8 9 10
Delayed DAV
11
RDY (Input)
Delayed
RDY
Figure 8. Port I/O with Output Handshake Timing
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AC CHARACTERISTICS
Preliminary Handshake Timing Table TA = 0C to +70C 8 MHz No 1 2 3 4 5 6 7 8 9 10 11 Symbol TsDI(DAV) ThDI(DAV) TwDAV TdDAVI(RDY) TdDAVId(RDY) TdRDYO(DAV) TdDO(DAV) TdDAV0(RDY) TdRDY0(DAV) TwRDY TdRDY0d(DAV) Parameter Data In Setup Time Data In Hold Time Data Available Width DAV Falling to RDY Falling Delay DAV Rising to RDY Falling Delay RDY Rising to DAV Falling Delay Data Out to DAV Falling Delay DAV Falling to RDY Falling Delay RDY Falling to DAV Rising Delay RDY Width RDY Rising to DAV Falling Delay VCC 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V Min 0 0 160 115 155 110 160 115 120 80 0 0 63 63 0 0 160 115 110 80 110 80 Max
Data Direction IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
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Z86L79/80 Low-Voltage Microcontroller
PIN FUNCTIONS
XTAL1 Crystal 1 (time-based input). This pin connects a parallel-resonant crystal, ceramic resonator, LC, or RC network or an external single-phase clock to the on-chip oscillator input. XTAL2 Crystal 2 (time-based output). This pin connects a parallel-resonant, crystal, ceramic resonant, LC, or RC network to the on-chip oscillator output. Port 0 (P07-P00). Port 0 is an 8-bit, bidirectional, CMOS compatible port. These eight I/O lines are configured under software control as a nibble I/O port. The output drivers are push-pull in this configuration. Using single trip point ROM mask option, Port 00-03 can be programmed to allow direct interface to applications that require single point comparison like mouse/trackball IR sensors. ROM mask option will enable the 0.4 VDD trip Point Buffers on these inputs. An optional 200 kOhms (port wide) pull-up is available as a mask option on all bits for the L79/L80 versions. These pull-ups are disabled when configured (bit by bit) as an output.
1
4 Z86L7X MCU 4 Port 0 I/O
OEN
Mask Option 200 k PAD
Out
In 0.5 VDD Trip Point Buffer In
**
0.4 VDD Trip Point Buffer **Mask Selectable
Figure 9. Port 0 Configuration
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PIN FUNCTIONS (Continued)
Port 2 (P27-P20). Port 2 is an 8-bit, bidirectional, CMOS compatible I/O port. These eight I/O lines can be independently configured under software control as inputs or outputs. Port 2 is always available for I/O operation. A mask option is available to connect eight 200 kOhms (50%) pull-up resistors on this port. Bits programmed as outputs are globally programmed as either push-pull or opendrain. Port 2 may be placed under handshake control. In this configuration, Port 3 lines, P31 and P36 are used as the handshake controls lines /DAV2 and RDY2. The handshake signal assignment for Port 3, lines P31 and P36 is dictated by the direction (input or output) assigned to Bit 7, Port 2 (Figure 6). The CCP wakes up with the eight bits of Port 2 configured as inputs with open-drain outputs. Port 2 also has an 8-bit input NOR and an NAND gates which can be used to wake up the part from STOP mode (Figure 38). P20 can be programmed to access the edge selection circuitry (Figure 10).
Port 2 (I/O) Z86L7X MCU
Optional Handshake Controls /DAV2 and RDY2 (P31 and P36)
VCC Open-Drain 200 k OEN Mask Option PAD
Out
In
Figure 10. Port 2 Configuration
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DS97LVO0601
Zilog Port 3 (P37-P31). Port 3 is a 7-bit, CMOS compatible three fixed input and four fixed output port. Port 3 consists of three fixed input (P33-P31) and four fixed output (P37P34), and can be configured under software control for Input/Output, Interrupt, Port handshake, Data Memory functions and output from the counter/timers. P31, P32, and P33 are standard CMOS inputs; outputs are push-pull, except for P34, 35 which are controlled by P3M, D0. Two on-board comparators process analog signals on P31 and P32 with reference to the voltage on Pref1 and P33. The analog function is enabled by programming the Port 3 Mode Register (bit 1). P31 and P32 are programmable as
Z86L79/80 Low-Voltage Microcontroller rising, falling, or both edge triggered interrupts (IRQ register bits 6 and 7). Pref1 and P33 are the comparator reference voltage inputs. Access to the edge detection circuit is through P31 or P20. Handshake lines Ports 0, 1, and 2 are available on P31 through P36. Port 3 provides the following control functions: handshake for Ports 0, and 2 (/DAV and RDY); four external interrupt request signals (IRQ3-IRQ0). (See Table 2). Port 3 also provides output for each of the counter/timers and the AND/OR Logic. Control is performed by programming bits D5-D4 of CTRI, bit 0 of CTR0 and bit 0 of CTR2.
1
Table 2. Pin Assignments Pin Pref1 P31 P32 P33 P34 P35 P36 P37 I/O IN IN IN IN OUT OUT OUT OUT C/T ISP Comp. RF1 AN1 AN2 RF2 A01 Int. IRQ2 IRQ0 IRQ1 P0 HS P2 HS D/R D/R
T8 T16 T8/16
R/D R/D A02
Notes: 1. HS = Handshake Signals 2. D = /DAV 3. R = RDY
Comparator Inputs. Port 3, P31 and P32 all have a comparator front end. The comparator reference voltages are on P33 and Pref1. The internal P33 register and its corresponding IRQ1 is connected to the Stop-Mode Recovery source selected by the SMR. In this mode, any of the StopMode Recovery sources can be used to toggle the P33 bit or generate IRQ1. In digital mode, P33 can be used as a Port 3 register input or IRQ1 for P33 (Figure 8).
Note: The comparators are disabled in STOP mode. Comparator Outputs. These may be programmed to be outputted on P34 and P37 through the PCON register (Figure 11).
PRELIMINARY
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PIN FUNCTIONS (Continued)
Counter/Timer T8 P34 OUT P34 OUT P31 + CTR0 D0
P34 PAD
Pref1
0 Normal Control* 1 8-bit Timer output active P37
P37 OUT P32 REF2 (P33) PCON D0 0 = P34, P37 Standard Output * 1 = P34, P37 Comparator Output + -
PAD
*
Reset condition.
Figure 11. Port 3 Comparator Configuration
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DS97LVO0601
Zilog Reset. Program execution begins at location 000CH, 5-10 TpC cycles after the RST is released. For Power-On Reset, the typical reset output time is 5 ms. The Z86L7X does
Z86L79/80 Low-Voltage Microcontroller not reset WDTMR, SMR, P2M or P3M registers on a StopMode Recovery operation either from WDT or the programmed STOP mode recovery source.
1
Pref1 200 K P31 P32 Z86L7X MCU P33 P34 P35 P36 P37 Note: P31, 32, 33 have a 200 K mask option. Port 3 (I/O or Handshake) Mask Option
R247 = P3M D1 1 = Analog 0 = Digital
DIG. P31 (AN1) + Pref1 AN. IRQ2, P31 Data Latch
P32 (AN2) IRQ0, P32 Data Latch + P33 (REF2) -
From Stop-Mode Recovery Source
IRQ1, P33 Data Latch
Figure 12. Port 3 Configuration
PRELIMINARY
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PIN FUNCTIONS (Continued)
CTR0, D0 P3M D0 open-drain Out P34 T8_Out MUX
VDD *
Pad P34
CTR2, D0 P3M D0 open-drain Out P35 T16_Out MUX
VDD *
Pad P35
CTR1, D6
VDD *
Out P36 T8/16_Out
MUX Pad P36
* Default after reset output is push-pull.
Figure 13. Port 3 Configuration
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DS97LVO0601
Zilog
Z86L79/80 Low-Voltage Microcontroller
FUNCTIONAL DESCRIPTION
The Z8 CCPTM incorporates special functions to enhance the Z8's functionality in consumer and battery operated applications. Reset. The device is reset in one of the following conditions:
s s s s
External Data Memory. Not accessible using the 28-pin Z86L79/80. Expanded Register File. The register file has been expanded to allow for additional system control registers, and for mapping of additional peripheral devices along with I/O ports into the register address area. The Z8 register address space R0 through R15 has now been implemented as 16 groups of 16 registers per group. These register groups are known as the ERF (Expanded Register File). Bits 7-4 of register RP select the working register group. Bits 3-0 of register RP select the expanded register group (Figure 15). The upper nibble of the register pointer (Figure 12) selects which group of 16 bytes in the register file, out of the full 256, will be accessed. The lower nibble selects the expanded register file bank and, in the case of the Z86L79/80 Banks F and D are implemented. A 0H in the lower nibble will allow the normal register file to be addressed, but any other value from 1H to FH will exchange the lower 16 registers in favor of an expanded register group of 16 registers. For example:
1
Power-On Reset Watch-Dog Timer Stop-Mode Recovery Source Low Voltage Detection
Program Memory. The Z86L7X addresses up to 4K and 8 Kbytes of internal program memory. (Figure 10). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain five 16-bit vectors that correspond to the five available interrupts. Addresses 12 to 4K, and 8K (dependent on version) consist of on-chip mask-programmed ROM.
8191 On-Chip ROM
Z86L79/80: (See Figure 15) R253 RP = 00H R0 = Port 0 R1 = Port 1 R2 = Port 2 R3 = Port 3 But if:
Location of First Byte of Instruction Executed After RESET 12 11 10 9 8 7 Interrupt Vector (Lower Byte) 6 5 4 3 2 1 0
Reset Start Address Reserved Reserved IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQ0 IRQ0
R253 RP = 0DH R0 = CTRL0 R1 = CTRL1 R2 = CTRL2 R3 = Reserved The counter/timers are mapped into ERF group D. Access is easily done using the following example: LD RP, #0DH Select ERF D for access and register Bank 0 as the working register group LDR0,#xx access CTRL0 LD1, #xx access CTRL1 LDRP, #7DH Select expanded register group(ERF) Bank D for access and register Group 7 as the working register Group. LD R1, 2 CTRL2 register 71H
Interrupt Vector (Upper Byte)
Figure 14. Program Memory Map
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Z8(R) ST ANDARD CONTROL REGISTERS
RESET CONDITION
D7 D6 D5 D4 D3 D2 D1 D0
REGISTER** REGISTER POINTER
7 6 5 4 3 2 1 0 FF FE FD SPL SPH RP FLAGS IMR IRQ IPR P01M P3M P2M Reserved Reserved Reserved Reserved Reserved Reserved U U 0 U 0 0 U 0 0 1 U U U U 0 0 U U 0 U U 0 U 1 0 1 U U U U 0 U U U 0 U U 0 U 0 0 1 U U U U 0 U U U 0 U U 0 U 0 0 1 U U U U 0 0 U U 0 U U 0 U 1 0 1 U U U U 0 0 U U 0 U U 0 U 1 0 1 U U U U 0 0 U U 0 U U 0 U 0 0 1 U U U U 0 0 U U 0 U U 0 U 1 0 1 U U U U 0 0
Working Register Group Pointer
Expanded Register Group Pointer
FC FB FA F9
* * *
Z8 Register File**
FF FO
F8 F7 F6 F5 F4 F3 F2 F1 F0
EXP ANDED REG. GROUP (F) REGISTER**
RESET CONDITION
U U U 0 1 1 0 1
*
7F Reserved
(F) 0F (F) 0E (F) 0D (F) 0C
WDTMR Reserved SMR2 Reserved SMR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PCON
U
0
U
0
0
0
U
U
(F) 0B (F) 0A (F) 09 (F) 08
0
0
1
0
0
0
U
0
Reserved
0F 00
(F) 07 (F) 06 (F) 05 (F) 04 (F) 03 (F) 02 (F) 01
*
(F) 00
U
U
U
U
U
U
U
0
EXPANDED REG. GROUP (D) REGISTER** RESET CONDITION Reserved HI8 L08 HI16 L016 TC16H TC16L TC8H TC8L Reserved CTR2 CTR1 CTR0 0 0 0 U 0 U U U U U U U U U U U U U U U U 0 U 0 U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U
EXP ANDED REG. GROUP (0) REGISTER** RESET CONDITION
P3 P2 P1 P0 0 U U U 0 U U U 0 U U U 0 U U U U U U U U U U U U U U U U U U U
(D) 0C (D) 0B (D) 0A (D) 09 (D) 08 (D) 07 (D) 06 (D) 05 (D) 04 (D) 03 (D) 02 (D) 01 (D) 00
* * * *
(0) 03 (0) 02 (0) 01 (0) 00 U = Unknown
* Will not be reset with a Stop-Mode Recovery ** All addresses are in Hexadecimal
Will not be reset with a Stop-Mode Recovery, except Bit 0.
Figure 15. Expanded Register File Architecture
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Zilog
FUNCTIONAL DESCRIPTION (Continued)
Note: When SPH is used as a general-purpose register and Port 0 is in address mode, the contents of SPH will be loaded into Port 0 whenever the internal stack is accessed
R253 RP D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register File Pointer Default Setting After Reset = 0000 0000 Working Register Pointer
r 7 r 6 r 5 r 4 r 3 r 2 r 1 r 0 R253
Figure 16. Register Pointer Register File. The register file consists of four I/O port registers, 236 general-purpose registers with 10 control and status registers (R3-R0, R239-R4, and R255-R246, respectively), plus three Expanded Register Groups (0, D, and F) which reside in the expanded register group. Instructions can access registers directly or indirectly through an 8-bit address field. This allows a short, 4-bit register address using the Register Pointer (Figure 14). In the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 continuous locations. The Register Pointer addresses the starting location of the active working register group. Note: Register Bank E0-EF is only accessed through working registers and indirect addressing modes. R240R245 registers are reserved. Stack. The Z86L7X external data memory or the internal register file is used for the stack. An 8-bit Stack Pointer (R255) is used for the internal stack that resides within the general-purpose registers (R4-R239). SPH is used as a general-purpose register only when using internal stacks.
FF
The upper nibble of the register file address provided by the register pointer specifies the active working-register group
R15 to R0 F0
Specified Working Register Group
2F 20 1F Register Group 1 10 0F Register Group 0 I/O Ports
The lower nibble of the register file address provided by the instruction points to the specified register
R15 to R0
R15 to R4 R3 to R0
00
Figure 17. Register Pointer
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DS97LVO0601
Z86L79/80 Low-Voltage Microcontroller
Zilog L016(D)%08: Holds the captured data from the output of the 16-bit Counter/Timer16. This register holds the LSByte of the data. Field T16_Capture_LO Bit Position 76543210 R W Description Captured Data No Effect
Counter/Timer Register Description
. Expanded Register Group D (D)%0C (D)%0B (D)%0A (D)%09 (D)%08 (D)%07 (D)%06 (D)%05 (D)%04 (D)%03 (D)%02 (D)%01 Reserved HI8 LO8 HI16 LO16 TC16H TC16L TC8H TC8L Reserved CTR2 CTR1
TC16H(D)%07: Counter/Timer2 MS-Byte Hold Register. Bit Position 76543210 R/W
Field T16_Data_HI
Description Data
TC16L(D)%06: Counter/Timer2 LS-Byte Hold Register. Field T16_Data_LO Bit Position 76543210 R/W Description Data
HI8(D)%0B: Holds the captured data from the output of the 8-bit Counter/Timer0. This register is typically used to hold the number of counts when the input signal is 1. Field T8_Capture_HI Bit Position 76543210 R W Description Captured Data No Effect
TC8H(D)%05: Counter/Timer8 High Hold Register. Field T8_Level_HI Bit Position 76543210 R/W Description Data
L08(D)%0A: Holds the captured data from the output of the 8-bit Counter/Timer0. This register is typically used to hold the number of counts when the input signal is 0. Field T8_Capture_L0 Bit Position 76543210 R W Description Captured Data No Effect
TC8L(D)%04: Counter/Timer8 Low Hold Register. Bit Position 76543210 R/W
Field T8_Level_LO
Description Data
HI16(D)%09: Holds the captured data from the output of the 16-bit Counter/Timer16. This register holds the MSByte of the data. Bit Position 76543210 R W
Field T16_Capture_HI
Description Captured Data No Effect
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PRELIMINARY
Zilog CTR0 (D)00: Counter/Timer8 Control Register. Field T8_Enable Bit Position 7------R W Single/Modulo-N Time_Out -6--------5-----R/W R Value 0* 1 0 1 0* 1 0 1 0 1 0 0* 01 10 11 0 1 0 1 0 1
Z86L79/80 Low-Voltage Microcontroller
Description Counter Disabled Counter Enabled Stop Counter Enable Counter Modulo-N Single Pass No Counter Time-Out Counter Time-Out Occurred No Effect Reset Flag to 0 SCLK SCLK/2 SCLK/4 SCLK/8 Disable Data Capture Int. Enable Data Capture Int. Disable Time-Out Int. Enable Time-Out Int P34 as Port Output T8 Output on P34
1
T8 _Clock
---43---
R/W
Capture_INT_MASK Counter_INT_Mask P34_Out
-----2-------1-------0
R/W R/W R/W
Notes: * Indicates the value upon Power-On Reset.
PRELIMINARY
3-23
Z86L79/80 Low-Voltage Microcontroller CTR0: Counter/Timer8 Control Register Description T8 Enable. This field enables T8 when set (written) to 1. Single/Modulo-N. When set to 0 (modulo-n), the counter reloads the initial value when the terminal count is reached. When set to 1 (single pass), the counter stops when the terminal count is reached. Time-Out. This bit is set when T8 times out (terminal count reached). To reset this bit, a 1 should be written to this location. This is the only way to reset this status condition, therefore, care should be taken to reset this bit prior to using/enabling the counter/timers. Note: Care must be taken when utilizing the OR or AND commands to manipulate CTR0, bit 5 and CTR1, bits 0 and 1 (Demodulation Mode). These instructions use a Read-Modify-Write sequence in which the current status from the CTR0 and CTR1 registers will be ORed or ANDed with the designated value and then written back into the registers. Example: When the status of bit 5 is 1, a reset condition will occur.
Zilog T8 Clock. Defines the frequency of the input signal to T8. Capture_INT_Mask. Set this bit to allow interrupt when data is captured into either LO8 or HI8 upon a positive or negative edge detection in demodulation mode. Counter_INT_Mask. Set this bit to allow interrupt when T8 has a time out. P34_Out. This bit defines whether P34 is used as a normal output pin or the T8 output.
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Zilog CTR1(D)%01: Controls the functions in common with the T8 and T16. Field Mode P36_Out/ Demodulator_Input Bit Position 7-------6-----R/W R/W 0 1 0 1 T8/T16_Logic/ Edge _Detect --54---R/W 00 01 10 11 00 01 10 11 Transmit_Submode/ Glitch_Filter ----32-R/W 00 01 10 11 00 01 10 11 Initial_T8_Out/ Rising_Edge ------1R/W 0 1 0 1 0 1 0 1 0 1 0 1 Value 0 1
Z86L79/80 Low-Voltage Microcontroller
Description Transmit Mode Demodulation Mode Transmit Mode Port Output T8/T16 Output Demodulation Mode P31 P20 Transmit Mode AND OR NOR NAND Demodulation Mode Falling Edge Rising Edge Both Edges Reserved Transmit Mode Normal Operation Ping-Pong Mode T16_Out =0 T16_Out = 1 Demodulation Mode No Filter 4 SCLK Cycle 8 SCLK Cycle 16 SCLK Cycle Transmit Mode T8_OUT is 0 Initially T8_OUT is 1 Initially Demodulation Mode No Rising Edge Rising Edge Detected No Effect Reset Flag to 0 Transmit Mode T16_OUT is 0 Initially T16_OUT is 1 Initially Demodulation Mode No Falling Edge Falling Edge Detected No Effect Reset Flag to 0
1
R W Initial_T16_Out/ Falling _Edge -------0 R/W
R R
PRELIMINARY
3-25
Z86L79/80 Low-Voltage Microcontroller CTR1 Register Description Mode. If it is 0, the Counter/Timers are in the transmit mode, otherwise they are in the demodulation mode. P36_Out/Demodulator_Input. In Transmit Mode, this bit defines whether P36 is used as a normal output pin or the combined output of T8 and T16. In Demodulation Mode, this bit defines whether the input signal to the Counter/Timers is from P20 or P31. T8/T16_Logic/Edge _Detect. In Transmit Mode, this field defines how the outputs of T8 and T16 are combined (AND, OR, NOR, NAND). In Demodulation Mode, this field defines which edge should be detected by the edge detector. Transmit_Submode/Glitch Filter. In Transmit Mode, this field defines whether T8 and T16 are in the "Ping-Pong" mode or in independent normal operation mode. Setting this field to "Normal Operation Mode" terminates the "PingPong Mode" operation. When set to 10, T16_OUT is immediately set to A0. When set to 11, T16 is immediately forced to a 1. In Demodulation Mode, this field defines the width of the glitch that should be filtered out.
Zilog Initial_T8_Out/Rising_Edge. In Transmit Mode, if 0, the output of T8 is set to 0 when it starts to count. If 1, the output of T8 is set to 1 when it starts to count. Note: When (CTR1, D1, D0) Bits are loaded, T8_OUT and T16_OUT will switch to the opposite state. This ensures a transition to the initial value once the counters are enabled. Therefore, it is not advisable to change (CTR1, D1, D0) Bits while the counters are running. In Demodulation Mode, this bit is set to 1 when a rising edge is detected in the input signal. In order to reset it, a 1 should be written to this location. Initial_T16 Out/Falling _Edge. In Transmit Mode, if it is 0, the output of T16 is set to 0 when it starts to count. If it is 1, the output of T16 is set to 1 when it starts to count. This bit is effective only in Normal or Ping-Pong Mode (CTR1, D3, D2). In Demodulation Mode, this bit is set to 1 when a falling edge is detected in the input signal. In order to reset it, a 1 should be written to this location.
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Zilog CTR2 (D)%02: Counter/Timer16 Control Register. Field T16_Enable Bit Position 7------R W Single/Modulo-N -6-----R/W 0 1 0 1 0 Value 0* 1 0 1
Z86L79/80 Low-Voltage Microcontroller
Description Counter Disabled Counter Enabled Stop Counter Enable Counter Transmit Mode Modulo-N Single Pass Demodulation Mode T16 Recognizes Edge T16 Does Not Recognize Edge No Counter Time-Out Counter Time-Out Occurred No Effect Reset Flag to 0 SCLK SCLK/2 SCLK/4 SCLK/8 Disable Data Capture Int. Enable Data Capture Int. Disable Time-Out Int. Enable Time-Out Int. P35 as Port Output T16 Output on P35
1
Time_Out
--5-----
R
T16 _Clock
---43---
R/W
Capture_INT_Mask Counter_INT_Mask P35_Out
-----2-------1-------0
R/W R/W R/W
00 01 10 11 0 1 0 1 0 1
Note: *Indicates the value upon Power-On Reset.
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3-27
Z86L79/80 Low-Voltage Microcontroller CTR2 Description T16_Enable. This field enables T16 when set to 1. Single/Modulo-N. In Transmit Mode, when set to 0, the counter reloads the initial value when terminal count is reached. When set to 1, the counter stops when the terminal count is reached. In Demodulation Mode, when set to 0 , T16 captures and reloads on detection of all the edges; when set to 1, T16 captures and detects on the first edge, but ignores the subsequent edges. For details, see the description of T16 Demodulation Mode.
Zilog Time_Out. This bit is set when T16 times out (terminal count reached). In order to reset it, a 1 should be written to this location. T16_Clock. Defines the frequency of the input signal to Counter/Timer16. Capture_INT_Mask. Set this bit to allow interrupt when data is captured into LO16 and HI16. Counter_INT_Mask. Set this bit to allow interrupt when T16 times out. P35_Out. This bit defines whether P35 is used as a normal output pin or T16 output.
SMR2(F)%0D: Stop-Mode Recovery Register 2. Field Reserved Recovery Level Reserved Source Bit Position 7-------6-------5-------432-W Value 0 0* 1 0 000* 001 010 011 100 101 110 111 00 Description Reserved (Must be 0) Low High Reserved (Must be 0) A. POR Only B. NAND of P23-P20 C. NAND or P27-P20 D. NOR of P33-P31 E. NAND of P33-P31 F. NOR of P33-P31, P00,P07 G. NAND of P33-P31,P00,P07 H. NAND of P33-P31,P22-P20 Reserved (Must be 0)
W
Reserved
------10
Note: *Indicates the value upon Power-On Reset.
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Z86L79/80 Low-Voltage Microcontroller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Port pins configured as outputs are ignored as an SMR2 recover source. For example, if NAND of P23-P20 is selected as the recover source and P20 is configured as output, then P20 is ignored as a recover source. The effective recover source in this case is NAND of P23-P21.
CTR1 D5,D4
P31 MUX P20
Glitch Filter
Edge Detector
Pos Edge Neg Edge
CTR1 D6 CTR1 D3,D2
Figure 18. Glitch Filter Circuitry
Z8 Data Bus CTR0 D2 Pos Edge Neg Edge HI8 CTR0 D4, D3 Clock LO8 IRQ4
CTR0 D1 Clock Select 8-Bit Counter T8
SCLK
T8_OUT
TC8H
TC8L
Z8 Data Bus
Figure 19. 8-Bit Counter/Timer Circuits
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DS97LVO0601
Z86L79/80 Low-Voltage Microcontroller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Input Circuit The edge detector monitors the input signal on P31 or P20. Based on CTR1 D5-D4, a pulse is generated at the Pos Edge or Neg Edge line when an edge is detected. Glitches in the input signal which have a width less than specified (CTR1 D3, D2) are filtered out. T8 Transmit Mode When T8 is enabled, the output of T8 depends on CTR1, D1. If it is 0, T8_OUT is 1. If it is 1, T8_OUT is 0. When T8 is enabled, the output T8_OUT switches to the initial value (CTR1 D1). If the initial value (CTR1 D1) is 0, TC8L is loaded, otherwise TC8H is loaded into the counter. In Single-Pass Mode (CTR0 D6), T8 counts down to 0 and stops, T8_OUT toggles, the time-out status bit (CTR0 D5) is set, and a time-out interrupt can be generated if it is enabled (CTR0 D1) (Figure 22). In Modulo-N Mode, upon reaching terminal count, T8_OUT is toggled, but no interrupt is generated. Then T8 loads a new count (if the T8_OUT level now is 0), TC8L is loaded; if it is 1, TC8H is loaded. T8 counts down to 0, toggles T8_OUT, sets the time-out status bit (CTR0 D5) and generates an interrupt if enabled (CTR0 D1) (Figure 23). This completes one cycle. T8 then loads from TC8H or TC8L according to the T8_OUT level, and repeats the cycle. The user can modify the values in TC8H or TC8L at any time. The new values take effect when they are loaded. Care must be taken not to write these registers at the time the values are to be loaded into the counter/timer, to ensure known operation. An initial count of 1 is not allowed (a non-function will occur). An initial count of 0 will cause TC8 to count from 0 to %FF to %FE (Note, % is used for hexadecimal values). Transition from 0 to %FF is not a time-out condition. Note: Using the same instructions for stopping the counter/timers and setting the status bits is not recommended. Two successive commands, first stopping the counter/timers, then resetting the status bits is necessary. This is required because it takes one counter/timer clock interval for the initiated event to actually occur.
TC8H Counts
"Counter Enable" Command, T8_OUT Switches To Its Initial Value (CTR1 D1)
T8_OUT Toggles, Time-Out Interrupt
Figure 20. T8_OUT in Single-Pass Mode
T8_OUT Toggles
T8_OUT
TC8L
TC8H
TC8L
TC8H
TC8L
"Counter Enable" Command, T8_OUT Switches To Its Initial Value (CTR1 D1)
Time-Out Interrupt
Time-Out Interrupt
Figure 21. T8_OUT in Modulo-N Mode
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DS97LVO0601
Zilog T8 Demodulation Mode The user should program TC8L and TC8H to %FF. After T8 is enabled, when the first edge (rising, falling, or both depending on CTR1 D5, D4) is detected, it starts to count down. When a subsequent edge (rising, falling, or both depending on CTR1 D5, D4) is detected during counting, the current value of T8 is one's complemented and put into one of the capture registers. If it is a positive edge, data is
Z86L79/80 Low-Voltage Microcontroller put into LO8, if negative edge, HI8. One of the edge detect status bits (CTR1 D1, D0) is set, and an interrupt can be generated if enabled (CTR0 D2). Meanwhile, T8 is loaded with %FF and starts counting again. Should T8 reach 0, the time-out status bit (CTR0 D5) is set, an interrupt can be generated if enabled (CTR0 D1), and T8 continues counting from %FF (Figure 22).
1
T8 (8-Bit) Count Capture
No
T8_Enable (Set By User)
Yes
Edge Present No Yes
What Kind Of Edge Pos Neg
T8 L08
T8 HI8
%FF T8
Figure 22. Demodulation Mode Count Capture Flowchart
PRELIMINARY
3-31
Z86L79/80 Low-Voltage Microcontroller
Zilog
T8 (8-Bit) Transmit Mode
No
T8_Enable Bit Set CTR0, D7 Yes
Reset T8_Enable Bit 0
CTR1, D1 Value
1
Load TC8L Reset T8_OUT
Load TC8H Set T8_OUT
Set Time-out Status Bit (CTR0 D5) and Generate Timeout_Int If Enabled
Enable T8
No
T8_Timeout Yes
Single Pass
Single Pass? Modulo-N
1 T8_OUT Value
0
Load TC8L Reset T8_OUT
Load TC8H Set T8_OUT
Enable T8 Set Time-out Status Bit (CTR0 D5) and Generate Timeout_Int If Enabled No
T8_Timeout Yes Disable T8
Figure 23. Transmit Mode Flowchart
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Zilog
Z86L79/80 Low-Voltage Microcontroller
T8 (8-Bit) Demodulation Mode
1
No
T8_Enable CTR0, D7 Yes %FF TC8
Edge Present No Yes
Disable T8
Enable TC8
T8_Enable Bit Set
Yes No Edge Present
Yes Set Edge Present Status Bit And Trigger Data Capture Int. If Enabled
T8 Time Out
No
Yes Set Time-out Status Bit And Trigger Time Out Int. If Enabled
Continue Counting
Figure 24. Demodulation Mode Flowchart
PRELIMINARY
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Z86L79/80 Low-Voltage Microcontroller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Z8 Data Bus CTR0 D2 Pos Edge Neg Edge HI8 CTR0 D4, D3 Clock LO8 IRQ4
CTR0 D1 Clock Select 8-Bit Counter T8
SCLK
T8_OUT
TC8H
TC8L
Z8 Data Bus
Figure 25. 16-Bit Counter/TImer Circuits
T16 Transmit Mode In Normal or Ping-Pong Mode, the output of T16 when not enabled is dependent on CTR1, D0. If it is a 0, T16_OUT is a 1; if it is a 1, T16_OUT is 0. The user can force the output of T16 to either a 0 or 1 whether it is enabled or not by programming CTR1 D3, D2 to a 10 or 11. When T16 is enabled, TC16H * 256 + TC16L is loaded, and T16_OUT is switched to its initial value (CTR1 D0). When T16 counts down to 0, T16_OUT is toggled (in Normal or Ping-Pong Mode), an interrupt is generated if enabled (CTR2 D1), and a status bit (CTR2 D5) is set. Note that global interrupts will override this function as described in the interrupts section. If T16 is in Single-Pass Mode, it is stopped at this point. If it is in Modulo-N Mode, it is loaded with TC16H * 256 + TC16L and the counting continues.
The user can modify the values in TC16H and TC16L at any time. The new values take effect when they are loaded. Care must be taken not to load these registers at the time the values are to be loaded into the counter/timer, to ensure known operation. An initial count of 1 is not allowed. An initial count of 0 will cause T16 to count from 0 to %FF FF to %FFFE. Transition from 0 to %FFFF is not a time-out condition.
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PRELIMINARY
DS97LVO0601
Zilog
Z86L79/80 Low-Voltage Microcontroller
TC16H*256+TC16L Counts
1
"Counter Enable" Command, T16_OUT Switches To Its Initial Value (CTR1 D0) T16_OUT Toggles, Time-Out Interrupt
Figure 26. T16_OUT in Single-Pass Mode
TC16H*256+TC16L
TC16H*256+TC16L
T16_OUT
TC16H*256+TC16L
"Counter Enable" Command, T16_OUT Switches To Its Initial Value (CTR1 D0)
T16_OUT Toggles, Time-Out Interrupt
T16_OUT Toggles, Time-Out Interrupt
Figure 27. T16_OUT in Modulo-N Mode
T16 Demodulation Mode The user should program TC16L and TC16H to %FF. After T16 is enabled, when the first edge (rising, falling, or both depending on CTR1 D5, D4) is detected, begins to count down. If D6 of CTR2 is 0: When a subsequent edge (rising, falling, or both depending on CTR1 D5, D4) is detected during counting, the current count in T16 is one's complemented and put into HI16 and LO16. When data is captured, one of the edge detect status bits (CTR1 D1, D0) is set and an interrupt is generated if enabled (CTR2 D2). T16 is loaded with %FFFF and starts again.
If D6 of CTR2 is 1: T16 ignores the subsequent edges in the input signal and continues counting down. A time out of T8 will cause T16 to capture its current value and generate an interrupt if enabled (CTR2, D2). In this case, T16 does not reload and continues counting. If D6 bit of CTR2 is toggled (by writing a 0 then a 1 to it), T16 will capture and reload on the next edge (rising, falling, or both depending on CTR1 D5, D4) but continue to ignore subsequent edges. Should T16 reach 0, it continues counting from %FFFF; meanwhile, a status bit (CTR2 D5) is set and an interrupt time-out can be generated if enabled (CTR2 D1).
PRELIMINARY
3-35
Z86L79/80 Low-Voltage Microcontroller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Ping-Pong Mode This operation mode is only valid in Transmit Mode. T8 and T16 need to be programmed in Single-Pass Mode (CTR0 D6, CTR2 D6) and Ping-Pong Mode needs to be programmed in CTR1 D3, D2. The user can begin the operation by enabling either T8 or T16 (CTR0 D7 or CTR2 D7). For example, if T8 is enabled, T8_OUT is set to this initial value (CTR1 D1). According to T8_OUT's level, TC8H or TC8L is loaded into T8. After the terminal count is reached, T8 is disabled and T16 is enabled. T16_OUT switches to its initial value (CTR1 D0), data from TC16H and TC16L is loaded, and T16 starts to count. After T16 reaches the terminal count it stops, T8 is enabled again, and the whole cycle repeats. Interrupts can be allowed when T8 or T16 reaches terminal control (CTR0 D1, CTR2 D1). To stop the Ping-Pong operation, write 00 to bits D3 and D2 of CTR1. Note:Enabling Ping-Pong operation while the counter/timers are running may cause intermittent counter/timer function. Disable the counter/timers, then reset the status flags prior to instituting this operation.
Enable TC8
Time-Out
Enable Ping-Pong CTR1 D3,D2 TC16
Time-Out
Figure 28. Ping-Pong Mode
To Initiate Ping-Pong Mode First, make sure both counter/timers are not running. Then set T8 into Single-Pass Mode (CTR0 D6), set T16 into Single-Pass Mode (CTR2 D6), and set Ping-Pong Mode (CTR1 D2, D3). These instructions do not have to be in any particular order. Finally, start Ping-Pong Mode by enabling either T8 (CTR0 D7) or T16 (CTR2 D7).
During Ping-Pong Mode The enable bits of T8 and T16 (CTR0 D7, CTR2 D7) will be cleared by hardware. The time-out bits (CTR0 D5, CTR2 D5) will be set every time the counter/timers reach the terminal count.
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PRELIMINARY
DS97LVO0601
Zilog
Z86L79/80 Low-Voltage Microcontroller
TC8H
TC8H T8_OUT Toggles TC16H*256+TC16L
1
T8_OUT
Enable T8, T8_OUT Switches To Its Initial Value
T8_OUT Toggles
TC16H*256+TC16L T16_OUT Toggles T16_OUT
T16_OUT
T16_OUT Switches To Its Initial Value When TC16 Is Enabled
Figure 29. T8_OUT and T16_OUT in Ping-Pong Mode
P34_INTERNAL MUX
P34_EXT
CTR0 D0 P36_INTERNAL T8_OUT T16_OUT CTR1, D2 AND/OR/NOR/NAND Logic MUX CTR1 D6 CTR1 D5,D4 CTR1 D3 P35_INTERNAL MUX P35_EXT MUX P36_EXT
CTR2 D0
Figure 30. Output Circuit
PRELIMINARY
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Z86L79/80 Low-Voltage Microcontroller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Interrupts. The Z86L7X has five different interrupts. The interrupts are maskable and prioritized (Figure 31). The five sources are divided as follows: three sources are claimed by Port 3 lines P33-P31, the remaining two by the counter/timers (Table 3). The Interrupt Mask Register globally or individually enables or disables the five interrupt requests.
IRQ0 IRQ 1, 3, 4
IRQ2
Interrupt Edge Select
IRQ Register (D6, D7)
IRQ
IMR 5 IPR
Global Interrupt Enable Interrupt Request
Priority Logic
Vector Select
Figure 31. Interrupt Block Diagram
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PRELIMINARY
DS97LVO0601
Zilog Table 3. Interrupt Types, Sources, and Vectors Name IRQ0 Source /DAV0, IRQ0 Vector Location 0, 1 Comments External (P32), Rising Falling Edge Triggered External (P33), Falling Edge Triggered External (P31), Rising Falling Edge Triggered Internal Internal Software generated
Z86L79/80 Low-Voltage Microcontroller An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is mapped into IRQ0. Interrupts IRQ2 and IRQ0 may be rising, falling, or both edge triggered, and are programmable by the user. The software can poll to identify the state of the pin. Programming bits for the Interrupt Edge Select are located in the IRQ Register (R250), bits D7 and D6. The configuration is shown in Table 4. Table 4. IRQ Register IRQ D7 0 0 1 1
Notes: F = Falling Edge R = Rising Edge
1
IRQ1,
IRQ1
2, 3
IRQ2
/DAV2, IRQ2, TIN T16 T8
4, 5
IRQ3 IRQ4 IRQ5
6, 7 8, 9 10,11
D6 0 1 0 1
Interrupt Edge IRQ2 IRQ0 F F F R R F R/F R/F
When more than one interrupt is pending, priorities are resolved by a programmable priority encoder controlled by the Interrupt Priority register. An interrupt machine cycle is activated when an interrupt request is granted. This disables all subsequent interrupts, saves the Program Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt. All Z86L7X interrupts are vectored through locations in the program memory. This memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked and the Interrupt Request register is polled to determine which of the interrupt requests need service.
In analog mode, the Stop-Mode Recovery sources selected by the SMR register are connected to IRQ1 input. Any of the Stop-Mode Recovery sources for SMR (except P31, P32, and P33) can be used to generate IRQ1 (falling edge triggered). Clock. The Z86L7X on-chip oscillator has a high-gain, parallel-resonant amplifier for connection to a crystal, LC, ceramic resonator, or any suitable external clock source (XTAL1 = Input, XTAL2 = Output). The crystal should be AT cut, 1 MHz to 8 MHz maximum, with a series resistance (RS) less than or equal to 100 Ohms. The Z86L7X on-chip oscillator may be driven with a cost-effective RC network or other suitable external clock source.
PRELIMINARY
3-39
Z86L79/80 Low-Voltage Microcontroller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
The crystal should be connected across XTAL1 and XTAL2 using the suppliers recommended capacitors from each pin to ground. The RC oscillator configuration is an external resistor connected from XTAL1 to XTAL2, with a frequency-setting capacitor from XTAL1 to ground (Figure 32). Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator is used for the Power-On Reset (POR) timer function. The POR time allows VCC and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of three conditions: 1. Power Fail to Power OK status including waking up from Low Voltage standby mode. 2. Stop-Mode Recovery (if D5 of SMR = 1). 3. WDT Time-Out. The POR time is a nominal 5 ms. Bit 7 of the Stop-Mode Register determines whether the POR timer is bypassed after Stop-Mode Recovery (typical for external clock, RC, LC oscillators).
XTAL1 C1 C1 L
XTAL1 C1 R
XTAL1 C1 Rf
XTAL1
XTAL1
XTAL2 C2 C2
XTAL2
XTAL2 XTAL2 C2 Rd
XTAL2
Ceramic Resonator or Crystal C1, C2 = 47 pF TYP * f = 8 MHz * Preliminary value including pin parasitics
LC C1, C2 = 22 pF L = 130 H * f = 3 MHz *
RC @ 3V VCC (TYP) C1 = 33 pF * R = 1K *
32 kHz XTAL C1 = 20 pF, C = 33 pF Rd = 56 - 470K Rf =10 M
External Clock
Figure 32. Oscillator Configuration
HALT. HALT turns off the internal CPU clock, but not the XTAL oscillation. The counter/timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, and IRQ4 remain active. The devices are recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt service routine, the program continues from the instruction after the HALT. STOP. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 A (typical) or less. STOP mode is terminated only by a reset, such as WDT time-out, POR, SMR, or external reset. This causes the processor to restart the application program at address 000CH. In order to enter STOP (or HALT) mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user must execute a NOP (opcode = FFH) immediately before the appropriate sleep instruction, i.e.,
FF 6F FF 7F
NOP ; clear the pipeline STOP ; enter STOP mode or NOP ; clear the pipeline HALT ; enter HALT mode
Note: A WDT time-out during STOP mode will have the same effect like a recovery from any programmed STOP mode recovery source except the reset delay of TPOR will occur. Note: The comparators are disabled in STOP mode. Port Configuration Register (PCON). The PCON register configures the comparator output on Port 3. It is located in the expanded register file at Bank F, location 00 (Figure 33).
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PCON (FH) 00H D7 D6 D5 D4 D3 D2 D1 D0 Comparator Output Port 3 0 P34, P37 Standard Output* 1 P34, P37 Comparator Output Reserved (Must be 1) * Default Setting After Reset
1
Figure 33. Port Configuration Register (PCON) (Write Only)
Comparator Output Port 3 (D0). Bit 0 controls the comparator used in Port 3. A 1 in this location brings the comparator outputs to P34 and P37, and a 0 releases the Port to its standard I/O configuration.
Stop-Mode Recovery Register (SMR). This register selects the clock divide value and determines the mode of Stop-Mode Recovery (Figure 34). All bits are write only except bit 7, which is read only. Bit 7 is a flag bit that is hardware set on the condition of STOP recovery and reset by a power-on cycle. Bit 6 controls whether a low level or a high level is required from the recovery source. Bit 5 controls the reset delay after recovery. Bits 2, 3, and 4, the SMR register, specify the source of the Stop-Mode Recovery signal. Bits 0 and 1 determine the frequency of SCLK/TCLK in relation to the OSC. The SMR is located in Bank F of the Expanded Register Group at address 0BH.
PRELIMINARY
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FUNCTIONAL DESCRIPTION (Continued)
SMR (0F) 0B D7 D6 D5 D4 D3 D2 D1 D0 SCLK/TCLK Divide-by-16 0 OFF ** 1 ON External Clock DIvide By 2 0 SCLK/TCLK = XTAL/2* 1 SCLK/TCLK = XTAL Stop-Mode Recovery Source 000 POR Only* 001 Reserved 010 P31 0 11 P32 100 P33 101 P27 11 0 P2 NOR 0-3 111 P2 NOR 0-7 Stop Delay 0 OFF 1 ON* Stop Recovery Level 0 Low* 1 High Stop Flag 0 POR* 1 Stop Recovery** * Default Setting After Reset ** Default Setting After Reset and Stop-Mode Recovery
Figure 34. Stop-Mode Recovery Register
OSC SMR, D1 /2
/16
SCLK SMR, D0 TCLK
Figure 35. SCLK Circuit
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SMR D4 D3 D2 000 VCC VCC
SMR2 D4 D3 D2 000
1
SMR D4 D3 D2 010 P20 P31 S1 P23
SMR2 D4 D3 D2 001
SMR D4 D3 D2 011 P20 P32 S2 SMR D4 D3 D2 100 P33 S3 To IRQ1 S4 SMR D4 D3 D2 101 P27 SMR D4 D3 D2 110 P20 P23 P31 P32 P33 P31 P32 P33 P27
SMR2 D4 D3 D2 010
SMR2 D4 D3 D2 011
SMR2 D4 D3 D2 100
P31 P32 P33 P00 P07
SMR2 D4 D3 D2 101
SMR D4 D3 D2 111 P20 P27 SMR D6
P31 P32 P33 P00 P07
SMR2 D4 D3 D2 110
P31 P32 P33 P20 P21 P22
SMR2 D4 D3 D2 111
To RESET and WDT Circuitry (Active Low)
SMR2 D6
Figure 36. Stop-Mode Recovery Source PRELIMINARY 3-43
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FUNCTIONAL DESCRIPTION (Continued)
SCLK/TCLK Divide-by-16 Select (D0). D0 of the SMR controls a Divide-by-16 prescaler of SCLK/TCLK. The purpose of this control is to selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources interrupt logic). After Stop-Mode Recovery, this bit is set to a 0. External Clock divide-by-two (D1). This bit can eliminate the oscillator divide-by-two-circuitry. When this bit is 0, the System Clock (SCLK) and Timer Clock (TCLK) are equal to the external clock frequency divided-by-two. The SCLK/TCLK is equal to the external clock frequency when this bit is set (D1=1). Using this bit together with D7 of PCON further helps lower EMI (i.e., D7 (PCON)=0, D1 (SMR) = 1). The default setting is zero. Maximum external clock frequency is 4 MHz when SMR Bit D1=1 where SCLK/TCLK=XTAL. Note: When changing the system clock from either to or to divide-by-two or divide-by-16, you must follow the instruction with two NOP's in order to avoid clock conflicts during the internal system clock frequency change. Stop-Mode Recovery Source (D2, D3, and D4). These three bits of the SMR specify the wake up source of the STOP recovery (Figure 34 and Table 5). Table 5. Stop-Mode Recovery Source SMR: 432 D3 0 0 1 1 0 0 1 1 Operation Description of Action POR and/or external reset recovery Reserved P31 transition P32 transition P33 transition P27 transition Logical NOR of P20 through P23 Logical NOR of P20 through P27 Stop-Mode Recovery Delay Select (D5). This bit, if High, disables the 5 ms /RESET delay after Stop-Mode Recovery. The default configuration of this bit is one. If the "fast" wake up is selected, the Stop-Mode Recovery source needs to be kept active for at least 5TpC. Stop-Mode Recovery Edge Select (D6). A 1 in this bit position indicates that a High level on any one of the recovery sources wakes the Z86L7X from STOP mode. A 0 indicates Low level recovery. The default is 0 on POR (Figure 36). Cold or Warm Start (D7). This bit is set by the device upon entering STOP mode. A 0 in this bit (cold) indicates that the device will be reset by POR/WDT Reset. A 1 in this bit (warm) indicates that the device awakens by a SMR source. This is a READ only bit.
D4 0 0 0 0 1 1 1 1
D2 0 1 0 1 0 1 0 1
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Zilog Watch-Dog Timer Mode Register (WDTMR). The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WDT must initially be enabled by executing the WDT instruction and refreshed on subsequent executions of the WDT instruction. The WDT circuit is driven by an on-board RC oscillator or external oscillator from the XTAL1 pin. The WDT instruction affects the Zero (Z), Sign (S), and Overflow (V) flags. The POR clock source is selected with bit 4 of the WDT register. Bit 0 and 1 control a tap circuit that determines the
Z86L79/80 Low-Voltage Microcontroller time-out period. Bit 2 determines whether the WDT is active during HALT and Bit 3 determines WDT activity during STOP. Bits 5 through 7 are reserved (Figure 33). This register is accessible only during the first 64 processor cycles (64 internal system clocks) from the execution of the first instruction after Power-On-Reset, Watch-Dog Reset, or a Stop-Mode Recovery (Figure 40). After this point, the register cannot be modified by any means, intentional or otherwise. The WDTMR cannot be read and is located in Bank F of the Expanded Register Group at address location 0FH. It is organized as follows:
1
WDTMR (0F) F D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP 00 01* 10 11
INT RC OSC External Clock 5 ms 256 TpC 10 ms 512 TpC 20 ms 1024 TpC 80 ms 4096 TpC
WDT During HALT 0 OFF 1 ON * WDT During STOP 0 OFF 1 ON * XTAL1/INT RC Select for WDT 0 On-Board RC * 1 XTAL Reserved (Must be 0) * Default Setting After Reset
Figure 37. Watch-Dog Timer Mode Register (Write Only)
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FUNCTIONAL DESCRIPTION (Continued)
WDT Time Select (D0, D1). Selects the WDT time period. It is configured as shown in Table 6. Table 6. WDT Time Select Time-Out of Internal RC OSC 5 ms min 10 ms min 20 ms min 80 ms min Time-Out of XTAL Clock 256 TpC 512 TpC 1024 TpC 4096 TpC WDTMR During STOP (D3). This bit determines whether or not the WDT is active during STOP mode. Since the XTAL clock is stopped during STOP mode, the on-board RC has to be selected as the clock source to the WDT/POR counter. A 1 indicates active during STOP. The default is 1. Note: A WDT time-out during STOP mode will have the same effect like a recovery from any programmed STOP mode recovery source except the reset delay will occur. Clock Source for WDT (D4). This bit determines which oscillator source is used to clock the internal POR and WDT counter chain. If the bit is a 1, the internal RC oscillator is bypassed and the POR and WDT clock source is driven from the external pin, XTAL1. The default configuration of this bit is 0, which selects the RC oscillator. WDTMR During HALT (D2). This bit determines whether or not the WDT is active during HALT mode. A 1 indicates active during HALT. The default is 1.
D1 0 0 1 1
D0 0 1 0 1
Notes: TpC = XTAL clock cycle. The default on reset is 10 ms.
Note: The WDT can be permanently enabled through a mask programming option. The option is selected by the customer at the time of ROM code submittal. In this mode, WDT is always activated when the device comes out of reset. Execution of the WDT instruction serves to refresh the WDT time-out period. WDT operation in the HALT and STOP modes is controlled by WDTMR programming. If this mask option is not selected at the time of ROM code submission, the WDT must be activated by the user through the WDT instruction and is always disabled by any reset to the device.
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Z86L79/80 Low-Voltage Microcontroller
4 Clock Filter
Clear CLK
18 Clock RESET Generator
RESET
1
Internal RESET
WDT Select (WDTMR) CK Source Select (WDTMR) XTAL RC OSC. M U X
WDT TAP SELECT
5 ms POR 5 ms 15 ms 25 ms 100 ms CK WDT/POR Counter Chain CLR
VDD 2V REF . From Stop Mode Recovery Source WDT Stop Delay Select (SMR)
+ -
2V Operating Voltage Det.
12 ns Glitch Filter
Figure 38. Resets and WDT
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FUNCTIONAL DESCRIPTION (Continued)
Low Voltage Protection. An on-board Voltage Comparator checks that VCC is at the required level to ensure correct operation of the device. Reset is globally driven if VCC is below VLV (Low Voltage). The minimum operating voltage varies with the temperature and operating frequency, while VLV varies with temperature only. Mask Selectable Options. There are six Mask Selectable Options to choose from based on ROM code requirements. These are: Clock Source Port 0 Pull-ups (lower nibble) Port 0 Pull-ups (upper nibble) Port 2 Pull-ups Port 3 Pull-ups Mouse/Normal WDT Always On RC/Other On/Off On/Off On/Off On/Off M/N On/Off*
1.8 1.6 1.4 1.2 VLV 1 1.8 0.6 0.4 0.2 0 0 15 35 25 Temperature 45 55
VLV
The device functions normally at or above 2.0V under all conditions. Below 2.0V, the device is guaranteed to function normally until the Low Voltage Protection trip point VLV is reached, below which reset is globally driven and then the device is put in a low current stand by mode with the oscillator stopped. The device is guaranteed to function normally at supply voltages above the VLV trip point for the temperatures and operating frequencies in maximum VLV conditions. The actual VLV trip point is a function of temperature and process parameters (Figure 39).
*When WDT is selected as always on, the WDT will run in HALT or STOP mode regardless of the settings in the WDTMR Register Bits D2&D3. The Low Voltage trip voltage (VLV) is less than 2.1V under the following conditions: Maximum (VLV) Conditions: TA = 0C, +55C Internal clock frequency equal to or less than 4.0 MHz Note: The internal clock frequency is one-half the external clock frequency.
Figure 39. Typical Z86L7X Low Voltage vs. Temperature at 8 MHz
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Z86L79/80 Low-Voltage Microcontroller
EXPANDED REGISTER FILE CONTROL REGISTERS (0D)
CTR0 (0D) 0H D7 D6 D5 D4 D3 D2 D1 D0 0 P34 as Port Output* 1 Timer8 Output 0 Disable T8 Time Out Interrupt 1 Enable T8 Time Out Interrupt 0 Disable T8 Data Capture Interrupt 1 Enable T8 Data Capture Interrupt 00 01 10 11 R R W W SCLK on T8 SCLK/2 on T8 SCLK/4 on T8 SCLK/8 on T8 0 No T8 Counter Time Out 1 T8 Counter Time Out Occured 0 No Effect 1 Reset Flag to 0
1
0 Modulo-N 1 Single Pass R R W W 0 1 0 1 T8 Disabled * T8 Enabled Stop T8 Enable T8
* Default Setting After Reset
Figure 40. TC8 Control Register ((0D) 0H: Read/Write Accept Where Noted)
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CTR1 (0D) 1H D7 D6 D5 D4 D3 D2 D1 D0 Transmit Mode R/W 0 T16_OUT is 0 Initially 1 T16_OUT is 1 Initially Demodulation Mode R 0 No Falling Edge Detection R 1 Falling Edge Detection W W 0 No Effect 1 Reset Flag to 0
Transmit Mode* R/W 0 T8_OUT is 0 Initially 1 T8_OUT is 1 Initially Demodulation Mode 0 No Rising Edge Detection R 1 Rising Edge Detection R 0 No Effect W 1 Reset Flag to 0 W Transmit Mode 0 0 Normal Operation 0 1 Ping-Pong Mode 1 0 T16_OUT = 0 1 1 T16_OUT = 1 Demodulation Mode 0 0 No Filter 0 1 4 SCLK Cycle Filter 1 0 8 SCLK Cycle Filter 1 1 16 SCLK Cycle Filter Transmit Mode/T8/T16 Logic 0 0 AND 0 1 OR 1 0 NOR 1 1 NAND Demodulation Mode 0 0 Falling Edge Detection 0 1 Rising Edge Detection 1 0 Both Edge Detection 1 1 Reserved Transmit Mode 0 P36 as Port Output* 1 P36 as T8/T16_OUT Demodulation Mode 0 P31 as Demodulator Input 1 P20 as Demodulator Input Transmit/Demodulation Modes 0 Transmit Mode* 1 Demodulation Mode
Note: Care must be taken in differentiating Transmit Mode from Demodulation Mode. Depending on which of these two modes is operating, the CTR1 bit will have different functions. Note: Changing from one mode to another cannot be done without disabling the counter/timers. *Default setting after reset.
Figure 41. T8 and T16 Common Control Functions ((0D) 1H: Read/Write)
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EXPANDED REGISTER FILE CONTROL REGISTERS (0D) (Continued)
CTR2 (0D) 02H D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 P35 is Port Output* P35 is TC16 Output Disable T16 Time-Out Interrupt Enable T16 Time-Out Interrupt
0 Disable T16 Data Capture Interrupt 1 Enable T16 Data Capture Interrupt 00 01 10 11 R R W W 0 1 0 1 SCLK on T16 SCLK/2 on T16 SCLK/4 on T16 SCLK/8 on T16 No T16 Time Out T16 Time Out Occurs No Effect Reset Flag to 0
Transmit Mode 0 Modulo-N for T16 1 Single Pass for T16 Demodulator Mode 0 T16 Recognizes Edge 1 T16 Does Not Recognize Edge R R W W 0 1 0 1 T16 Disabled * T16 Enabled Stop T16 Enable T16
* Default Setting After Reset
Figure 42. T16 Control Register ((0D) 2H: Read/Write Except Where Noted)
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SMR (0F) 0B D7 D6 D5 D4 D3 D2 D1 D0 SCLK/TCLK Divide-by-16 0 OFF ** 1 ON External Clock DIvide By 2 0 SCLK/TCLK = XTAL/2* 1 SCLK/TCLK = XTAL Stop-Mode Recovery Source 000 POR Only* 001 Reserved 010 P31 0 11 P32 100 P33 101 P27 11 0 P2 NOR 0-3 111 P2 NOR 0-7 Stop Delay 0 OFF 1 ON* Stop Recovery Level 0 Low* 1 High Stop Flag 0 POR* 1 Stop Recovery** * Default Setting After Reset ** Default Setting After Reset and Stop-Mode Recovery
Figure 43. Stop-Mode Recovery Register ((F) 0BH: D6-D0 = Write Only,
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EXPANDED REGISTER FILE CONTROL REGISTERS (0D) (Continued)
SMR2 (0F) 0DH D7 D6 D5 D4 D3 D2 D1 D0 Reserved (Must be 0) Reserved (Must be 0) Stop-Mode Recovery Source 2 000 POR only* 001 NAND P20, P21, P22, P23 010 NAND P20, P21, P22, P23, P24, P25, P26, P27 011 NOR P31, P32, P33 100 NAND P31, P32, P33 101 NOR P31, P32, P33, P00, P07 110 NAND P31, P32, P33, P00, P07 111 NAND P31, P32, P33, P20, P21, P22 Reserved (Must be 0) Recovery Level 0 Low* 1 High Reserved (Must be 0) Note: If used in conjunction with SMR, either of the two specified events will cause a Stop-Mode Recovery. *Default Setting After Reset
Figure 44. Stop-Mode Recovery Register 2 ((0F) DH: D2-DH, D6 Write Only)
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WDTMR (0F) F D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP 00 01* 10 11
INT RC OSC External Clock 5 ms 256 TpC 10 ms 512 TpC 20 ms 1024 TpC 80 ms 4096 TpC
WDT During HALT 0 OFF 1 ON * WDT During STOP 0 OFF 1 ON * XTAL1/INT RC Select for WDT 0 On-Board RC * 1 XTAL Reserved (Must be 0) * Default Setting After Reset
Figure 45. Watch-Dog Timer Mode Register ((F) OFH: Write Only)
PCON (FH) 00H D7 D6 D5 D4 D3 D2 D1 D0 Comparator Output Port 3 0 P34, P37 Standard Output* 1 P34, P37 Comparator Output Reserved (Must be 1) * Default Setting After Reset
Figure 46. Port Configuration Register (PCON) ((0F) OH: Write Only)
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Z8(R) STANDARD CONTROL REGISTER DIAGRAMS
R247 P3M D7 D6 D5 D4 D3 D2 D1 D0
R249 IPR D7 D6 D5 D4 D3 D2 D1 D0
1
Interrupt Group Priority 000 Reserved 001 C > A > B 010 A > B > C 011 A > C > B 100 B > C > A 101 C > B > A 110 B > A > C 111 Reserved IRQ1, IRQ4 Priority (Group C) 0 IRQ1 > IRQ4 1 IRQ4 > IRQ1 IRQ0, IRQ2 Priority (Group B) 0 IRQ2 > IRQ0 1 IRQ0 > IRQ2 IRQ3, IRQ5 Priority (Group A) 0 IRQ5 > IRQ3 1 IRQ3 > IRQ5 Reserved (Must be 0)
0 Port 2 Open-Drain* 1 Port 2 Push-pull 0 Digital 1 Analog 0 P32 = Input* P35 = Output** 1 P32 = /DAV0/RDY0 P35 = RDY0//DAV0 Reserved (Must be 0)
Effects P34 and P35 as well * Default setting after reset ** Output status controlled by P3M, D0
Figure 47. Port 3 Mode Register (F7H; Write Only)
R248 P01M D7 D6 D5 D4 D3 D2 D1 D0
Figure 49. Interrupt Priority Registers ((0) F9H: Write Only
P00-P03 Mode 00 Output 01 Input* 1X A11-A8 Reserved (Must be 1) Reserved (Must be 0) P07-P04 Mode 00 Output 01 Input* 1X A15-A12
R250 IRQ D7 D6 D5 D4 D3 D2 D1 D0
IRQ0 = P32 Input IRQ1 = P33 Input IRQ2 = P31 Input IRQ3 = Software Controlled IRQ4 = T0 (L03 Software only) IRQ5 = T1 Inter Edge 00 P31 P32 01 P31 P32 10 P31 P32 11 P31 P32
* Default Setting After Reset.
Figure 48. Port 0 and 1 Mode Register (F8H: Write Only)
Figure 50. Interrupt Request Register ((0) FAH: Read/Write)
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Z8(R) STANDARD CONTROL REGISTER DIAGRAMS (Continued)
R251 IMR D7 D6 D5 D4 D3 D2 D1 D0
R246 P2M D7 D6 D5 D4 D3 D2 D1 D0
1 Enables IRQ4-IRQ0 (D0 = IRQ0) Reserved (Must be 0) Reserved (Must be 0) 0 Master Interrupt Disable* 1 Master Interrupt Enable * Default Setting After Reset
P27-P20 I/O Definition 0 Defines Bit as OUTPUT 1 Defines Bit as INPUT* *Default Setting After Reset
Figure 54. Port 2 Mode Register (F6H: Write Only)
Figure 51. Interrupt Mask Register ((0) FBH: Read/Write)
R254 RP D7 D6 D5 D4 D3 D2 D1 D0
R252 Flags D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer Upper Byte (SP15-SP8)
User Flag F1 User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag
Figure 55. Stack Pointer High ((0) FEH: Read/Write)
R255 SPL D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer Lower Byte (SP 0 - SP 7 )
Figure 52. Flag Register ((0) FCH: Read/Write)
Figure 56. Stack Pointer Low ((0) FFH: Read/Write)
R253 RP D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register File Pointer Default Setting After Reset = 0000 0000 Working Register Pointer
Figure 53. Register Pointer ((0) FDH: Read/Write)
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PACKAGE INFORMATION
1
Figure 57. 28-Pin DIP Package Diagram
Figure 58. 28-Pin SOIC Package Diagram
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ORDERING INFORMATION Z86L79/80
8.0 MHz 28-pin DIP Z86L7908PSC Z86L8008PSC 28-pin SOIC Z86L7908SSC Z86L8008SSC
Temperature
S = 0C to +70C
Speed
8 = 8.0 MHz
For fast results, contact your local Zilog sales office for assistance in ordering the part desired.
Environmental
C = Plastic Standard
Codes Package
P = Plastic DIP S = SOIC
Example:
Z 86L79/80 08 P S C is a Z86L79/80, 8 MHz, DIP, 0C to +70C, Plastic Standard Flow Environmental Flow T emperature Package Speed Product Number Zilog Prefix
(c) 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com
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