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PRELIMINARY PRODUCT SPECIFICATION
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Z87000/Z87L00
SPREAD SPECTRUM CONTROLLERS
FEATURES
Device Z87000 Z87L00 ROM (KWords) 12 12 RAM* I/O (Words) Lines 512 512 32 32 Package Information 84-Pin PLCC 100-Pin QFP 100-Pin QFP
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Note: *General-Purpose s
Transceiver Circuitry Provides Primary Cordless Phone Communications Functions - Digital Downconversion with Automatic Frequency Control (AFC) Loop - FSK Demodulator - FSK Modulator - - Symbol Synchronizer Time Division Duplex (TDD) Transmit and Receive Buffers
Transceiver/Controller Chip Optimized for Implementation of 900 MHz Spread Spectrum Cordless Phone - Adaptive Frequency Hopping - Transmit Power Control - Error Control Signaling - Handset Power Management - Support of 32 kbps ADPCM Speech Coding for High Voice Quality DSP Core Acts as Phone Controller - Zilog-Provided Embedded Transceiver Software to Control Transceiver Operation and Base StationHandset Communications Protocol - User-Modifiable Software Governs Phone Features
s s s s
On-Chip A/D and D/A to Support 10.7 MHz IF Interface Bus Interface to Z87010 ADPCM Processor Static CMOS for Low Power Consumption 3.0V to 3.6V, -20C to +70C, Z87L00 4.5V to 5.5V, -20C to +70C, Z87000 16.384 MHz Base Clock
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GENERAL DESCRIPTION
The Z87000/Z87L00 FHSS Cordless Telephone Transceiver/Controllers are expressly designed to implement a 900 MHz frequency hopping spread spectrum cordless telephone compliant with United States FCC regulations for unlicensed operation. The Z87000 and Z87L00 are distinct 5V and 3.3V versions, respectively, of the device. For the sake of brevity, all subsequent references to the Z87000 in this document also apply to the Z87L00, unless specifically noted. The Z87000 supports a specific cordless phone system design that uses frequency hopping and digital modulation to provide extended range, high voice quality, and low system costs.The Z87000 uses a Zilog 16-bit fixed-point two's complement static CMOS Digital Signal Processor core as the phone and RF section controller. The Z87000's DSP core processor further supports control of the RF section's frequency synthesizer for frequency hopping and the generation of the control messages needed to coordinate incorporation of the phone's handset and base station.
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GENERAL DESCRIPTION (Continued)
Additional on-chip transceiver circuitry supports Frequency Shift Keying modulation/demodulation and multiplexing/demultiplexing of the 32 kbps voice data and 4 kbps command data between handset and base station. The Z87000 provides thirty-two I/O pins, including four wakeup inputs and two CPU interrupt inputs. These programmable I/O pins allow a variety of user-determined phone features and board layout configurations. Additionally, the pins may be used so that phone features and interfaces are supported by an optional microcontroller rather than by the Z87000's DSP core. In combination with an RF section designed according to the system specifications, Zilog's Z87010/Z87L10 ADPCM Processor, a standard 8-bit PCM telephone CODEC and minimal additional phone circuity, the Z87000 and its embedded software provide a total system solution.
CODEC
CODEC Z87010 ADPCM Processor Z87000 Spread Spectrum Controller RF Section RF Section Z87000 Spread Spectrum Controller Z87010 ADPCM Processor
Telephone Line Interface
Base Station
Handset
Figure 1. System Block Diagram of a Z87000/Z87010 Based Phone
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Z87000/Z87L00 Spread Spectrum Controllers
RX VREF
ADC (1-bit)
FSK Demodulator (downconverter, limiter discriminator, AFC, bit sync, frame sync, SNR detector)
Receive Rate Buffer
Z87010 Interface
VXDATA[7..0] VXADD[2..0] VXSTRB VXRWB VXRDYB CLKOUT CODCLK
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TX
DAC (4-bit)
FSK Modulator
Transmit Rate Buffer
RXON RFRX RFTX RFEON SYLE Frame Counter(s), Event Trigger, T/R Switch Ctrl, Power On/Off Ctrl, Antenna Select
256 Word RAM 0
256 Word RAM 1
Port 0
P0[15..0]
RSSI
ADC (8-bit) DAC (4-bit)
DSP Core
PWLV ANT0 ANT1 HBSW RESETB TEST
12K Words Program ROM
Port 1
P1[15..0]
Analog Power Digital Power
AVDD AGND VDD GND
Figure 2. Z87000 Functional Block Diagram
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PIN DESCRIPTION AVDD RSSI PWLV AGND RFRX RXON SYLE RFTX VDD MCLK GND /RESETB CODCLK VXADD0 VXADD1 VXADD2 VDD VXRWB VXSTRB VXRDYB GND TX AGND RX AVDD VREF RFEON P115 GND P114 P113 P112 VDD P111 P110 P19 GND P18 P17 P16 VDD P15
12 1 75
Z87000
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VXDATA0 VXDATA1 VXDATA2 VDD VXDATA3 VXDATA4 VXDATA5 VXDATA6 VXDATA7 CLKOUT HBSW GND TEST VDD ANT0 ANT1 P00 P01 GND P02 P03
Figure 3. 84-Pin PLCC ROM Pin Configuration (Z87000 only)
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P14 P13 P12 GND P11 P10 P015 P014 VDD P013 P012 P011 P010 GND P09 P08 P07 P06 VDD P05 P04
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Zilog Table 1. 84-Pin PLCC Pin Description Summary Pin Number 1,19,27,36,46, 56,63,75 2 3,23,31,41,51, 61,71,79 4 5 6 7 8,13 9 10 11,15 12 14 16 17 18,20,21,22,24, 25,26,28,29,30, 32,33,34,35,37,38 59,60 62 64 65 76 77 78 80,81,82 83 84 GND MCLK VDD RFTX SYLE RXON RFRX AGND PWLV RSSI AVDD TX RX VREF RFEON P115 Symbol Ground Master clock (16.384 MHz) Digital RF transmit switch control RF synthesizer load enable Demodulator "on" indication RF receive switch control Analog ground RF transmit power level RF receive signals strength indicator Analog VDD Analog transmit IF signal Analog receive IF signal Analog reference voltage for RX signal RF module on/off control General-purpose Function
Z87000/Z87L00 Spread Spectrum Controllers
Direction - Input - Output Output Output Output - Output Input - Output Input Output Output Input
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ANT1 TEST HBSW CLKOUT VXRDYB VXSTRB VXRWB VXADD2 CODCLK /RESETB
RF diversity antenna control Main test mode control Handset/Base Control Clock output to ADPCM Processor ADPCM processor ready signal ADPCM processor data strobe ADPCM read/write control ADPCM processor address bus Clock output to codec Reset signal
Input/Output Input - Output Output Input Input Input Output Input
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PIN DESCRIPTION (Continued)
RSSI PWLV AGND RFRX RXON SYLE RFTX VDD MCLK GND N/C RESETB CODCLK VXADD0 VXADD1 VXADD2 VDD VXRWB VXSTRB VXRDYB AVDD N/C N/C N/C TX AGND RX AVDD VREF RFEON P115 GND P114 P113 N/C P112 VDD P111 P110 P19 GND P18 P17 P16 VDD P15 N/C N/C N/C P14
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GND N/C N/C N/C VXDATA0 VXDATA1 VXDATA2 VDD VXDATA3 VXDATA4 VXDATA5 VXDATA6 VXDATA7 CLKOUT N/C HBSW GND TEST VDD ANT0 ANT1 P00 P01 GND P02 P03 N/C N/C N/C P04
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P13 P12 GND P11 P10 P015 P014 VDD P013 N/C P012 P011 P010 GND P09 P08 P07 P06 VDD P05
Figure 4. 100-Pin QFP Pin Configuration PRELIMINARY
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Zilog Table 2. 100-Pin QFP Pin Configuration No 1,8 2,3,4,15,27,28, 29,40,52,53,54, 66,77,78,79,90 5 6,98 7 9 10 11,13,14,16,18, 19,20,22,23,23, 26,30,31,32,34,35 17,25,38,49,62, 73,84,93 36,37,39,41,42, 43,45,46,47,48, 50,51,55,56,58,59 60,61 63 65 67 68,69,70,71,72, 74,75,76 81 82 83 85,86,87 88 89 92 94 95 96 97 99 100 Symbol AVDD N/C Analog VDD No connection Function
Z87000/Z87L00 Spread Spectrum Controllers
Direction - -
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TX AGND RX VREF RFEON P1[15..0]
Analog transmit IF signal Analog ground Analog receive IF signal Analog reference voltage for RX signal RF module on/off control General-purpose I/O port 0
Output - Input - Output Input
VDD P0[15..0]
Digital General-purpose I/O port 0
- Input
ANT[1..0] TEST HBSW CLKOUT VXDATA[7..] VXRDYB VXSTRB VXRWB VXADD[2..0] CODCLK /RESETB MCLK RFTX SYLE RXON RFRX PWLV RSSI
RF diversity antenna control Main test mode control Handset/bast control Clock output to ADPCM processor ADPCM processor data bus ADPCM processor ready signal ADPCM processor data strobe ADPCM processor read/write control ADPCM processor address bus Clock output to codec Reset signal Master clock input (16.384 MHz) RF transmit switch control RF synthesizer load enable Demodulator "on" indication RF receive switch control RF transmit power level RF receive signal strength indicator
Input/Output Input Input Output Input Output Input Input Input Output Input Input Output Output Output Output Input Input
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ABSOLUTE MAXIMUM RATINGS
Symbol Parameter VDD, AVDD DC Supply Voltage(1) VIN Input Voltage(2) VOUT TA TSTG Output Voltage(3) Operating Temperature Storage Temperature Min -0.5 Max 7.0 Units V V V C C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended period may affect device reliability.
-0.5 VDD + 0.5 -0.5 VDD + 0.5 -20 -65 +70 +150
Notes: 1. Voltage on all pins with respect to GND. 2. Voltage on all inputs WRT VDD 3. Voltage on all outputs WRT VDD
STANDARD TEST CONDITIONS
The electrical characteristics listed below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to GND. Positive current flows into the referenced pins. Standard test conditions are as follows:
s s s s
IoL
3.0V < VDD < 3.6V (Z87L00) 4.5V < VDD < 5.5V (Z87000) GND = 0V TA = -20 to +70 C
Threshold Voltage
Output Under Test
50pF
IoH
Figure 5. Test Load Diagram
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RECOMMENDED OPERATING CONDITIONS
Table 3. 5V 0.5V Operation (Z87000) Symbol VDD, AVDD VIH VIL IOH IOL1 IOL2 TA Supply Voltage Input High Voltage Input Low Voltage Output High Current Output Low Current Output Low Current, Ports (limited usage, 1) Operating Temperature -20 Parameter Min 4.5 2.0 GND -0.3 Max 5.5 VDD + 0.3 0.8 -2.0 4.0 12.0 +70 Units V V V mA mA mA C
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Notes: 1. Maximum 3 pins total from P0[15..0] and P1[15..0]
Table 4. 3.3V 0.3V Operation (Z87L00) Symbol VDD VIH VIL IOH IOL1 IOL2 TA Supply Voltage Input High Voltage Input Low Voltage Output High Current Output Low Current Output Low Current, Ports (limited usage, 2) Operating Temperature -20 Parameter Min 3.0 0.7 VDD GND -0.3 Max 3.6 VDD+0.3 0.1 VDD -1.0 2.0 6.0 +70 Units V V V mA mA mA C
Notes: 1. Maximum 3 pins total from P0[15..0] and P1[15..0]
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DC ELECTRICAL CHARACTERISTICS
Conditions for DC characteristics are corresponding operating conditions, and standard test conditions, unless otherwise specified. Table 5. 5V 0.5V Operation (Z87000) Symbol VOH VOL1 VOL2 IL ICC ICC2 Parameter Output High Voltage Output Low Voltage Output Low Voltage, Ports (1) Input Leakage Supply Current Standby Mode Current (2) Test Condition VDD min, IOH max VDD min, IOL1 max VDD min, IOL2 max VIN = 0V, VDD -2 Min 2.4 0.6 1.2 2 80 4 Max Units V V V A mA mA
Notes: 1. Maximum 3 pins total from P0[15..0] and P1[15..0] 2. 2.3 mA typical at 25C, 5 volts.
Table 6. 3.3V 0.3V Operation (Z87L00) Symbol VOH VOL1 VOL2 IL ICC ICC2 Parameter Output High Voltage Output Low Voltage Output Low Voltage, Ports(1) Input Leakage Supply Current Standby Mode Current(2) 1.4 Test Condition VDD min, IOH max VDD min, IOL1 max VDD min, IOL2 max VIN = 0V, VDD -2 Min 1.6 0.4 1.2 2 55 Max Units V V V A mA mA
Notes: 1. Maximum 3 pins total from P0[15..0] and P1[15..0] 2. 1.6 mA typical at 25C, 3.3 volts.
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ANALOG CHARACTERISTICS
Table 7. 1-Bit ADC (Temperature: -20/+70C) Parameter Resolution Power dissipation Power dissipation, Stop mode Sample frequency Sample window(1) Bandwidth Supply Range(=AVDD) Z87L00 Z87000 Acquisition time Settling time Conversion time Aperture delay Aperture uncertainty(2) Input voltage range (p-p) Reference voltage Z87L00 Z87000 Input resistance Input capacitance Minimum 0.54 (70c) 0.06 (70c) 29 3.0 4.5 2 8 4 2 800 3 10 6 3 1000 Typical 1 1.0 (40c) 0.2 (40c) 8.192 31 60 Maximum 2.75 (-20c) 1.1 (-20c) 33 3.6 5.5 8 18 18 8.5 0.5 1200 Units bit mW mW MHz ns MHz V V ns ns ns ns ns mV V V KOhm pF
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1.7 (AVDD= 3V) 1.9 (AVDD= 3.3V) 2.1 (AVDD= 3.6V) 2.7 (AVDD=4.5V) 3.0 (AVDD= 5V) 3.3 (AVDD= 5.5V) 10 18 10 25 -
Notes: Window of time while input signal is applied to sampling capacitor; see next figure. Uncertainty in sampling time due to random variations such as thermal noise.
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ANALOG CHARACTERISTICS (Continued)
CLK (16.384MHz) Aperture Delay SAMPLING WINDOW Latched Output INPUT SIGNAL Acquisition Time Settling + Conversion Time (for Time digital output)
Sampling
Figure 6. 1-Bit ADC Definition of Terms
Table 8. 8-bit ADC (Temperature -20/+70C) Parameter Resolution Integral non-linearity Differential non-linearity Power Dissipation (peak) Sample window Bandwidth Supply Range (=AVDD) Z87L00 Z87000 Input voltage range Conversion time Aperture delay Aperture uncertainty Input resistance Input capacitance
Notes: 1. 8-bit ADC only tested for 6-bit resolution.
Minimum 5 3.0 4.5 0.5 2 -
Typical 6 0.5 35 3.3 5.0 0-AVDD 3 25 10
Maximum 1 0.5 70 120 2 3.6 5.5 8.5 1 -
Units bit LSB LSB mW ns Msps V V V s ns ns Kohm pF
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Zilog Table 9. 4-bit DAC (Temperature: -20/+70C) Parameter Resolution Integral non-linearity Differential non-linearity Settling time (1/2 LSB) Zero error at 25C Conversion time (input change to output change) Power dissipation, 25 pF load Power dissipation, 25 pF load, Stop mode Conversion time (input change to output change) Rise time (full swing) Output slew rate Output voltage range Supply Range (=AVDD) Z87L00 Z87000 Output load resistance Output load capacitance Minimum 14 1.2 (70c) 0.18 (70c) 14.5 11 8 3.0 4.5 Typical
Z87000/Z87L00 Spread Spectrum Controllers
Maximum 0.5 1 22.5 2 76 24.1 (-20c) 1.1 (-20c) 75.8 71 96 3.6 5.5 -
Units bit LSB LSB ns mV ns mW mW ns ns V/s V V V Ohm pF
4 0.25 0.25 1 19 20 (40c) 1.0 (40c) 19.1 15 67 0.2 AVDD to 0.6AVDD 3.3 5.0 330 25
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INPUT/OUTPUT PIN CHARACTERISTICS
All digital pins (all pins except VDD, AVDD, GND, AGND, VREF, RX, TX, RSSI and PWLV) have an internal capacitance of 5 pF. The RX analog input pin has an input capacitance of 10 pF. The RSSI analog input pin has an input capacitance of 10 pF.
AC ELECTRICAL CHARACTERISTICS Clocks, Reset and RF Interface
Table 10. Clocks, Reset and RF Interface No. 1 2 3 4 5 6 7 Symbol TpC TwC TrC, TfC TrCC, TfCC TrCO, TfCO TwR TrRF, TfRF Parameter MCLK input clock period (1) MCLK input clock pulse width MCLK input clock rise/fall time CLKOUT output clock rise/fall time CODCLK output clock rise/fall time RESETB input low width RF output controls rise/fall time (2) Min 61 20 2 2 18 2 Max 61 40 15 6 6 6 Units ns ns ns ns ns TpC ns
Notes: 1. MCLK is 16.384 MHz 25 ppm 2. RF Controls are RFTX, RFRX, RXON, RFEON, SYLE.
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Z87000/Z87L00 Spread Spectrum Controllers READ CYCLES refer to data transfers from the Z87000 to the ADPCM Processor. WRITE CYCLES refer to data transfers from the ADPCM Processor to the Z87000.
ADPCM Processor Interface
The Z87000 is a peripheral device for the ADPCM Processor. The interface from the Z87000 perspective is composed of an input address bus, a bidirectional data bus, strobe and read/write input control signals and a ready/wait output control signal.
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Table 11. Read Cycles Signal Name VXADD[2..0] VXDATA[7..0] VXSTRB VXRWB VXRDYB Function Address Bus Data Bus Strobe Control Signal Read/Write Control Signal Ready Control Signal Direction ADPCM Proc. to Z87000 Bidirectional ADPCM Proc. to Z87000 ADPCM Proc. to Z87000 Z87000 to ADPCM Proc.
Table 12. Write Cycles No. 8 9 10 11 12 13 14 15 16 Symbol TsAS ThSA TaDrS ThDrS TwS TsDwS ThDwS TaDrRY TdSRY Parameter Address, Read/Write setup time before Strobe falls Address, Read/Write hold time after Strobe rises Data read access time after Strobe falls Data read hold time after Strobe rises Strobe pulse width Data write setup time before Strobe rises Data write hold time after Strobe rises Data read valid before Ready falls Strobe high after Ready falls Min 10 3 8.5 20 10 3 22 0 30 (1) 40 (2) Max Units ns ns ns ns ns ns ns ns
Notes: 1. Requires wait state on ADPCM Processor read cycles 2. Requires no write cycle directly following read cycle on ADPCM Processor
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AC TIMING DIAGRAMS
TwC(2)
MCLK
TrC(3) TfC(3) TpC (1)
CLKOUT
TrCC(4) TfCC(4)
CODCLK
TrCO(5) TfCO(5)
1
2
3
4
16
17
18
MCLK RESETB
TwR(6)
RFTX RFRX RXON RFEON SYLE
TrRF(7)
TfRF(7)
Figure 7. Transceiver Output Signal
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TsAS(8)
ThSA(9)
VXADD VXRWB
1
VXSTRB
TaDrS(10) ThDrS(11)
VXDATA
VXRDYB VXDATA Read Cycle
TsAS(8)
ThSA(9)
VXADD VXRWB
TwS(12)
VXSTRB
ThDwS(14) TsDwS(13)
VXDATA
VXRDYB VXDATA Write Cycle
Figure 8. Read/Write Cycle TImings
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AC TIMING DIAGRAMS (Continued)
TsAS(8)
ThSA(9)
VXADD VXRWB
VXSTRB
ThDrS(11)
VXDATA
TaDrRY(15) TdSRY(16)
VXRDYB VXDATA Read Cycle with Wait State
TsAS(8)
ThSA(9)
VXADD VXRWB
TwS(12)
VXSTRB
TsDwS(13)
ThDwS(14)
VXDATA
TdSRY(16)
VXRDYB
VXDATA Write Cycle with Wait State
Figure 9. Read/Write Cycle Timing with Wait State
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PIN FUNCTIONS
VDD. Digital power supply. GND. Digital ground. AVDD. Analog power supply. AGND. Analog ground. VREF (analog reference). This signal is the reference voltage used by the high speed analog comparator to sample the RX input signal. RX (analog input). This is the RX IF receive signal from the RF module, input to the analog comparator and FSK demodulator. It is internally biased to the VREF DC voltage. The IF signal from the RF module should be AC coupled to the RX pin. TX (analog output). This is the IF transmit signal to the RF module, output from the FSK modulator and transmit 4-bit D/A converter. RXON (output; active high or low programmable). This pin reflects the programming of the demodulator turn-on time. RFRX (output; active high or low programmable). Control for the receive switch on the RF module. Active during receive periods. RFTX (output; active high or low programmable). Control for the transmit switch on the RF module. Active during transmit periods. RFEON (output; active high or low programmable). On/off control for the RF module. Active (on) during wake periods. Inactive (off) during sleep periods on the handset. RSSI (analog input). Receive signal strength indicator from RF module, input to the RSSI 8-bit ADC. PWLV (analog output). Power level control for RF module, output from the transmit power 4-bit DAC. SYLE (output). RF synthesizer load enable: latches new frequency hopping control word of external RF synthesizer. Programmable polarity. ANT[1..0] (output). Control for optional antenna diversity on the RF module. MCLK (input). Master clock input. CODCLK (output). Clock output for external voice CODEC. /RESETB (input, active low). Reset signal. VXADD[2..0] (input). Address bus controlled by external ADPCM processor. The Z87000 acts as peripheral of the Z87010 ADPCM processor. VXDATA[7..0](input/output). Read/write data bus controlled by external Z87010 ADPCM processor. VXSTRB (input). Data strobe signal for the VXDATA bus, controlled by external Z87010. VXRWB (input). Read/write control for the VXDATA bus, controlled by external Z87010. VXRDYB (output, active low). Ready control for the VXDATA bus. This signal is driven high (de-asserted) by the Z87000 to insert wait states in the Z87010 ADPCM processor accesses. TEST (input, active high). Main test mode control. Must be set to GND. HBSW (input with internal pull-up). Control for handset/base configuration. Must be driven high or not connected for handset, low for base. P0[15..0] (input/output). General-purpose I/O port. Direction is bit-programmable. Pins P0[3..0],when configured in input mode, can also be individually programmed as wakeup pins for the Z87000 (wake-up active low; signal internally debounced and synchronized to the bit clock). P0 0 P0 1 P0 2 P0 3 WAKEUP0 WAKEUP1 WAKEUP2 WAKEUP3 CLKOUT (output). Clock output for external ADPCM processor.
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P1[15..0] (input/output).General-purpose I/O port. Direction is bit-programmable. Pins P114 and P115, when configured in input mode, also behave as individually maskable interrupt pins for the core processor (positive edge-triggered). P1 14 P1 15 INT0 INT2
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FUNCTIONAL DESCRIPTION
The functional partitioning of the Z87000 is shown in Figure 2. The chip consists of a receiver, a transmitter, and several additional functional blocks. The receiver consists of the following blocks:
s s s
Transmit 4-Bit DAC In Addition, there are the following Shared Blocks.
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Receive 1-bit ADC Demodulator, including: - IF Downconverter - AFC (Automatic Frequency Control) - Limiter-Discriminator - Matched Filter - Bit Synchronizer - Bit Inversion - Frame Synchronizer (unique word detector) - SNR Detector Receive Frame Timing Counter
Event Trigger Block, Controlling: - Transmit/Receive Switch - Power On/Off Switches (Modulator, Demodulator, RF Module) - Antenna Switch Control (used on Base Station only for Antenna Diversity) 4-Bit DAC for Setting Transmit Power Level 8-Bit ADC for Sampling the Received Signal Strength Indicator (RSSI) DSP Core Processor Two 16-Bit General-Purpose I/O Ports Z87010 ADPCM Processor Interface
s s
s s s
s s
Receive Buffer and Voice Interface The Transmitter Consists of the Following Blocks:
s s
Basic Operation
The transmitter and receiver operate in time-division duplex (TDD): handset and base station transmit and receive alternately. The TDD duty cycle lasts 4 ms and consists of the following events:
s
Transmit Buffer and Voice Interface Transmit Frame Timing Counter (used on base station only) Modulator, including: - NCO - Bit Inversion
s
At the beginning of the cycle, the frequency is changed (hopping) The base station transmits a frame of 144 bits while the handset receives The handset then transmits a frame of 148 bits while the base receives.
s
s
4ms frame HOP
144 bits
148 bits
BASE
Frequency Hopping guard time
TX
TDD switching guard time
RX
HANDSET
RX
TX
Figure 1. Basic Time Duplex Timing
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Receive 1-Bit ADC
The incoming receive signal at the RX analog input pin is sampled by a 1-bit analog-to-digital converter at 8.192 MHz. The receive signal is FSK-modulated (Frequency Shift Keying) with a carrier frequency of 10.7 MHz (Intermediate Frequency, or IF). The instantaneous frequency varies between 10.7 MHz plus or minus 32.58 kHz. Since the data rate is 93.09 kbps, there are 88 samples per data bit. This oversampled data is further processed by the demodulator to retrieve the baseband information. The 1-bit converter is implemented with a fast comparator, which determines whether the RX signal is larger or smaller than a reference signal (VREF). The Z87000 internally generates the DC level of both VREF and RX input pins. The received signal at 10.7 MHz should thus be AC coupled to the RX pin via a coupling capacitor. To ensure accurate operation of the converter, the user should also attach to the VREF pin a network whose impedance matches the DC impedance seen by the RX pin.
Demodulator
The demodulator includes a two-stage IF downconverter that brings the sampled receive signal to baseband. The narrow-band 10.7 MHz receive signal, sampled at 8.192 MHz by the 1-bit ADC, provides a 2.508 MHz useful image. The first local oscillator used to downconvert this IF signal is obtained from a Numerically Controlled Oscillator (NCO) internal to the Z87000, at the nominal frequency of 460 kHz. The resulting signal is thus at 2.048 MHz (= 2.508 MHz - 460 kHz). A second downconversion by a 2.048 MHz signal brings the receive signal to baseband. The exact frequency of the 460 kHz NCO is slightly adjusted by the Automatic Frequency Control (AFC) loop for exact downconversion of the end signal to the zero frequency. The AFC circuit detects any DC component in the output of the limiter-discriminator (see below) when receiving a known sequence of data (preamble). This DC component is called the "frequency bias". The bias estimate out of the AFC can be read by the DSP processor on every frame and subsequently filtered. The processor then adds or subtract this filtered bias to/from the NCO control word to correct the NCO frequency output.
1
SNR
SSB Rx signal 1-bit ADC 460 kHz + bias Filter LimiterDiscriminator Bit Sync Frame Sync
2.048 MHz
Rx Buffer AFC
NCO
Figure 2. Demodulator Block Diagram
The main element of the demodulator is its limiter-discriminator. The limiter-discriminator detects the frequency variations (ideally up to 32.58 kHz) and converts them to "0" or "1" information bits. First, the data is processed through low-pass filters to eliminate high frequency spurious components introduced by the 1-bit ADC. The resulting signal is then differentiated and fed to a matched filter. In the matched filter, an integrate-and-dump operation is performed to extract the digital information from its background noise.
The symbol clock is provided by the bit synchronizer. The bit synchronizer circuit detects 0-to-1 and 1-to-0 transitions in the incoming data stream in order to synchronize a digital phase-lock loop (DPLL). The PLL output is the recovered bit clock, used to time the receiver on the base station, and both receiver and transmitter on the handset. To ensure enough transitions in the voice data stream, a pseudo-random bit inversion operation is performed on the outgoing voice data. The inversion is then reversed on the demodulated data.
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FUNCTIONAL DESCRIPTION (Continued)
Since the data is packed in frames sent alternately from base and handset every 4 ms (TDD), additional synchronization means are necessary. This is realized in a frame synchronizer, based on detection of a "unique word" following the preamble. The receiver also features a signal-to-noise ratio detector, which allows the DSP software to detect noisy channels and eliminate them from the frequency hopping cycle. The SNR information is also used by the Z87000 software as a measure the current range between handset and base station. This information allows the adaptive power control algorithm to provide sufficient output power to the RF transmitter.
Transmit Rate Buffer and Voice Interface
The transmit rate buffer stores the data to be modulated. The data is sourced from the Z87010 or the Z87000 core processor. As for the receive rate buffer, the Z87010 sees a unique pipe to write to, while the Z87000 DSP core accesses the rate buffer as random-access memory. The modulator reads from the rate buffer as from a circular buffer.
Transmit Frame Timing Counter
On the handset, transmission does not start until the receiver has synchronized itself to the signal received from the base station. The transmission timing is based on the recovered clock. No additional counter is necessary. On the base station, the situation is different. Transmission timing is based on a local clock, while the reception's timing is based on the clock recovered from the incoming received signal. Two counters, respectively clocked by local and recovered clocks, are necessary to track the transmit and receive signals. Note that the receive clock on the base station tracks the handset's transmit clock, which is also the handset's receive clock and tracks the transmit clock of the base station. As a result, receive and transmit clocks of the base station have exactly the same frequency; only their phases differ.
Receive Frame Counter
The receive frame counter is responsible to keep track of time within the frame. It is initialized by the frame synchronizer logic on detection of the unique word. It is then clocked by the recovered bit clock from the bit synchronizer. On the base station, the receive frame counter is used as time base for the receiver. On the handset, it is used as time base for both receiver and transmitter.
Receive Rate Buffer and Voice Interface
The voice signal is generated at the fixed rate of 32 kips by the Z87010 processor, and transmitted/received in bursts of 93.09 kips across the air. Data buffers in the transmitter and receiver are thus necessary to absorb the rate differences over time. These buffers are called "rate buffers". They can store up to 144 data bits and are organized as an array of 36 4-bit nibbles. The receive rate buffer stores the received data from the demodulator. Incoming bits are arranged in 4-bit nibbles and transferred to successive locations of the rate buffer. When the last location is reached, transfers resume from the beginning (circular buffer). The system design guarantees that no buffer overrun nor enduring can occur. The receive rate buffer can be read by the DSP core processor of the Z87000 or by the Z87010 chip. On the Z87000 side, the buffer can be read as a random-access memory: the processor writes the nibble address in an address register and reads the 4-bit data from a data register. On the Z87010 side, a voice processor interface logic handles the addressing to automatically present the successive voice nibbles to the Z87010 in the order they were received.
Modulator
The modulator consists of a numerically controlled oscillator (NCO) which generates an FSK (Frequency Shift Keying) signal at the carrier frequency of 2.508 MHz. The carrier frequency is shifted plus or minus 32.58 kHz for a "1" or a "0" data bit. To facilitate conformance to FCC regulations, the transitions from "1" to "0" or vice-versa are smoothed in order to decrease the amplitude of the side lobes of the transmit signal. In practice, the jump from one frequency to the next is performed in several smaller steps. The carrier frequency is adjustable by the DSP core processor in order to provide additional frequency adjustment between base and handset. This is provided in case of a frequency offset too large for possible correction by the AFC. The modulator also includes bit inversion logic as discussed in the receiver section.
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Tx signal 4-bit DAC NCO Tx Buffer
Z87000/Z87L00 Spread Spectrum Controllers
Spectral Shaping
1
Figure 3. Modulator Block Diagram
Transmit 4-Bit DAC
The transmit DAC clocks one new NCO value out of the Z87000 every 8.192 MHz period. Only the 10.7 MHz alias frequency component of the transmit signal (2.508 + 8.192 MHz image) is filtered, amplified and upconverted to the 900 MHz ISM band by the companion RF module.
8-Bit ADC for Sampling the Received Signal Strength Indicator (RSSI)
RSSI information is typically generated from the last stage of the RF receiver. The RSSI is sampled once per frame by the 8-bit ADC and used by the Z87000 software to compute the necessary Transmit Power Level voltages.
Event Trigger Block
The event trigger block is responsible for scheduling the different events happening at the bit and frame levels. The event trigger block receives input from the frame counters as well as the register interface of the DSP core processor. The event trigger schedules the following events:
DSP Core Processor
A DSP core processor constitutes the heart of the Z87000. The DSP runs the application software which performs the following functions:
s s
Register initialization Implementation of high-level phone features; control of phone user interface (keypad, Led, etc.) Control of the Z87010 ADPCM Processor Control of the phone line interface Ring detection by DSP processing Communication protocol between handset and base station supporting voice and signalling channels Control of the RF synthesizer and adaptive frequency hopping algorithm Control of the RF power and adaptive power algorithm Control of the demodulator (bit synchronizer loop filter, AFC bias estimate filtering) Control of the modulator (carrier frequency) and adaptive frequency alignment
s
Start of the 4 ms frame: a synthesizer load enable pulse is issued on the SYLE pin
s
s
Power-up of the modulator section and transmission of the frame on handset and base station Use of the bit inversion as function of mode Power-up of the demodulator section and reception of the frame on handset and base station Control of RFTX and RFRX output pins, to be used as TDD control signals switching the antenna as well as transmitter and receiver chains on the RF module Control of RFEON pin, to be used as general on/off switch on the RF module Control of the Z87000 sleep mode
s s s
s s
s
s
s s
s
s
s
4-Bit DAC for Setting Transmit Power Level
In order to save battery life, the Z87000 only transmits the amount of RF power needed to reach the remote receiver with a sufficient SNR margin. The on-board transmit power 4-bit DAC provides 4 different voltage levels to the power amplifier in the RF module for that purpose. This DAC is directly controlled by the Z87000 software through an output register.
s
Signalling between base and handset to support above features The DSP core is characterized by an efficient hardware architecture that allows fast arithmetic operations such as multiplication, addition, subtraction and multiply-accumulate of two 16-bit operands. Most instructions are executed in one clock cycle.
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FUNCTIONAL DESCRIPTION (Continued)
The DSP core is operated at the internal speed of 8.192 MHz. It has an internal RAM memory of 512 16-bit words divided in two banks. Six register pointers provide circular buffering capabilities and dual operand fetching. Three vectored interrupts are complemented by a six-level stack. One interrupt is used by the transceiver, while the two remaining vectors are mapped into port P1. In the phone system, one of these interrupts is customarily reserved for the Z87010 ADPCM Processor. The other interrupt can be used for custom purposes. The Z87000 has a (12K+128) x 16-bit internal ROM including 4 words for interrupt and reset vectors. The ROM is mapped at addresses 0000h to 2FFFh, 3F80h to 3FFFh, as shown in Figure 13.
Z87010 Interface
In addition to providing clock signals to the Z87010 processor, the Z87000 interfaces to the Z87010 through two different paths:
s s
A command/status interface
A data interface The command/status interface consists of two dual-port registers accessible by both Z87000 and Z87010 DSP core processors. On the Z87000 side, the registers are mapped into the DSP core processor's register interface. To allow access by the Z87010, the internal command/status registers can also be decoded on the pinto of the Z87000. Arbitration logic resolves access contentions. The data interface allows the Z87010 processor direct access to the Z87000's receive and transmit rate buffers. The rate buffers are decoded on the pin to of the Z87000, and dedicated voice processor interface logic handles the addressing within the rate buffers. The physical interface between Z87000 and Z87010 consists of an 8-bit data bus, a 3-bit address bus and control signals, as summarized in the following:
3FFFh 3F80h
128w ROM
Int. Vector 0 Int. Vector 1 Int. Vector 2 Reset Vector
3FFFh 3FFEh 3FFDh 3FFCh
3000h 2FFFh
12K USER ROM
VXDATA[7.0] VXADD[2.0] VXSTRB VXRWB VXRDYB
Data bus Address bus Data Strobe Read/Write Control Read Control
0000h
Figure 4. ROM Mapping
This bus is controlled by the Z87010. Although in the system the Z87010 is enslaved to the Z87000 master, at the physical level the Z87000 acts as a peripheral of the Z87010. The mapping of the command status and data interfaces from the Z87010 side is given below.
Two 16-Bit General-Purpose I/O Ports
Two 16-bit general-purpose I/O ports are directly accessible by the DSP core. These input and output pins are typically used for:
s
Address Interface (VXADD [2.0]) Transmit rate buffer Receive rate buffer Command Status 1 1 0 0
Read /Write W R R W
Data (VXDATA[7.0]) ----3210 ----3210 76543210 76543210
Implementation of the phone's user interface (keypad, LED, optional display, etc.) Control of phone line interface (on/off hook, ring detect) Control of battery charging and detection of low battery conditions Implementation of additional features for customizing of the phone
s s
s
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Z87000/Z87L00 Spread Spectrum Controllers
OPERATION Automatic Frequency Control Loop (Receiver) and Modulator AFC Loop
The AFC loop consists of a bias estimator block, which determines frequency offsets in the incoming signal, an adder, to add this bias to the 460 kHz frequency control word driving the NCO, and various interface points to the DSP core processor. In particular, the DSP can read the bias estimate data and substitute its own calculated bias value to the NCO. The bias estimator accumulates the discriminator output values (image of instantaneous frequency) that exceed a programmable threshold (BIAS_THRESHOLD). The processor can freeze the bias calculation any time by resetting the BIAS_ENABLE control bit. The accumulated bias, available in BIAS_ERROR_DATA, can be used directly to correct the NCO frequency. Alternately, the estimated bias can be read by the DSP, further processed, and written to the CORE_BIAS_DATA field. The DSP controls which value is used by setting the USE_CORE_BIAS field. The selected value is added to the 460 kHz signal which downconverts the receive IF signal. The CORE_BIAS_DATA and BIAS_ERROR_DATA are two's complement numbers in units of 125 Hz. In addition to correcting the difference in clock frequencies on the receiver using the AFC loop, a Z87000-base system can also modify the frequency of the remote transmit IF signals. The software has access to this frequency through the MOD_FREQ register fields.
1
Rx signal
Second downconvertor, Discriminator 460 kHz + bias
Discriminator Output Bias estimator
"0"
BIAS_THRESHOLD
BIAS_ENABLE
BIAS_ERROR_DATA Downconverter NCO and bias adder CORE_BIAS_DATA
DSP Core Processor
USE_CORE_BIAS
Figure 5. AFC Loop and Processor Control
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OPERATION (Continued) Modulator Control
The MOD_FREQ fields specify the carrier center frequency (should be programmed to 2.508 MHz) and deviation for the FSK signal (should be programmed to 32.58 kHz). In addition, wave shaping is performed on bit transitions, in order to satisfy FCC regulations. Up to four different intermediate deviation values are programmable for each of the two FSK states. The MOD_FREQ fields are programmable in units of 62.5 Hz. Table 1. AFC and Modulator Control Fields Field
BIAS_THRESHOLD BIAS_ENABLE BIAS_ERROR_DATA CORE_BIAS_DATA
Bit Synchronizer
The bit synchronizer circuit is an implementation of the Data-Transition-Tracking Loop (DTTL), best described in "Telecommunications Systems Engineering", by W. Lindsey and M. Simon (Dover 1973; oh. 9 p. 442). Its operation is summarized in the following block diagram.
Register CONFIG1 SSPSTATE BIAS_ERROR CORE_BIAS
Bank
3 3 2 2
EXT
EXT0 EXT2 EXT2 EXT4
Discriminator Output
In-phase Matched Filter
Transition Detection Signed Error
Mid-phase Matched Filter
Error Magnitude Loop Filter Clock Generator
division "by 1" "by 64"
INT_SYM_ERR0 INT_SYM_ERR1
first order
Recovered Bit clock
SECOND_ORDER BSYNC_GAIN
DSP Core Processor
Figure 6. Bit Synchronizer Loop and Processor Control
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Zilog The loop filter is controlled by the DSP core processor. The DSP core can implement a first order loop by setting the SECOND_ORDER field to zero. Typically, the BSYNC_GAIN would then be set to "divide-by-1" operation to provide a wide closed loop bandwidth and thus a quick acquisition of the bit clock. When the bit clock is in phase with the input data, the loop bandwidth can be narrowed to maintain tracking of the receive clock with minimum impact from signal noise. To reduce the loop bandwidth, the BSYNC_GAIN can be set to "divide-by-64" the first order gain, while the integrated tracking error (available to the DSP in fields INT_SYM_ERR0 and INT_SYM_ERR1) can be used by the DSP software to adjust the SECOND_ORDER term. The bit synchronizer relies on transitions in the received bit stream to operate. The bit inversion logic guarantees enough transitions for all transferred data. At the handset, the bit synchronizer must track both frequency and phase of the receive signal's data clock. At the base, only the phase must be tracked. The frequency is inherently correct since the base is the source of the system's data clock. Table 2. Bit Synchronizer Control Fields Field BYSNC_GAIN INT_SYM_ERR1 INT_SYM_ERR0 SECOND_ORDER Register SSPSTATE BIT_SYNC INT_SYM-ERR0 BIT_SYNC Bank 3 1 0 1 EXT EXT2 EXT2 EXT6 EXT2
Z87000/Z87L00 Spread Spectrum Controllers Each frame lasts 4 ms, which corresponds to (372 + 8/22) bits; the frame counters count from 0 to 371, with the last count lasting a bad longer than the other ones; at the end of count 371, the counters wrap around to 0. The "hop" command pulse is asserted to pin SYLE during count "0" of the frame counter (transmit frame counter on the base station).
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Frame Synchronizer, Timings and RF Interface
The frame synchronizer tracks the received frames and resets the receive frame counter. The synchronization is performed by recognizing certain data patterns present in the receive bit stream: a comparison is done on the fly between the data pattern and the incoming bit stream; when the data match, the frame counter is reset. Two possible 16-bit data patterns are pre-programmed in the Z87000. One is named UW (Unique Word) and is used in acquisition mode for first-time synchronization to an incoming signal. UW can also be used to track an acquired signal. The second pattern is named SYNC_D and is used to track the received data frames while voice is being transferred. The transition from tracking UW to tracking SYNC_D is controlled by the DSP processor through the SYNC_SEARCH_WORD field.
UW Synchronization
When the Z87000 matches the UW, the receive frame counter is reset to the value of UW_LOCATION. This value is programmable by the DSP processor. On the handset, where the receive frame counter is used to derive all timings, UW_LOCATION actually defines the guard time between the frequency hop command and the beginning of data reception, which starts at FRAME_COUNTER = (UW_LOCATION - 84) as shown in the next figure. On the base station, data reception starts when the receive frame counter equals (UW_LOCATION - 84), but this has less significance since the hop pulse is synchronized with the transmit frame counter and there is no fixed relationship between transmit and receive frame counters. On the base station, the UW_LOCATION should be set to 301.
Frame Counters
The handset only has one frame counter, which times all receive and transmit events. The base station has distinct transmit and receive frame counters. When used in this document without any explicit reference to either base or handset, the terms "receive frame counter" and "transmit frame counter" refer to both sides. For the handset, both terms refer to the same unique counter. The frame counters are clocked at the bit rate, or 93.09 kHz (2.048 MHz/22). Each count lasts one bit = 1000/93.09 = 10.74 s.
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OPERATION (Continued)
UW_LOCATION-84 Handset FRAME_COUNTER 0 SYLE timing 1 2
Receive data at RX pin
Figure 7. Frame Counter and UW_LOCATION on Handset
Two modes of search are programmable through the SYNC_SEARCH_MODE field: "full search" and "window search". The full search is used by the handset when first acquiring the signal from the base station. In full search, the handset is in receive mode and continuously looks for a match with the UW. When a match is found and the time reference established (UW_LOCATION is set), the DSP processor on the handset detects the synchronization (see below), switches to Time Division Duplex mode (TDD) and starts receiving and transmitting alternately. The search mode should also be switched to "window search" by the DSP software. The window search mode only searches for a match in a certain time window centered around the expected match time. The window size is programmable by the DSP processor in the WINDOW_SIZE field. If the matching does not occur at the expected time, due to so-called "bit slips", the receive frame counter timing is adjusted. Note: although the bit synchronizer is meant to keep track of time and prevent bit slips when the phone is operating continuously in TDD mode, bit slips are still possible when the handset is in standby mode, and only receives once in a while (see description of sleep mode).
The transition to voice mode proceeds in two steps, through an intermediate mode. The mode is set by the DSP processor by programming the MULTIPLEX_SWITCH field. The three modes are:
s
SMUX: initial mode. This mode allows acquisition, AFC operation, UW synchronization and signalling; ADPCM Processor access disabled; bit inversion disabled. STMUX: intermediate mode. This mode allows SYNC_D frame synchronization and signalling; ADPCM Processor access disabled; bit inversion enabled.
s
s
TMUX: voice mode. This mode allows voice transmission, SYNC_D frame synchronization and signalling; ADPCM Processor access enabled; bit inversion enabled. In order to detect synchronizations, the software has access to the SYNC_ACQ_IND status field. This field is set by the Z87000 matching hardware every time a match is detected within the right time window. The software must reset the "IND" bit by setting the SYNC_ACQ_CLEAR field. In addition, the software can track the frame timing by reading the frame counter value, available in the FRAME_COUNTER field. On the base station, where two frame counters are in use, this field returns the value of the transmit frame counter. Every time the frame counter wraps around to 0, a frame start indicator bit is set (FRAME_START_IND status field). The software must reset this "IND" bit by setting the FRAME_START_CLEAR field. If the FS_INT_ENABLE bit is set, frame starts also trigger interrupts to the DSP processor.
SYNC_D Synchronization
When the DSP processor switches the Z87000 operation to voice mode, the frame synchronization parameters should be modified by the DSP software to:
s s
SYNC_SEARCH_MODE = window search
SYNC_SEARCH_WORD = SYNC_D pattern In this mode, the receiver searches for the SYNC_D pattern in windows of the incoming data stream. The window size is determined by the WINDOW_SIZE field.
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SYNC_SEARCH-MODE SYNC_SEARCH_WORD UW_LOCATION WINDOW_SIZE MULTIPLEX_SWITCH SYNC_ACQ_IND SYNC_ACQ_CLEAR FRAME_COUNTER FS_INT_ENABLE FRAME_START_IND FRAME_START_CLEAR SYNC_SEARCH-MODE
Z87000/Z87L00 Spread Spectrum Controllers In addition to the SYLE signal, the interface to the most RF synthesizers includes two more input lines, "data" and "clock", for serial programming of the data values defining the RF channel. In order to allow interfacing to various popular synthesizers, the Z87000 does not have dedicated clock and data lines with fixed timing. Instead, two general I/O pins from ports P0 and P1 can be controlled in software by the DSP core to realize any particular interface timing. This flexibility is made possible by the high speed, singlecycle architecture of the DSP core. The transmitter control includes a global enable signal for all transmit functions: TX_ENABLE. The transmission start is controlled by the MOD_PWR_ON field. On the base station, the value programmed in MOD_PWR_ON is referenced to the transmit frame counter. Two additional fields, RFTX_PWR_ON and RFTX_PWR_OFF, define the duty cycle of the RFTX output pin. On the base station, these fields are referenced to the transmit frame counter. The RFTX_POLARITY bit defines the polarity of the RFTX pin. This pin can be used to control the transmit section and power amplifier of the external RF module. On the receive side, two fields define the internal timing of the receiver. The start of reception is controlled by the DEMOD_PWR_ON field. Stop of reception (and receiver power down) is controlled by the DEMOD_PWR_OFF field. On the base station, these fields are referenced to the receive frame counter. The RXON output pin follows the timing defined by the DEMOD_PWR_ON and OFF fields. Two additional fields, RFRX_PWR_ON and RFRX_PWR_OFF, define the duty cycle of the RFRX output pin. On the base station, these fields are referenced to the TRANSMIT (!) frame counter. The RFRX_POLARITY bit defines the polarity of the RFRX and RXON pins. The RFRX pin can be used to control the receive section of the external RF module.
1
Register
SSPSTATE SSPSTATE RX_CONTROL CONFIG1 SSPSTATE SSPSTATUS SSPSTATE SSPSTATUS CONTROL SSPSTATUS SSPSTATE SSPSTATE
Bank 3 3 2 3 3 3 3 3 1 3 3 3
Ext EXT2 EXT2 EXT1 EXT0 EXT2 EXT3 EXT2 EXT3 EXT6 EXT3 EXT2 EXT2
RF Interface
Several control fields are available in the Z87000 register set to control the timing and polarity of the RF module interface signals. A first field, RFEON_POLARITY, controls the polarity of the RFEON pin. This pin should be used to control the power of the RF module. It is asserted by the Z87000 when the RF module is in use, and de-asserted in sleep mode. The sleep mode is used by the handset to save battery life when no phone call is in process (See "Sleep mode" on page 21). The SYLE pin (Synthesizer Load Enable), which carries a "load enable" pulse that tells an external RF synthesizer to generate the next RF channel, is controlled by two fields. The HOP_ENABLE field is a global enable signal for the SYLE signals. The SYLE_POLARITY field defines the polarity of the SYLE pin. The system designer should ensure that the leading edge of the SYLE pulse triggers channel hopping.
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OPERATION (Continued)
The various timing control registers reviewed in this paragraph should be programmed differently for handset and base station. If the same ROM code is used on base and handset, the software can determine which station it runs on by reading the HAND_BASE_SEL bit, which reflects the state of the HBSW pin. The following figure and table summarize the RF interface control fields.
HBSW
HAND_BASE_SEL
Sleep Mode Control
RFEON_POLARITY DSP Core Processor HOP_ENABLE SYLE_POLARITY MOD_PWR_ON RFTX_PWR_ON RFTX_PWR_OFF RFTX_POLARITY TX_ENABLE
RFEON
SYLE
RFTX
Modulator
RFRX_PWR_ON RFRX_PWR_OFF RFRX_POLARITY DEMOD_PWR_ON DEMOD_PWR_OFF
TX RFRX
RXON
Demodulator
RX,VREF
Figure 8. RF interface Control
Table 4. Timing and RF Interface Control Fields Field RFEON_POLARITY HOP_ENABLE SYLE_POLARITY TX_ENABLE MOD_PWR_ON RFRX_PWR_ON/OFF DEMOD_PWR_ON/OFF RFRX_POLARITY RFTX_PWR_ON/OFF RFTX_POLARITY HAND_BASE_SEL Register RX_PWR_CTRL SSPSTATE CONFIG1 SSPSTATE MOD_PWR_CTRL RFRX_PWR_CTRL DEMOD_PWR_CTRL RFRX_PWR_CTRL RFTX_PWR_CTRL RFTX_PWR_CTRL SSP_STATUS Bank 2 3 3 3 2 0 2 0 2 2 3 Ext EXT6 EXT2 EXT0 EXT2 EXT5 EXT7 EXT6 EXT7 EXT7 EXT7 EXT3
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Sleep Mode
To save the phone's battery life on the handset, the Z87000 can be operated in sleep mode while the phone is not in use. The sleep mode is entered by software command. The sleep mode first needs to be enabled by setting the SLEEP_WAKE field. Then a GO_TO_SLEEP command puts the processor to sleep by temporarily stopping its clock. The sleep period can be set to last between 4 ms and 1.02 s by programming the SLEEP_PERIOD field. In sleep mode, the RFEON pin is de-asserted. The processor comes out of sleep mode in one of two ways. Either the sleep counter counts down to zero, or one of the enabled pins from port P0 is asserted prior to normal expiration of the counter. Four port pins (P0[0..4]) can be individually enabled to provide the wake-up function by setting the appropriate bits in P0_WAKE_ENABLE. Typically, these port pins are connected to the telephone keypad. When the processor core wakes up, the software needs to know how much time it was actually asleep, in order to restore synchronization to the base station's hopping sequence. For that purpose, the current value of the sleep counter is available to the processor in SLEEP_REMAINING. A value of zero indicates normal expiration of the sleep counter. In order to guarantee a good operation of the wake-up pins, the wake-up signals are hardware-denounced by the Z87000. Furthermore, these signals are internally synchronized to the bit clock. This ensures that the processor has enough time (one bit time = 10.74 ms) to read a stable value of the remaining sleep time and synchronize correctly to the base station's hopping sequence. Table 5. Sleep Mode Control Fields Field
SLEEP_EAKE GO_TO_SLEEP SLEEP_PERIOD SLEEP_REMAINING P0_WAKEUP_ENABLE
Clock Interface
The Z87000 generates the Z87010 clock at 16.384 or 8.192 MHz, as set in VP_CLOCK. In addition, the clock can be stopped and restarted with the VP_STOP_CLOCK field in order to reduce power consumption (Note: a software handshaking between Z87000 and Z87010 is necessary before stopping and after restarting the clock). In addition to providing the Z87010 main clock, the Z87000 generates a CODCLK signal which will be used by the codec and by the Z87010 to synchronize its data transfers with the Z87000. On the base station, the CODCLK is simply obtained by dividing the 16.384 MHz input clock. On the handset, the CODCLK is synchronized to the base station's CODCLK signal through the receive bit sync logic. This ensures that production and consumption of voice data is happening at identical rates on handset and base, eliminating buffer overrun and underrun situations.
1
Command/Status Interface
The Z87000 sends commands to the Z87010 through the VP_COMMAND write-only field. It reads the Z87010 status in the VP_STATUS read-only field. Both fields are located at the same address in the Z87000 register interface. A communication protocol should be established in software to ensure correct reception of all commands. Dedicated hardware ensures data integrity when both Z87000 and Z87010 simultaneously access the same register. Table 6. ADPCM Processor Control Fields Field VP_CLOCK VP_STOP_CLCOCKS VP_COMMAND VP_STATUS Register CONFIG1 SSPSTATE VP_INOUT VP_INOUT Bank 3 3 2 2 Ext EXT0 EXT2 EXT0 EXT0
Register
SSPSTATE SSPSTATE CONFIG2 CONFIG2 CONTROL
Bank 3 3 3 3 1
Ext EXT2 EXT2 EXT1 EXT1 EXT6
Data Interface and Rate Buffers
The digitized voice data is communicated between the Z87000 and Z87010 through the rate buffers and ADPCM Processor data interface. The transmit and receive rate buffers each contain 36 4-bit nibbles. To write to the transmit rate buffer, the Z87000 core processor must first set the nibble address in the TX_BUF_ADDR register field, then write the nibble data through TX_BUF_DATA. If the TX_AUTO_INCREMENT bit is set, the address is automatically incriminated (modulo 51 = the number of nibbles in rate buffer + 15 additional data words accessible through TX_BUF_DATA; for more information, see Register Description) after each data write. This allows the DSP core to write successive nibbles without resetting the address each time.
ADPCM Processor Interface and Rate Buffers
The interface to the ADPCM Processor (Z87010) consists of clock control, command/status interface and data interface. The data interface gives the ADPCM Processor access to the rate buffers.
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OPERATION (Continued)
The operation of the receive rate buffer is identical. The Z87000 core processor must set the nibble address in RX_BUF_ADDR, then read the nibble from RX_BUF_DATA. If the RX_AUTO_INCREMENT bit is set, the read address is automatically incriminated (modulo 36 = number of nibbles in rate buffer) after each data read. This allows the DSP core to read successive nibbles without resetting the address each time. Through its register interface, the Z87000 also controls which rate buffer addresses the Z87010 ADPCM Processor can access. The nibble addresses are contained in the TX_BUF_VP_ADDR and RX_BUF_VP_ADDR register fields. After the Z87010 writes or reads a nibble to or from transmit or receive rate buffer, the corresponding "VP_ADDR" is automatically incriminated (modulo 36) to the next accessible address. The locations of accessible addresses are individually controlled by the Z87000 in the three TX_RX_NIBBLE_MARKER register fields. A marker bit equal to "1" enables the Z87010 to access the corresponding address; a bit equal to "0" causes the Z87010's read or write access to skip to the next nibble that has a marker bit equal to "1".
Z87000
RX RATE BUFFER
Demodulator
RX_BUF_VP_ADDR
Address Decoder
TX_RX_NIBBLE_ MARKER TX_BUF_VP_ADDR
TX RATE BUFFER
Modulator Data
RX_BUF_ADDR RX_AUTO_INCR. RX_BUF_DATA TX_BUF_DATA TX_BUF_ADDR TX_AUTO_INCR.
ADPCM Proc. Interface Addr Ctrl
DSP Core Processor
VP_COMMAND VP_STATUS
Figure 9. Rate Buffers Access and ADPCM Processor Interface
1-32
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DS96WRL0501
Zilog Table 7. Data and Control Access to Rate Buffers Field
RX_AUTO_INCREMENT RX_BUF_ADDR TX_AUTO_INCREMENT TX_BUF_ADDR RX_BUF_DATA TX_BUF_DATA TX_BUF_DATA RX_BUF_VP_ADDR TX_BUF_VP_ADDR TX_RX_NIBBLE_MARKER
Z87000/Z87L00 Spread Spectrum Controllers
General-Purpose I/O Ports
The Z87000 includes two general-purpose input/output ports, P0 and P1, of 16 bit each. The direction of each bit is independently programmable by setting the register fields DIRECTION0 and DIRECTION1. Then, the software can access the input and output values by accessing DATA0 and DATA1. Two pins of port P1 (pins 14 and 15), when configured in input mode, also behave as interrupt pins for the core processor. The software can enable or disable each interrupt by setting the INTERRUPT_0_ENABLE and INTERRUPT_2_ENABLE fields. The interrupts are positive edge-triggered. Pin Number P1 14 P1 15 Interrupt Number INT0 INT2 DSP Interrupt Vector 3FFFh 3FFDh
Register
RATE_BUF_ADDR RATE_BUF_ADDR RATE_BUF_ADDR RATE_BUF_ADDR RATE_BUF_DATA RATE_BUF_ADDR RATE_BUF_DATA RATE_BUF_DATA RATE_BUF_DATA RATE_BUF_DATA
Bank Next
1 1 1 1 1 1 1 1 1 1 EXT0 EXT0 EXT0 EXT0 EXT0 EXT1 EXT1 EXT1 EXT1 EXT1
1
Additional Features Power Control
The Z87000 features several means of measuring and controlling power levels. One input pin (RSSI) connects an external "receive signal strength indicator" to a half flash 8bit ADC in the Z87000. This ADC is sampled once per frame during the receive portion of the TDD cycle. The RSSI value can be accessed in software in the RSSI_DATA register field. With external multiplexing, the 8-bit ADC can be used for additional purposes. The RSSI data is used by the software to implement adaptive power control. In order to determine whether the RSSI information is made of signal or noise, the Z87000 includes logic to measure the signal-to-noise ratio (SNR) of the receive signal. This SNR value is available at the end of every frame in the SNR_ESTIMATE register field. It is also used by the adaptive frequency hopping algorithm to determine and avoid the noisy channels. Finally, a 4-bit DAC (resistive ladder) is provided to control RF power output level. The DAC is under software control through register field TX_PWR_DAC_DATA. Table 8. Power Control Field
RSSI_DATA SNR_ESTIMATE TX_PWR_DAC_DATA RSSI_DATA SNR_ESTIMATE
Table 9. General-Purpose I/O Ports Field
DIRECTION0 DATA0 DIRECTION1 DATA1 INTERRUPT_0_ENABLE INTERRUPT_1_ENABLE
Register
GPI00DIR GPI00DATA GPI0IDIR GPI0IDATA CONTROL CONTROL
Bank
3 3 3 3 1 1
Ext EXT4 EXT5 EXT6 EXT7 EXT6 EXT6
Four pins of port P0 (pins 0 to 3), when configured in input mode, can also be individually programmed as wake-up pins for the Z87000 (See "Sleep mode" on page 21).
Register
RSSI RX_CONTROL CONTROL RSSI RX_CONTROL
Bank
2 2 1 2 2
Ext
EXT3 EXT1 EXT6 EXT3 EXT3
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Z87000/Z87L00 Spread Spectrum Controllers
Zilog
REGISTER DESCRIPTION
The Z87000 DSP core processor has four banks of eight registers mapped in the core processor's "external register" space, as summarized in the following table. Table 10. Register Summary BANK ADDRESS Bank 3 EXT0 REGISTER CONFIG1 READ DESCRIPTION WRITE DESCRIPTION TABLE # Table 25
EXT1 EXT2
CONFIG2 SSPSTATE
EXT3
SSPSTATUS
Bank 2
Bank 1
EXT4 EXT5 EXT6 EXT7 EXT0 EXT1 EXT2 EXT3 EXT4 EXT5 EXT6 EXT7 EXT0 EXT1 EXT2 EXT3 EXT4 EXT5 EXT6 EXT7 EXT0 EXT1 EXT2 EXT3 EXT4 EXT5 EXT6 EXT7
GPIO0DIR GPIO0DATA GPIO1DIR GPIO1DATA VP_INOUT RX_CONTROL BIAS_ERROR RSSI CORE_BIAS MOD_PWR_CTRL DEMOD_PWR_CTRL RFTX_PWR_CTRL RATE_BUF_ADDR RATE_BUF_DATA BIT_SYNC RESERVED RESERVED RESERVED CONTROL RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED INT_SYM_ERR0 RFRX_PWR_CTRL
Clock Dividers, Use Core Bias, SYLE polarity, search window size, Bias Threshold Remaining Sleep time ANT0/1 control, Sleep Period Stop VP clock, Absent gain, Bias Enable, Tx Enable, Sync Search control, Hop Enable, Frame Start control, Multiplex control, Sleep mode control Frame Counter, Handset/Base, Sync Search control, Frame Start control General-Purpose I/O port 0 direction control General-Purpose I/O port 0 data General-Purpose I/O port 1 direction control General-Purpose I/O port 1 data ADPCM Processor Status ADPCM Processor Command SNR estimate UW location FCW value 8-bit ADC data (RSSI) Core Bias data MOD_PWR control RXON, RFEON pin control RFTX pin control Rate Buffer address Re Rate Buffer data Tx Rate Buffer data, control data Bit Sync monitoring Bit Sync control
Table 26 Table 27
Table 28
Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 44 Table 44 Table 45 Table 46 Table 47 Table 47 Table 47 Table 47 Table 47 Table 47 Table 47 Table 49
INT, WAKEUP pin control, 4-bit DAC data (PWLV)
Bank 0
Bit Sync monitoring RFRX, RXON pin control
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DS96WRL0501
Zilog The bank is selectable in software by writing to the core's status register (see Table 24). Once a bank is selected,
Z87000/Z87L00 Spread Spectrum Controllers each of the eight external registers (EXT0 through EXT7) can be accessed by a single-cycle software instruction.
Table 11. Bank Switching Bank Bank 0 Bank 1 Bank 2 Bank 3 Status Register xxxx xxxx x00x xxxx b xxxx xxxx x01x xxxx b xxxx xxxx x10x xxxx b xxxx xxxx x11x xxxx b Bank Function Test point access, TDD switching control Rate buffer access, miscellaneous ADPCM processor interface, RF interface, etc. Configuration, status, general-purpose port data and direction
1
Bank 3 Registers
Table 12. Bank 3 Registers Config 1 Field RESERVED VP_CLOCK Bank 3 Bit Position f---------------e-------------EXT0 R/W R W Data Description Returns 0 Must be set to 1 Controls CLKOUT output pin (clock for ADPCM Processor). Returns 0 0 CLOCKOUT=16.384 MHz 1 CLOCKOUT = 8.192 Controls which bias value is used by the downconverter's NCO as part of the automatic frequency control loop (AFC) Returns 0 0* Uses BIAS_ERROR_DATA value from AFC hardware 1 Uses CORE_BIAS_DATA value from DSP core Controls the polarity of the SYLE output pin (hop pulse) Returns 0 0 SYLE is a positive pulse 1 SYLE is a negative pulse Defines the search window size (in bits) for windowed search mode (for Unique Word or SYNC_D words). Returns 0 0000 Window size=1 0001 Window size =3 (11) *** 1111 Window size = 31 (1 15) Bias estimator threshold value Returns 0 XXh Sets the bias value
USE_CORE_BIAS --d------------R W SYLE_POLARITY ---c-----------R W WINDOW_SIZE ----ba98-------R W
BIAS_THRESHOL -------76543210 D
R W
Notes: 1. VP_CLOCK. Internally synchronized to avoid glitches. Changes to this bit take effect immediately. 2. SYLE_POLARITY. Changes to this bit take effect immediately. 3. BIAS_THRESHOLD. The bias threshold must be coded as a negative value (opposite of the threshold value) coded in 2's complement. The nominal value for the threshold is -46 (=D3h). Internally, this value is sign-extended to 13 bits.
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Z87000/Z87L00 Spread Spectrum Controllers
Zilog
REGISTER DESCRIPTION (Continued)
Table 13. Bank 3 Register EXT1 Config 2 Field Bank 3 Bit Position EXT1 R/W Data Description
ANTENNA_SW_DEFEAT f--------------R W ANTENNA_SW_OFFSET -edcba98-------R W SLEEP_PERIOD --------76543210 W
Controls optional antenna switching (ANT0 and ANT1 pins) Returns 0 0 Enables antenna switching 1 Disables antenna switching Controls antenna switching time advancement Returns 0 Offset in number of 2.048 MHz clock cycles xXh (<108) 00h Programs sleep duration in sleep mode Illegal 01h Sleep period=1 frame (4 ms) *** FFh Sleep period = 255 frames (1.020s) Returns value of sleep counter when sleep mode is interrupted by a "wake" signal 00h Normal expiration of sleep counter 01h One frame left before normal expiration *** FFh 255 frames left before normal expiration
SLEEP_REMAINING
--------76543210 R
Notes: 1. SLEEP_PERIOD. In sleep mode, the RFEON pin is active. Changes to this bit take effect immediately. 2. SLEEP_REMAINING. A non-zero value indicates that the Z87000 was awakened by a key press activating one of the wake-up pins on port 0. In this case, the processor should immediately reset the SLEEP_WAKE field in SSPSTATE to prevent the process from going back to sleep when the user key press ceases.
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DS96WRL0501
Zilog Table 14. Bank 3 Register Description SSPSTATE Field SW_SYLE Bank 3 Bit Position f--------------R/W 0* 1 STOP_CODCLK -e-------------R/W 0* 1 DBP_STOP_CLOCK --d------------R/W 0* 1 BSYNC_GAIN ---c-----------R/W 0* 1 BIAS_ENABLE ----b----------R/W 0* 1 TX_ENABLE -----a---------R/W 0* 1 SYNC_SEARCH_WORD ------9--------R/W 0* 1 SYNC_SEARCH_MODE -------87------R/W 00* 01 10 11 HOP_ENABLE ---------6-----R/W 0 1 SYNC_ACQ_CLEAR ----------5----R W FRAME_START_CLEAR -----------4---R W SLEEP_WAKE ------------3--R/W 0 1 MULTIPLEX_SWITCH -------------21R/W 00* 01 10 11 1->0 1->0 EXT2 R/W Data Description
Z87000/Z87L00 Spread Spectrum Controllers
GO_TO_SLEEP
--------------0 R W 0->1
Controls accelerated synthesizer programming after sleep Not Active Active Inhibits toggling of codec clock output during sleep CODCLK is free running CODCLK is frozen high Controls toggling of CLKOUT output pin (clock for ADPCM Processor). CLKOUT is free running CLKOUT is frozen high Selects gain for first order loop of the bit synchronizer Nominal gain Gain divided by 64 Controls closed-loop AFC circuit No new bias estimation is performed (latest estimate used) Enables BIAS_ERROR_DATA updates Global enable for all transmit functions Transmitter disabled Transmitter enabled Controls the word searched for in search mode Search for UW pattern (Unique Word) Search for SYNC_D pattern Controls the search mode (and frame synchronization) No search Window search (<= UW_LOCATION & WINDOW_SIZE) Full search (during whole frame) Not used Enables transmission of the hop pulse on SYLE pin Hop pulse disabled Hop pulse enabled Clears the SYNC_ACQ_IND flag. Returns last value written A transition from 1 to 0 clears the flag Clears the FRAME_START_IND flag Returns last value written A transition from 1 to 0 clears the flag Enable bit for entering sleep mode Wake mode only Sleep mode can be activated by GO_TO_SLEEP command Controls operation of the transceiver SMUX (bit inversion and ADPCM Processor access disabled) STMUX (bit inv. enabled; ADPCM Proc. access disabled) Reserved TMUX (bit inversion and ADPCM Processor access enabled) Command bit to place the Z87000 in sleep mode Returns last value written A transition from 0 to 1 causes Z87000 sleep mode
1
DS96WRL0501
PRELIMINARY
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Z87000/Z87L00 Spread Spectrum Controllers
Zilog
REGISTER DESCRIPTION (Continued)
Table 14. Bank 3 Register Description SSPSTATE Field
TX_ENABLE
Bank 3 Bit Position
-----a----------
EXT2 R/W Data
R/W 0* 1 0* 1 00* 01 10 11 0 1
Description
Global enable for all transmit functions Transmitter disabled Transmitter enabled Controls the word searched for in search mode Search for UW pattern (Unique Word) Search for SYNC_D pattern Controls the search mode (and frame synchronization) No search Window search (<= UW_LOCATION & WINDOW_SIZE) Full search (during whole frame) Not used Enables transmission of the hop pulse on SYLE pin Hop pulse disabled Hop pulse enabled Clears the SYNC_ACQ_IND flag. Returns last value written A transition from 1 to 0 clears the flag Clears the FRAME_START_IND flag Returns last value written A transition from 1 to 0 clears the flag Enable bit for entering sleep mode Wake mode only Sleep mode can be activated by GO_TO_SLEEP command Controls operation of the transceiver SMUX (bit inversion and ADPCM Processor access disabled) STMUX (bit inv. enabled; ADPCM Proc. access disabled) Reserved TMUX (bit inversion and ADPCM Processor access enabled) Command bit to place the Z87000 in sleep mode Returns last value written A transition from 0 to 1 causes Z87000 sleep mode
SYNC_SEARCH_WORD
------9--------R/W
SYNC_SEARCH_MODE
-------87------R/W
HOP_ENABLE
---------6-----R/W
SYNC_ACQ_CLEAR
----------5----R W 1->0
FRAME_START_CLEAR
-----------4---R W 1->0 0 1 00* 01 10 11
SLEEP_WAKE
------------3--R/W
MULTIPLEX_SWITCH
-------------21R/W
GO_TO_SLEEP
---------------0 R W 0->1
Notes: 1. DBP_STOP_CLOCK. When this bit is set to 1, the ADPCM Processor clock (CLKOUT) is stopped within two clock periods. When this bit is set to 0, the ADPCM Processor clock restarts within two clock periods; in every case, the ADPCM Processor clock minimum specifications for high time and low time are respected. 2. BSYNC_GAIN. Changes to this bit take effect immediately. BIAS_ENABLE. This bit is a global enable for the Automatic Frequency Control. When the bit is set, the AFC hardware updates the current BIAS_ERROR_DATA during specific time windows, controlled by the event trigger hardware and suitable for a good operation of the AFC. When the bit is reset, the AFC operation is suspended. However, the current BIAS_ERROR_DATA, resulting from previous bias estimations, can still be used to bias the downconverter NCO. Changes to the BIAS_ENABLE bit take effect at the beginning of the frame following the change. 3. TX_ENABLE. Global control for all system transmit functions, including RFTX pin control (timing set by the RFTX_PWR_ON/OFF register fields) and power to the modulator and NCO (timing set by MOD_PWR_ON and the wake/sleep modes). 4. Changes to this bit take effect immediately. 5. HOP_ENABLE. Changes to this bit take effect immediately. 6. SLEEP_WAKE. This bit must be set to enable the core to put itself to sleep via the GO_TO_SLEEP command. The SLEEP_WAKE bit must be reset to prevent the core to fall back to sleep after it is awaken by one of the Port 0 Wake-up pins when the sleep period has not expired. If the bit is not reset, the core will fall right back to sleep when the wake-up input is de-asserted (note that by design, a wake-up input has a minimum of 10 ms duration, to allow the software enough time to safely reset the SLEEP_WAKE bit). 7. SYNC_AQC_CLEAR. This bit must be set to "1" again after every "clear" operation to allow for the next "clear". 8. FRAME_START_CLEAR. This bit must be set to "1" again after every "clear" operation to allow for the next ?"clear".
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DS96WRL0501
Zilog Table 15. Bank 3 Register Description SSPSTATUS Field FRAME_COUNTER Bank 3 Bit Position fedcba987-----R EXT3 R/W Data
Z87000/Z87L00 Spread Spectrum Controllers
Description Current frame counter value First value at beginning of frame (0)
1
RESERVED HAND_BASE_SEL
---------65--------------4---
W R W R W
SYNC_ACQ_IND
------------3-R W
FRAME_START_IND
------------2-R W
RESERVED
-------------10
R W
00h ... 173h Last value at end of frame (371) ... Illegal values No effect Returns 0 No effect Reflects status of Handset/Base select pin (HBSW) 0 Base (HBSW = 0) 1 Handset (HBSW = 1) No effect Indicates detection of a Sync word (UW or SYNC_D depending on SYNC_SEARCH_WORD search mode) 0 No sync word detected Sync word detected 1 No effect Indicates start of a new frame 0 No start of new frame (1 written to 1 FRAME_START_CLR) New frame started No effect Returns 0 No effect
Notes: FRAME_COUNTER. Read the double-buffered current value of the Frame Counter. On the handset, a single frame counter is used to clock transmit and receive events. On the base station, the transmit frame counter value is returned
Table 16. Bank 3 Register Description GPIO0DIR Field DIRECTION0 Bit 3 Bit Position fedcba9876543210 R/W ..0. ..1. EXT4 R/W Data Description Independent control of Port 0 pin direction Sets pin in input mode Sets pin in output mode
Table 17. Bank 3 Register Description GPIO0DATA Field DATA0 Bank 3 Bit Position fedcba9876543210 R W EXT5 R/W Data Description
Access to Port 0 data XXXXh Reads pin values XXXXh Writes output pin values
Notes: DATA0. The read value returns the actual pin values and does not depend on the pin directions (i.e. for output pins, the output value is returned unless a contention occurs).
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PRELIMINARY
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Z87000/Z87L00 Spread Spectrum Controllers
Zilog
REGISTER DESCRIPTION (Continued)
Table 18. Bank 3 Register Description GPIO1DIR Field DIRECTION1 Bank 3 Bit Position fedcba9876543210 R/W ..0. ..1. EXT6 R/W Data Description Independent control of Port 1 pin direction Pin in input mode Pin in output mode
Table 19. Bank 3 Register Description GPIO1DATA Field DATA1 Bank 3 Bit Position fedcba9876543210 R W EXT7 R/W Data Description
Access to Port 1 data XXXXh Reads pin values XXXXh Writes output pin values
Notes: DATA1. The read value returns the actual pin values and does not depend on the pin directions (i.e. for output pins, the output value is returned unless a contention occurs)
Bank 2 Registers
Table 20. Bank 2 Register Description VP_INOUT Field RESERVED VP_STATUS Bank 2 Bit Position fedcba98---------------76543210 R VP_COMMAND --------76543210 W XXh XXh EXT0 R/W R W Data Description Returns 0 No effect Access to ADPCM Processor's Command/Status mailbox Reads Status byte from ADPCM Processor Access to ADPCM Processor's Command/Status mailbox Writes Command byte to ADPCM Processor
Table 21. Bank 2 Register Description RX_CONTROL Field SNR_ESTIMATE Bank 2 Bit Position fedcba9876543210 R UW_LOCATION -------876543210 W XXXXh Location of the Unique Word XXXXh Initializes the value that the receive frame counter is set to on detection of the Unique Word EXT1 R/W Data Description Access to channel measurement (SNR) estimate Returns the SNR value
Notes: SNR_ESTIMATE. This value is updated every frame. It should be read by the software during the frequency hopping guard time of the next frame.
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PRELIMINARY
DS96WRL0501
Zilog Table 22. Bank 2 Register Description BIAS_ERROR Field BIAS_ERROR_DATA Bank 2 Bit Position fedcba9876543210 R W EXT2 R/W Data
Z87000/Z87L00 Spread Spectrum Controllers
Description
Access to the bias estimate from the AFC loop. XXXXh Current bias estimate value No effect
1
Notes: BIAS_ERROR_DATA. This value is used to bias the downconverter's NCO if the USE_CORE_BIAS register field is reset. It is encoded as a 2's complement number. The unit is 125 Hz
. Table 23. Bank 2 Register Description RSSI Field RESERVED RSSI_DATA Bank 2 Bit Position fedcba98--------------76543210 R W XXh EXT3 R/W R W Data Description Returns 0 No effect Access to 8-bit ADC (can be used for RSSI data) Returns latest value on 8-bit DAC No effect
Note: RSSI_DATA. This value is sampled once per frame (4ms) approximately at bit 72 (middle) of the received data.
Table 24. Bank 2 Register Description CORE_BIAS Field RESERVED CORE_BIAS_DATA Bank 2 Bit Position fed---------------cba9876543210 R W EXT4 R/W R W Data Description
Returns 0 No effect Stores bias value for correction of downconverter's NCO. Returns 0 xXXXh Updates bias value
Notes: CORE_BIAS_DATA.This value is used if the USE_CORE_BIAS register field is set. It is encoded as a 2's complement number. The unit is 125 Hz.
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PRELIMINARY
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Z87000/Z87L00 Spread Spectrum Controllers
Zilog
REGISTER DESCRIPTION (Continued)
Table 25. Bank 2 Register Description MOD_PWR_CTRL Field RESERVED MOD_PWR_ON Bank 2 Bit Position f---------------edcba98-------R W R W EXT5 R/W R W Data Description Returns 0 No effect Determines modulator turn-on time referenced to the transmit frame counter Returns 0 Bits 6-0 of turn-on time (=(x modulo 128) -1) Returns 0 No effect
xXh
RESERVED
--------76543210
Notes: 1. MOD_PWR_ON. Controls the turn-on time for the internal modulator and NCO. Only the 7 LSBits of the 9-bit value necessary to encode an event (from frame counter 0 to 371) are programmable. The two MSBits have fixed values which depend on whether base station or handset is selected: "00" on the base and "01" on the handset. The modulator's turn-off time occurs a fixed time (number of bits) after the turn-on time: 144 bits on the base station, 148 bits on the handset. 2. Changes to this value take effect immediately. 3. To disable the modulator continuously, clear TX_ENABLE
Table 26. Bank 2 Register Description DEMOD_PWR_CTRL Field RFEON_POLARITY Bank 2 Bit Position f--------------R W DEMOD_PWR_ON -edcba98-------0 1 EXT6 R/W Data Description Controls the polarity of the RFEON output pin Returns 0 Active high Active Low Determines internal power up of demodulator and turn on time of RXON pin, referenced to the receive frame counter Returns 0 Bits 6-0 of turn-on time (=(x modulo 128) -1) Returns 0 No effect Determine internal power down of demodulator and turn off time of RXON pin, referenced to the receive frame counter Returns 0 Bits 6-0 of turn-off time (=(x modulo 128) -1)
RESERVED DEMOD_PWR_OFF
--------7---------------6543210
R W R W
xXh
R W
XXh
Notes: 1. DEMOD_PWR_ON, DEMOD_PWR_OFF. Controls internal receive hardware and the RXON output pin. The turn-on and off times are given in number of received bit periods and are referenced to the Receive Frame Counter. Only the 7 LSBits of the 9-bit value are programmable. The two MSBits have fixed values which depend on whether base station or handset is selected. For DEMOD_PWR_ON, the two bits are "01" on the base and "00" on the handset. For DEMOD_PWR_OFF, the two bits are "10" on the base and "01" on the handset 2. Changes to these values take effect immediately. 3. To enable receive power continuously, clear TX_ENABLE and set SYNC_SEARCH_MODE to FULL_SEARCH (this is the case in acquisition mode). 4. The polarity of the RXON output pin is controlled by the RFRX_POLARITY bit in the RFRX_PWR_CTRL register
.
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DS96WRL0501
Zilog Table 27. Bank 2 Register Description RFTX_PWR_CTRL Field RFTX_POLARITY Bank 2 Bit Position f--------------R W RFTX_PWR_ON -edcba98-------R W R W 0 1 EXT7 R/W Data
Z87000/Z87L00 Spread Spectrum Controllers
Description Controls the polarity of the RFTX output pin Returns 0 Active high Active Low Determines RFTX output pin turn-on time referenced to the transmit frame counter Returns 0 Bits 6-0 of turn-on time (=(x modulo 128) -1) Returns 0 No effect Determine RFTX output pin turn-off time referenced to the transmit frame counter Returns 0 Bits 6-0 of turn-off time (=(x modulo 128) -1)
1
xXh
RESERVED RFTX_PWR_OFF
--------7---------------6543210
R W
xXh
Notes: 1. RFTX_PWR_ON, RFTX_PWR_OFF. Controls the RFTX output pin, and thereby the external RF module's transmitter. The turn-on and off times are given in number of transmitted bit periods and are referenced to the transmit Frame Counter. Only the 7 LSBits of the 9-bit value are programmable. The two MSBits have fixed values which depend on whether base station or handset is selected. For RFTX_PWR_ON, the two bits are "00" on the base and "01" on the handset. For RFTX_PWR_OFF, the two bits are "01" on the base and "10" on the handset. 2. Changes to these values take effect immediately. 3. To disable the transmitter continuously, clear TX_ENABLE in SSP_STATE.
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Z87000/Z87L00 Spread Spectrum Controllers
Zilog
REGISTER DESCRIPTION (Continued) Bank 1 Registers
Table 28. Bank 1 Register Description RATE_BUF_ADDR File RESERVED Bank 1 Bit Position f-------------EXT0 R/W R W R W Data Description
RX_AUTO_INCREMENT -e-------------
RX_BUF_ADDR
--dcba98-------R W
RESERVED
--------7-------
R W R W
TX_AUTO_INCREMENT ---------6------
TX_BUF_ADDR
----------543210 R W
Returns 0 No effect Controls the auto-increment feature of the Rx rate buffer 0 Returns 0 1 Disables auto-increment Enables auto-increment Access to Rx rate buffer address Returns 0 00h Address 0 ... ... 23h Address 23h = 35 ... Illegal Returns 0 No effect Controls the auto-increment feature of the Tx rate buffer Returns 0 0 Disables auto-increment 1 Enables auto-increment Access to Tx rate buffer address Returns 0 00h Address 0 ... ... 23h Address 23h = 35 24h Tx/Rx rate buffer address for ADPCM Processor 25h accesses 26h Tx/Rx Nibble Marker bits [15..0] 27h Tx/Rx Nibble Marker bits [31..16] 28h Tx/Rx Nibble Marker bits [35..32] 29h MOD_FREQ_DEV 0 2Ah MOD_FREQ_DEV 1 2Bh MOD_FREQ_DEV 2 2Ch MOD_FREQ_DEV 3 2Dh MOD_FREQ_DEV 4 2Eh MOD_FREQ_DEV 5 2Fh MOD_FREQ_DEV 6 30h MOD_FREQ_DEV 7 31h MOD_FREQ_DEV 8 32h MOD_FREQ_DEV 9 ... MOD_CENTER_FREQ Illegal
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PRELIMINARY
DS96WRL0501
Zilog Table 29. Bank 1 Register Description RATE_BUF_DATA Field RX_BUF_DATA Bank 1 Bit Position ------------3210 R TX_BUF_DATA ------------3210 W TX_BUF_VP_ADDR --dcba98-------W RX_BUF_VP_ADDR ----------543210 W TX_RX_NIBBLE_MARKER fedcba9876543210 W MOD_FREQ fedcba9876543210 W EXT1 R/W Data
Z87000/Z87L00 Spread Spectrum Controllers
Description
Access to the Rx rate buffer data Xh Reads value at current RX_BUF_ADDR address (0 to 23h) Access to the Tx rate buffer data XXXXh Writes value at current TX_BUF_ADDR address (0 to 23h) Sets the initialization value of the Tx rate buffer address used for ADPCM Processor accesses XXh Writes initialization value (TX_BUF_ADDR address= 24h) Sets the initialization value of the Rx rate buffer address used for ADPCM Processor accesses XXh Writes initialization value (TX_BUF_ADDR address= 24h) Sets the Nibble Marker register for Tx and Rx rate buffer accesses by ADPCM Processor XXXXh Write nibble marker value (TX_BUF_ADDR= 25h to 27h) Access to modulator settings XXXXh Writes modulator setting value (TX_BUF_ADDR=28h to 32h)
1
Note: The meaning and address for any RATE_BUF_DATA is set in the RATE_BUF_ADDR register. MOD_FREQ. The unit for center frequency and frequency deviation words is 62.5 Hz. These words are encoded as 2's complement numbers. The meaning and address for any RATE_BUF_DATA is set in the RATE_BUF_ADDR register. MOD_FREQ. The unit for center frequency and frequency deviation words is 62.5 Hz. These words are encoded as 2's complement numbers.
Table 30. Bank 1 Register Description BIT_SYNC Field INT_SYM_ERR1 Bank 1 Bit Position fedcba9876543210 R SECOND_ORDER fedcba9876543210 W EXT2 R/W Data Description
Read access to the integrated symbol error from the bit synchronizer's second order loop XXXXh Reads error data bits [23..8] (bits [7..0] are in bank 0, EXT6) Write access to the bit synchronizer's second-order loop XXXXh Writes second order loop's 16-bit value
Table 31. Bank 1 Register Description RESERVED Field RESERVED Bank 1 Bit Position fedcba9876543210 EXT3 EXT4 EXT5R/W R W
Data
Description
Returns 0 0000h Must be left alone or written to 0000h (or unpredictable results may occur)
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PRELIMINARY
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Z87000/Z87L00 Spread Spectrum Controllers
Zilog
REGISTER DESCRIPTION (Continued)
Table 32. Bank 1 Register Description CONTROL Field RESERVED FS_INT_ENABLE Bank 1 Bit Position fedcb---------------a---------R/W INTERRUPT_0_ENABLE ------9--------R/W INTERRUPT_2_ENABLE -------8-------R/W P0_WAKEUP_ENABLE --------7654---R/W 0000* 1xxx x1xx xx1x xxx1 Xh 0* 1 0* 1 0* 1 EXT6 R/W R W Data Description Returns 0 No effect Controls frame start interrupt (INT1) Disables frame start interrupt Enables frame start interrupt Controls interrupt 0 (INT0 on P114) Disables interrupt 0 Enables interrupt 0 Controls interrupt 2 (INT2 on P115) Disables interrupt 2 Enables interrupt 2 Controls wake-up pins (P0[3..0]) Disables all wake-up pins Enables P03 as wake-up pin (if in input mode) Enables P02 as wake-up pin (if in input mode) Enables P01 as wake-up pin (if in input mode) Enables P00 as wake-up pin (if in input mode) Access to Tx power 4-bit DAC output data Sets output value
TX_PWR_DAC_DATA
------------3210 R/W
Note: P0_WAKEUP_ENABLE. When enabled, pins P0[3..0] are active low wake-up pins for the Z87000 sleep mode. The input signal is internally debounced and synchronized to the bit clock. It is internally given a minimum duration of one bit to allow the software to exit sleep mode safely.
Table 33. Bank 1 Register Description RESERVED Field RESERVED Bank 1 Bit Position fedcba9876543210 EXT7 R/W R W Data Returns 0 No effect Description
1-46
PRELIMINARY
DS96WRL0501
Zilog
Z87000/Z87L00 Spread Spectrum Controllers
Bank 0 Registers
Table 34. Bank 0 Register Description EXT0 EXT1 EXT2 EXT3 EXT4 EXT5 R/W R W
1
RESERVED Field RESERVED
Bank 0 Bit Position fedcba9876543210
Data Returns 0 No effect
Description
Table 35. Bank 0 Register Description INT_SYM_ERR0 Field RESERVED INT_SYM_ERR0 Bank 0 Bit Position fedcba98---------------76543210 R W XXh EXT6 R/W R W Data Description Returns 0 No effect Read access to the integrated symbol error from the bit synchronizer's second order loop Reads error data bits [7..0] (bits [23..8] are in bank1, EXT2) No effect
Table 36. Bank 0 Register Description RFRX_PWR_CTRL Field RFRX_POLARITY Bank 0 Bit Position f--------------R W RFRX_PWR_ON -edcba98-------R W R W EXT7 R/W Data Description Controls the polarity of the RFRX (and RXON) output pins Returns 0 RFRX active Low and RXON active High RFRX active High and RXON active Low Determines RFRX output pin turn-on time referenced to the transmit frame counter Returns 0 Bits 6-0 of turn-on time (=(x modulo 128) -1) Returns 0 No effect Determine RFRX output pin turn-off time referenced to the transmit frame counter Returns 0 Bits 6-0 of turn-off time (=(x modulo 128) -1)
0 1
xXh
RESERVED RFRX_PWR_OFF
--------7---------------6543210
R W
xXh
Notes: 1. RFRX_POLARITY. Caution: notice the inverse polarity of the RFRX pin. 2. RFRX_PWR_ON, RFRX_PWR_OFF. Controls the RFRX output pin. The turn-on and off times are given in number of transmitted bit periods and are referenced to the TRANSMIT (!) Frame Counter. Only the 7 LSBits of the 9-bit value are programmable. The two MSBits have fixed values which depend on whether base station or handset is selected. For RFRX_PWR_ON, the two bits are "00" on the base and "01" on the handset. For RFRX_PWR_OFF, the two bits are "01" on the base and "10" on the handset. 3. Changes to these values take effect immediately. 4. To disable transmit power continuously, clear TX_ENABLE.
DS96WRL0501
PRELIMINARY
1-47
Z87000/Z87L00 Spread Spectrum Controllers
Zilog
INSTRUCTION SET DESCRIPTION
Refer to Zilog's Z89C00 User's Manual, Chapter 5 (Instruction Set Features) and Chapter 6 (Assembly Language Instruction Set), for a complete description of the core processor's instruction set.
Table 37. Instruction Set Summary Instruction Description
ABS Absolute Value 1001000 1001000 ADD Addition 1001001 1000001 1000100 1000101 1000011 1000001 1000000 AND Bitwise AND 1011001 1010001 1010100 1010101 1010001 1010001 1010000 CALL Subroutine call 0010100 0010100 CCF CIEF COPF CP Clear carry flag 1001010 Clear Carry Flag 1001010 Clear OP flag 1001010 Comparison 0111001 0110001 0110101 0110011 0110001 0110000 0110100 DEC Decrement 1001000 1001000 INC Increment 1001000 1001000 JP Jump 0100110 0100110 JP [,]

, 2 2 2 2 JP NIE,Label JP Label INC [,] ,A A 1 1 1 1 INC PL,A INC A DEC [,] A, A 1 1 1 1 DEC NZ,A DEC A CP, A, A, A, A, A, A, A, 1 1 1 1 1 1 2 1 1 3 1 1 1 2 CP A,P0:0 CP A,D3:1 CP A,@@P0:0 CP A,%FF CP A,@P2:1+ CP A,STACK CP A,#%FFCF COPF None 1 1 COPF CIEF None 1 1 CIEF CALL [,]

CCF None 1 1 CCF AND, A, A, A, A, A, A, A, , 1 1 2 1 1 1 1 2 2 1 1 2 3 1 1 1 2 2 AND A,P2:0 AND A,D0:1 AND A,#%1234 AND A,@@P1:0 AND A, %2C AND A,@P1:2+LOOP AND A, EXT3 CALL sub1 CALL Z,sub2 ADD, A, A, A, A, A, A, A, 1 1 2 1 1 1 1 1 1 2 3 1 1 1 ADD A,P0:0 ADD A,D0:0 ADD A,#%1234 ADD A,@@P0:0 ADD A,%F2 ADD A, @P1:1 ADD A,X
Opcode
Synopsis
ABS[,] ,A A
Operands
# # Words Cycles
1 1 1 1
Example
ABS NC,A ABS A
1-48
PRELIMINARY
DS96WRL0501
Zilog Table 37. Instruction Set Summary Instruction Description
LD
Z87000/Z87L00 Spread Spectrum Controllers
Opcode
Synopsis
LD,
Operands
A, A, A, A, A, A, ,A , , , , , , , , , , , ,
# # Words Cycles
1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 2 3 3 1 1 1 1 1 1
Example
LD A,X LD A,D0:0 LD A,P0:1 LD A,@P1:1 LD A,@D0:0 LD A, 124 LD 124, A LD DO:0, EXT7 LD P1:1,#%FA LD P1:1,EXT1 LD @P1:1,#%1234 LD @P1:1+,X LD Y,P0:0 LD SR,D0:0 LD PC,#%1234 LD X,@A LD Y,@D0:0 LD A,@P0:0-LOOP LD X, EXT6 MLD A,@P0:0+LOOP MLD A,@P1:0,OFF MLD @P1:1,@P2:0 MLD@P0:1,@P1:0,O N
MLD
Load destination with source 0000000 0000001 0001001 0000001 0000101 0000011 0000111 0000100 0001100 0001010 0000110 0000010 0001001 0000001 0000100 0100101 0000101 0000001 0000000 Multiply 1010010 1010010 1011011 1011011
1
MLD, [,]
, ,, , ,, , ,, , ,,
MPYA
Multiply and add 1010010 1010010 1011011 1011011
MPYA , [,]
1 1 1 1
1 1 1 1
MPYA A@P0:0 MPYA A,@P1:0,OFF MPYA @P1:1,@P2:0 MPYA@P0:1,@P1:0, ON
MPYS
Multiply and subtract
0010010 0010010 0011011 0011011
NEG
Negate 1001000 1001000
NOP OR
No operation 0000000 Bitwise OR 1101001 1100001 1100100 1100101 1100011 1100001 1100000
MPYS, [,] , ,, , ,, NEG ,A , A A NOP None OR , A, A, A, A, A, A, A,
1 1 1 1
1 1 1 1
MPYS A,@P0:0 MPYS A,@P1:0,OFF MPYS @P1:1,@P2:0 MPYS@P0:1,@P1:0, ON
1 1 1 1 1 2 1 1 1 1
1 1 1 1 1 2 3 1 1 1
NEG NZ,A NEG A NOP OR A, P0:1 OR A, D0:1 OR A,#%202 OR A,@@P2:1+ OR A, %2C OR A, @P1:0-LOOP OR A, EXT6
DS96WRL0501
PRELIMINARY
1-49
Z87000/Z87L00 Spread Spectrum Controllers
Zilog
INSTRUCTION SET DESCRIPTION (Continued)
Table 37. Instruction Set Summary Instruction Description
POP Pop value from stack
Opcode
0001010 0000100 0000010 0000000
Synopsis
POP
Operands

# # Words Cycles
1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 2 3 3 2 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 1 1 1 1 1 2 3 1 1 1
Example
POP P0:0 POP D0:1 POP @P0:0 POP A PUSH P0:0 PUSH D0:1 PUSH @P0:0 PUSH BU5 PUSH #12345 PUSH @A PUSH @@P0:0 RET RL NZ,A RL A RR C,A RR A SCF SIEF SLL NZ,A SLL A SOPF SRA NZ,A SRA A SUB A,P1:1 SUB A,D0:1 SUB A,#%2C2C SUB A,@D0:1 SUB A,%15 SUB A, @P2:0-LOOP SUB A, STACK XOR A, P2:0 XOR A,D0:1 XOR A,#13933 XOR A,@P2:1+ XOR A, %2F XOR A, @P2:0 XOR A, BUS
PUSH
Push value onto stack
PUSH 0001001 0000001 0000001 0000000 0000100 0100101 0000101 RET 0000000 RL ,A 1001000 1001000 ,A A RR ,A 1001000 1001000 ,A A SCF 1001010 None SIEF 1001010 None SLL 1001000 1001000 [,]A A SOPF 1001010 None SRA,A 1001000 1001000 SUB, 0011001 0010011 0010100 0010101 0010011 0010001 0010000 A, A, A, A, A, A, A, XOR , 1111001 1110001 1110100 1110001 1110011 1110001 1110000 A, A, A, A, A, A, A, ,A A None
RET RL
Return from subroutine Rotate Left
RR
Rotate Right
SCF SIEF SLL
Set C flag Set IE flag Shift left logical
SOPF SRA
Set OP flag Shift right arithmetic Subtract
SUB
XOR
Bitwise exclusive OR
1-50
PRELIMINARY
DS96WRL0501

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