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| CXB1581Q Fibre Channel Transmitter Description The CXB1581Q is a transmitter IC with a built-in PLL for high-speed serial data transmission. It can be used together with the receiver IC CXB1582Q as a chip set, and 1062.5Mbaud, 20-bit or 531.25Mbaud, 10-bit operation can be selected. Features * Conforms to ANSI X3T11 Fibre channel standard * Supports GLM (Gigabaud Link Module) interface * Built-in PLL for synthesizing a low-jitter clock * Single 3.3V power supply or dual 3.3V/5V power supply (for 5V TTL interface) operation can be selected. * Low power consumption: 830mW (Typ.) when operating with a single 3.3V power supply * 1062.5Mbaud, 20-bit or 531.25Mbaud, 10-bit operation can be selected. * Test pattern (K28.5) generation circuit 80 pin QFP (Plastic) Applications Fibre channel 1062.5Mbaud and 531.25Mbaud communications Structure Bipolar silicon monolithic IC Pin Configuration LDALM VEEP1 VCCG SDSEL LPF_A LPF_B R_FLT VEEP2 SDDIS VEEP1 REXT CLR VCCP VCCG VEEG VCCP LBEN TCLKSEL ECLKSEL 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VEEE 61 VEEE 62 EXCLK 63 EXCLK 64 SDIN 65 SDIN 66 VCCE 67 VCCE 68 SDOUT 69 SDOUT 70 VCCE 71 LBOUT 72 LBOUT 73 VCCE 74 VCCE 75 PSOUT 76 PSOUT 77 VEEE 78 TJMON1 79 TJMON2 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 NC 39 ALTSEL 38 TPGEN 37 PPSEL 36 SDRSEL 35 BYTSEL 34 TBC_IN 33 VCCG 32 VEEG 31 TX19 30 TX18 29 TX17 28 TX16 27 TX15 26 TX14 25 TX13 24 TX12 23 TX11 22 TX10 21 VEEG VEET LKDT TX00 VCCT5 TX05 TX06 VEET VCCT3 VCCG TBC_OUT FAULT Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- VCCG TX04 VEEG TX03 TX02 TX01 TX07 TX08 TX09 NC E95912A64-ST CXB1581Q Absolute Maximum Ratings (VEEE, VEET, VEEG, VEEP = 0V) Item Supply voltage (excluding VCCT5) Supply voltage for TTL output TTL DC input voltage ECL DC input voltage ECL differential input voltage TTL output current (High level) TTL output current (Low level) ECL output current Operating ambient temperature Storage temperature Symbol VCC VCCT5 VI_T VI_E VIS_E IOH_T IOL_T IO_E Ta Tstg Min. -0.3 VCCG - 2, or -0.3 -0.5 VCC - 2 -2 -20 0 -30 -55 -65 Typ. Max. 4 VCCG + 5, or 5.5 5.5 VCC 2 0 20 0 70 150 Unit V V V V V mA mA mA C C Recommended Operating Conditions (VEEE, VEET, VEEG, VEEP = 0V) During single 3.3V power supply operation Item Supply voltage (including VCCT5) Ambient temperature Symbol VCC Ta Min. 3.135 0 Typ. 3.3 Max. 3.465 70 Unit V C During dual 3.3V/5V power supply operation (VCCT3 open) Item Supply voltage (excluding VCCT5) Power supply for TTL output Ambient temperature Symbol VCC VCCT5 Ta Min. 3.135 4.75 0 Typ. 3.3 5 Max. 3.465 5.25 70 Unit V V C -2- CXB1581Q Block Diagram SDRSEL ALTSEL SDSEL SDIN SDIN 53.125Mbaud TX00 to 09 10 Parallel Data Input Buffer 53.125Mbaud TX10 to 19 10 10 10 P/S Converter 531.25 or 1062.5Mbaud 1 0 1 0 BYTSEL TPGEN SDDIS LBEN SDOUT SDOUT LBOUT LBOUT PSOUT PSOUT PPSEL TBC_EN 53.125MHz RQ RSFF S FAULT TBC_IN LPF_A 53.125MHz PLL 531.25 or 1062.5MHz TBC OUT LPF_B REXT 1 0 LKDT EXCLK ECLKSEL -3- LDALM R_FLT EXCLK TCLKSEL CXB1581Q Pin Description Pin No. Symbol Type Power supply Power supply Power supply Typical pin I/O voltage 0V Equivalent circuit Description Negative power supplies for internal logic gate. Positive power supplies for internal logic gate. Negative power supplies for TTL output. VCCT5 1, 21, VEEG 32, 49 2, 20, 33,50, VCCG 51 3, 4 VEET -- 3.3V -- 0V -- VCCT3 5 LKDT TTL output TTL level LKDT PLL lock detection signal output. This pin outputs low level when the PLL is locked to TBC_IN and operating normally, and high level when the PLL is not operating normally. VEET VCCT5 VCCT3 6 FAULT TTL output TTL level FAULT FAULT signal output. This pin is used for the FAULT signal in the GLM standard. This pin outputs high level at the rising edge of LDALM and low level at the falling edge of R_RLT. (See Table 3.) VEET VCCT5 VCCT3 7 TBC_OUT TTL output TTL level TBC_OUT Transmission byte clock output (53.125MHz). This clock is generated by frequency-dividing the transmission bit clock (1.0625GHz or 531.25MHz). VEET -4- CXB1581Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCT5 8 VCCT3 Power 3.3V or open supply VCCG VCCT3 VEET Positive power supply for TTL output. Set to 3.3V when using the IC with a single 3.3V power supply; leave open when using the IC with a dual 3.3V/5V power supply. VCCT5 9 VCCT5 Power supply VCCT3 3.3V or 5V VCCG Positive power supply for TTL output. Set to 3.3V when using the IC with a single 3.3V power supply; to 5V when using the IC with a dual 3.3V/5V power supply. VEET VCCG 10 to 19 TX00 to 09 TTL input TTL level TX00 to 09 Parallel data inputs (Byte_0). VEET VEET VCCG 22 to 31 TX10 to 19 TTL input TTL level TX10 to 19 Parallel data inputs (Byte_1). VEET VEET -5- CXB1581Q Pin No. Symbol Type Typical pin I/O voltage VCCG Equivalent circuit Description 34 TBC_IN TTL input TTL level TBC_IN Transmission byte clock input (53.125MHz). VEET VEET VCCG 35 BYTSEL TTL input TTL level BYTSEL Byte selection. (See Table 2.) VEET VEET VCCG 36 SDRSEL TTL input TTL level SDRSEL Serial data transmission rate selection. Setting this pin to low level selects 531.25Mbaud mode and to high level selects 1.0625Gbaud mode. VEET VEET VCCG 37 PPSEL TTL input TTL level PPSEL Ping-Pong mode selection. (See Table 2 and the Timing Charts.) VEET VEET -6- CXB1581Q Pin No. Symbol Type Typical pin I/O voltage VCCG Equivalent circuit Description 38 TPGEN TTL input TTL level TPGEN VEET VEET Test pattern generation control. Inputting high level to this pin generates positive or alternating disparity K28.5 (one of the 8B10B conversion codes) as the serial transfer data. VCCG 39 ALTSEL TTL input TTL level ALTSEL VEET VEET Alternating disparity selection. The test pattern generated when TPGEN is set to high level becomes alternating disparity K28.5 if this pin is set to low level, and positive disparity K28.5 if this pin is set to high level. 40, 41 NC Open No connection. VCCG 42 TTL ECLKSEL input TTL high level or 3.3V ECLKSEL External clock selection. When this pin is set to low level, the clock input to EXCLK is used as the transmission bit clock. VEET VEET VCCG 43 TCLKSEL TTL input TTL high level or 3.3V TCLKSEL Transmission bit clock output selection. When this pin is set to low level, the transmission bit clock is output from PSOUT. (See Table 1.) VEET VEET -7- CXB1581Q Pin No. Symbol Type Typical pin I/O voltage VCCG Equivalent circuit Description 44 SDSEL TTL input TTL level SDSEL SDIN selection. When this pin is set to high level, the data input to SDIN is output unmodified from SDOUT. VEET VEET VCCG 45 LBEN TTL input TTL level LBEN Loop-back enable. When this pin is set to high level, LBOUT functions as the serial data output. (See Table 1.) VEET VEET VCCG 46 SDDIS TTL input TTL level SDDIS SDOUT disable. Setting this pin to high level fixes SDOUT to low level and SDOUT to high level. (See Table 1.) VEET VEET VCCG 47 R_FLT TTL input TTL level R_FLT Reset FAULT. FAULT output goes to low level at the falling edge of this signal. (See Table 3.) VEET VEET -8- CXB1581Q Pin No. Symbol Type Typical pin I/O voltage VCCG Equivalent circuit Description 48 LDALM TTL input TTL lebel LDALM Laser diode alarm signal input. FAULT output goes to high level at the rising edge of this signal. (See Table 3.) VEET VEET VCCG 52 CLR TTL input TTL high level or 3.3V CLR Internal counter clear. Setting this signal to low level clears the internal counter. VEET VEET 53, 54 VCCP Power supply 3.3V -- Positive power supplies for internal PLL. VCCP 55 REXT External part connection pin -- REXT VEEP2 Connects the resistor which determines the VCO center frequency. Connect a 4.7k resistor between this pin and VEEP1. (See Notes on Operation and Fig. 1.) 56, 57 VEEP1 Power supply Power supply 0V -- Negative power supplies for internal PLL. Negative power supply for internal PLL. 58 VEEP2 0V -- -9- CXB1581Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description VCCP 59 LPF_A External part connection pin LPF_A LPF_B -- External loop filter connection. (See Notes on Operation and Fig. 1.) VEEP2 VEEP1 VCCP LPF_A 60 LPF_B External part connection pin LPF_B -- External loop filter connection. (See Notes on Operation and Fig. 1.) VEEP1 VEEP2 61, 62, VEEE 78 Power supply 0V -- Negative power supplies for ECL I/O. VCCE VCCG 64 63 EXCLK EXCLK ECL input (differen -tial) EXCLK Open EXCLK VCCE - 1.3V VEEE VEEG External clock inputs. When ECLKSEL is set to low level, the clock input to these pins is used as the transmission bit clock. EXCLK is biased to become low level when left open. VCCE VCCG 66 65 SDIN SDIN ECL input (differen -tial) SDIN ECL level SDIN VCCE - 1.3V Serial data inputs. When SDSEL is set to high level, the data input to these pins is output unmodified from SDOUT. VEEE VEEG - 10 - CXB1581Q Pin No. Symbol Type Typical pin I/O voltage Equivalent circuit Description 67, 68, 71, 74, VCCE 75 Power supply 3.3V -- Positive power supplies for ECL I/O. VCCE 70 69 SDOUT SDOUT ECL output (differen -tial) SDOUT ECL level SDOUT VEEE Serial data outputs for transmission. The serial data order is TX00 TX19 for 1GHz mode and TX00 TX09 (Byte_0) or TX10 TX19 (Byte_1) for 531MHz mode. VCCE 73 72 LBOUT LBOUT ECL output (differen -tial) LBOUT ECL level LBOUT Serial data outputs for loop-back test. VEEE VCCE 77 76 PSOUT PSOUT ECL output (differen -tial) PSOUT ECL level PSOUT Parallel/serial conversion outputs. These outputs are enabled when SDSEL is high level. (See Table 1.) VEEE VCCE TJMON1 79 80 TJMON1 TJMON2 Test pin Open TJMON2 Junction temperature measurement. VEEE - 11 - CXB1581Q Description of Operation Tables TCLKSEL L L L L L L L L H H H H H H H H SDSEL L L L L H H H H L L L L H H H H LBEN L L H H L L H H L L H H L L H H SDDIS L H L H L H L H L H L H L H L H SDOUT Serialized Data Fixed to Low Serialized Data Fixed to Low SDIN Fixed to Low SDIN Fixed to Low Serialized Data Fixed to Low Serialized Data Fixed to Low SDIN Fixed to Low SDIN Fixed to Low LBOUT Fixed to Low Fixed to Low Serialized Data Serialized Data Fixed to Low Fixed to Low SDIN SDIN Fixed to Low Fixed to Low Serialized Data Serialized Data Fixed to Low Fixed to Low SDIN SDIN PSOUT Trans. Bit Clock Trans. Bit Clock Trans. Bit Clock Trans. Bit Clock Trans. Bit Clock Trans. Bit Clock Trans. Bit Clock Trans. Bit Clock Fixed to Low Fixed to Low Fixed to Low Fixed to Low Serialized Data Serialized Data Serialized Data Serialized Data Table 1. ECL Output Selection Table SDRSEL L L L L H H H H BYTSEL L L H H L L H H PPSEL L H L H L H L H Operation mode 531Mbaud, Byte0 selected 531Mbaud, Byte0 selected 531Mbaud, Byte1 selected 531Mbaud, Byte1 selected 1062.5Mbaud, Ping-Pong OFF 1062.5Mbaud, Ping-Pong ON 1062.5Mbaud, Ping-Pong OFF 1062.5Mbaud, Ping-Pong ON TBC_OUT Trans. Byte Clock Fixed to Low Trans. Byte Clock Fixed to Low Trans. Byte Clock Trans. Byte Clock Fixed to Low Fixed to Low Table 2. Operation Mode Selection Table - 12 - CXB1581Q LDALM L LH HL L L LH H H R_FLT HL L L LH HL L LH HL FAULT L H H H L H H L Table 3. FAULT Function Table Timing Charts Tp_TBC Tl_TBC Th_TBC 2.0V 1.5V 0.8V TBC_IN Tir_TBC Tif_TBC Ts Th 2.0V VALID VALID 1.5V 0.8V Tir_TX TX00 to 19 or TX00 to 09 during Ping-Pong mode Tif_TX Ts Th VALID VALID 1.5V TX10 to 19 during Ping-Pong mode - 13 - CXB1581Q Electrical Characteristics DC Characteristics (under the recommended operating conditions) Item TTL high level input voltage TTL low level input voltage TTL high level input current TTL low level input current TTL high level output voltage Single 3.3V power supply Dual 3.3V/5V power supply TTL low level output voltage Single 3.3V power supply Dual 3.3V/5V power supply ECL high level input voltage ECL low level input voltage VIH_E VIL_E VCC - 1.17 VCC - 1.81 200 VCC - 1.05 VCC - 1.81 650 VOL_T 0.5 0.5 VCC - 0.88 VCC - 1.48 1000 VCC - 0.81 VCC - 1.55 V V V V mV V V mV AC coupling input 50 terminated to VCC - 2V 50 terminated to VCC - 2V 50 terminated to VCC - 2V Output pins open ICC 250 237 13 313 297 17 mA mA mA 3.3V power supply 5V power supply (VCCT5) Output pins open PD 0.83 0.85 1.1 1.12 W W IOL = 2mA IOL = 4mA VOH-T 2.2 2.6 V V IOH = -0.4mA IOH = -0.4mA Symbol aVIH_T VIL_T IIH_T IIL_T -400 Min. 2 0 Typ. Max. 5.5 0.8 20 Unit V V A A VIH = VCC VIL = 0 Conditions ECL differential input voltage VIS_E ECL high level output voltage VOH_E ECL low level output voltage VOL_E ECL output amplitude Current consumption Single 3.3V power supply Dual 3.3V/5V power supply Power consumption Single 3.3V power supply Dual 3.3V/5V power supply VOS_E - 14 - CXB1581Q AC Characteristics (under the recommended operating conditions) Item TX00 to 19 rise time TX00 to 19 fall time TBC_IN rise time TBC_IN fall time TTL output rise time Single 3.3V power supply Dual 3.3V/5V power supply TTL output fall time Single 3.3V power supply Dual 3.3V/5V power supply ECL output rise time ECL output fall time TBC_IN cycle TBC_IN low time TBC IN high time TX setup time TX hold time Deterministic jitter (p-p) Random jitter (p-p) Tor_E Tof_E Tp_TBC Tl_TBC Th_TBC Ts Th DJ RJ 18.2 6 6 1.8 1.8 0.02 0.18 0.07 0.23 18.8 Tof_T 3.5 3.2 400 400 22.2 ns ns ps ps ns ns ns ns ns Ul Ul K28.5 serial data output Serial data output 2.0 to 0.8V, CL = 10pF 2.2 to 0.6V, CL = 10pF 20 to 80%, CL 2pF 20 to 80%, CL 2pF Tor_T 3.5 3.2 ns ns 0.8 to 2.0V, CL = 10pF 0.6 to 2.2V, CL = 10pF Symbol Tir_TX Tif_TX Tir_TBC Tif_TBC Min. Typ. Max. 4.8 4.8 2.4 2.4 Unit ns ns ns ns Conditions 0.8 to 2.0V 2.0 to 0.8V 0.8 to 2.0V 2.0 to 0.8V - 15 - CXB1581Q Electrical Characteristics Measurement Circuit (See Fig. 3 Power Supply Circuits regarding the power supply.) II_T Measurement device TTL_IN TTL_OUT Io_T A VI_T V Vo_T (a) TTL I/O DC characteristics measurement circuit Measurement device Pulse generator TTL_IN TTL_OUT CL Probe Oscilloscope CL = 10pF (including the probe capacitance) (b) TTL I/O AC characteristics measurement circuit II_E Measurement device ECL_IN ECL_OUT 50 VCCE - 2V A VI_E V VO_E (c) ECL I/O DC characteristics measurement circuit VCCE - 2V 50 Pulse generator 50 50 Transmission Line VCCE - 2V VCCE - 2V CL 2pF (input capacitance of the measurement instrument and floating capacitance) VCCE - 2V 50 Oscilloscope 50 Measurement device ECL_IN ECL_IN ECL_OUT ECL_OUT (d) ECL I/O AC characteristics measurement circuit Measurement device 26.5625MHz Pulse pattern generator 53.125MHz 20 53.125MBPS TX00 to 19 TBC_IN SDOUT VCCE - 2V 50 Triger Oscilloscope 1.0625Gbps SDOUT 50 VCCE - 2V (e) Jitter characteristics measurement circuit - 16 - CXB1581Q Notes on Operation 1. Clock synthesizer (PLL) The CXB1581Q has a built-in PLL-based clock synthesizer for generating the serial data transmission frequency clock (transmission bit clock) from TBC_IN. This clock synthesizer requires an external loop filter and an external resistor which determines the VCO center frequency. The external part circuit and recommended constant values are shown in the figure below. The parasitic capacitance attached to the IC pins (Pins 55, 59 and 60) which are used to connect external parts should be kept as small as possible in order to obtain the good PLL characteristics. In addition, resistor R3 should have a small temperature coefficient to reduce the temperature dependence of the VCO oscillation frequency. 55 R3 56 57 58 R1 59 60 R2 C1 R1: 1.5k R2: 1.5k R3: 4.7k C1: 0.01F Fig. 1. External Part Circuit and Recommended Constants - 17 - CXB1581Q 2. ECL input circuit The ECL differential input pins (excluding EXCLK) of the CXB1581Q are biased to VBB (VCC - 1.3V) via an 18k resistor in the IC. See the figures below for ECL differential input methods. VCC = 3.3V, VEE = GND VCC = 3.3V, VEE = GND VBB (VCC - 1.3V) 18k 18k 160 3.3V ECL output buffer 160 ECL differential input buffer (a) ECL differential signal from 3.3V ECL output buffer VCC = GND, VEE = -4.5V 0.01F VCC = 3.3V, VEE = GND VBB (VCC - 1.3V) 18k 0.01F 330 ECL100K output buffer 330 VEE 18k ECL differential input buffer (b) ECL differential signal from ECL100K output buffer 0.01F 50 TRANS. LINE 0.01F 50 50 VTT (VCC - 2V) VCC = 3.3V, VEE = GND VBB (VCC - 1.3V) 18k 18k ECL differential input buffer (c) ECL differential signal from 50 transmission line VCC = 3.3V, VEE = GND VBB (VCC - 1.3V) 0.01F 50 TRANS. LINE 18k 50 VTT (VCC - 2V) 0.01F 18k ECL differential input buffer (d) ECL single signal from 50 transmission line Fig. 2. ECL Input Circuits - 18 - CXB1581Q 3. Power supply Power can be supplied to the CXB1581Q by either a single 3.3V power supply or a dual 3.3V/5V power supply. When a TTL output high level of 2.2V is sufficient (for example, when only interfacing with a 3.3V CMOS), use a single 3.3V power supply. When a TTL output high level of greater than 2.2V is required (for example, when interfacing with a 5V TTL/CMOS), use a dual 3.3V/5V power supply. VCCT5 VCCT3 VCCE VCCG VCCP 3mH 3mH 3.3V 22F 0.1F 22F 0.1F 22F 0.1F VEET VEEE VEEG VEEP1 VEEP2 (a) Single 3.3V power supply VCCT5 VCCE VCCG VCCP 3mH 5.0V 22F 0.1F 3.3V 22F 0.1F 22F 0.1F VEET VEEE VEEG VEEP1 VEEP2 (b) Dual 3.3V/5V power supply Fig. 3. Power Supply Circuits - 19 - CXB1581Q Example of Representative Characteristics Jitter transfer (1.0625GHz operation) 5 R1 = R2 = 1.5k 0 -5 Jitter transfer [dB] R1 = R2 = 1.0k -10 -15 -20 C1 = 0.01F R3 = 4.7k Ta = 27C -25 101 102 103 104 105 Modulation frequency [MHz] 106 107 108 RJ temperature characteristics (SDOUT, 1.0625GHz operation) 15 14 RJ [ps-RMS-] 13 12 11 R1 = R2 = 1.5k C1 = 0.01F R3 = 4.7k TBC_IN: 53.125MHz 10 -20 0 20 Ta [C] 40 60 80 - 20 - CXB1581Q Exampe of RJ measurement (SDOUT, 1.0625GHz operation) R1 = R2 = 1.5k C1 = 0.01F R3 = 4.7k Ta = 27C RJ = 12.1ps (RMS) [50ps/div] Eye pattern (SDOUT, 1.0625GHz operation) [200mV/div] R1 = R2 = 1.5k C1 = 0.01F R3 = 4.7k Ta = 27C [200ps/div] - 21 - CXB1581Q Package Outline Unit: mm 80PIN QFP (PLASTIC) + 0.35 1.5 - 0.15 + 0.1 0.127 - 0.05 0.1 41 40 16.0 0.4 + 0.4 14.0 - 0.1 60 61 80 1 0.65 20 21 + 0.15 0.1 - 0.1 0.12 M 0 to 10 PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-80P-L03 LQFP080-P-1414 LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 0.6g - 22 - 0.5 0.2 + 0.15 0.3 - 0.1 (15.0) |
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