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IR3Y30M/M1
IR3Y30M/M1
DESCRIPTION
The IR3Y30M/M1 are bipolar single-chip signal processing ICs with built-in low-pass filter and delay line for B/W video cameras. They realize both downsizing and cost reduction of the finished set.
CCD Signal Processors for B/W CCD Cameras
FEATURES
* Low power consumption : 265 mW (TYP.) * Wide AGC range : -3 to +29 dB * High speed sample-and-hold circuits : pulse width 15 ns (MIN.) * Signal processing from CCD output to 75 $ video output is possible * Built-in low-pass filter * Built-in comparator for electronic exposure control * Built-in aperture circuit and delay line * Single +5 V power supply * Packages - IR3Y30M : 48-pin QFP (QFP048-P-1010) - IR3Y30M1 : 48-pin QFP (QFP048-P-0707) 0.5 mm pin-pitch
COMPARISON TABLE
Package Power consumption PD derating ratio Operating temperature IR3Y30M 48-pin QFP (QFP048-P-1010) 725 mW 5.8 mW/C -30 to +75 C IR3Y30M1 48-pin QFP (QFP048-P-0707) 560 mW 4.5 mW/C -30 to +70 C
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1
IR3Y30M/M1
PIN CONNECTIONS
48-PIN QFP
PGND FCDS FS PVCC CDS OUT CLAMP1 AGC OP IN MAX GAIN AGC OP OUT AGC CTRL VC VREF
TOP VIEW
48 47 46 45 44 43 42 41 40 39 38 37 CCD IN 1 CLAMP BIAS 2 IRIS GAMMA 3 WINDOW 4 IRIS OUT 5 VCC1 6 GND1 7 EE NR 8 SET NR 9 IRIS IN 10 SET UP 11 EE UP 12 13 14 15 16 17 18 19 20 21 22 23 24 SYNC BLK CLP BCLIP VCC2 VIDEO OUT PEDESTAL WCLIP CLAMP2 AMP2 OUT GAIN CTRL C3 C2 36 AGC OUT 35 LPF ADJ 34 AMP1 IN 33 C1 32 AGC DET 31 GND2 30 GAMMA ADJ 29 KNEE ADJ 28 GAMMA OUT 27 DL ADJ 26 HAPA IN 25 APA CTRL
(QFP048-P-1010) (QFP048-P-0707)
2
5V
+ FCDS FS 47 FCDS 46 45
PVcc - - BLK + + CLAMP1 AGC CTRL AGC OP MAX GAIN OUT VC FS
BLOCK DIAGRAM
48 PGND AGC OP AMP LPF
CLP
44 CDS OUT 43 VREF CLAMP AMP1 CLEANING
42 AGC OP IN
40
41 39
38
37 VREF 35 LPF ADJ 36 AGC OUT
34 AMP1 IN
C1 33
CCD
1
CCD IN
GND2
31 32
AGC DET
CLAMP
S/H
2 CLAMP H CLIP + AGC -
CLAMP BIAS
3
IRIS GAMMA
4
IRIS AMP + - CLP
WINDOW
GAMMA KNEE
GAMMA ADJ
30
KNEE ADJ
WINDOW
5
WINDOW
IRIS GAMMA
29
IRIS OUT
BLK
8
CLP + - IRIS COMP + -
EE NR
AMP2
+ CLP - GAMMA OUT
3
PEDESTAL SYNC W CLIP
BUFF CLP
9
28 DL
APA AMP + - + - DL ADJ
SET NR
10 IRIS IN
IRIS OP AMP + -
27 26 BASE CLIP MIX
CLP HAPA IN
11 SET UP
25 CLAMP
+ - AMP2 OUT GAIN CTRL C3 BCLIP APA CTRL
12 EE UP PULSE SEPA
Vcc2 BLK CLP SYNC
Vcc1
GND1
6
5V
7 + OUT SYNC BLK CLP +
14
BLK CLP
16
17
VIDEO OUT
13
18
PEDESTAL
19
WCLIP
20
CLAMP2
21
22 23 15
24
C2
5V
+
IR3Y30M/M1
IR3Y30M/M1
PIN DESCRIPTION
PIN NO. PIN NAME VOLTAGE
VCC1
9k
EQUIVALENT CIRCUIT
DESCRIPTION Input for the signal from CCD area sensor. 2.5 V bias applied internally.
25 k
1
CCDIN
2.5 V
1
200
25 k
9k
GND VCC1
9k
Feed through level of the input signal is clamped to this pin voltage.
21 k
2
CLAMP BIAS
2.9 V
2
2.9 V bias applied internally. Connect capacitor between this pin and GND.
200
29 k
9k
GND VCC1
25 k 200
Gamma adjustment of the exposure circuit. This pin is preset to 3.1 V, and gamma becomes 0.45 at open.
3
IRIS GAMMA
3.1 V
3
6.4 k
33.8 k
25 k 25 k
GND VCC1
18.8 k 1k
Window pulse input for the exposure circuit. Outputs the signal while "H".
4
WINDOW
4 7k 190
GND VCC1
20 k 50
Output for the exposure signal. Connect a resistor between this pin and GND.
5
IRIS OUT
2.3 V
1k 5
GND
4
IR3Y30M/M1
PIN NO. PIN NAME VOLTAGE 6 VCC1 7 GND1
VCC1
50 k 200
EQUIVALENT CIRCUIT
DESCRIPTION Power supply for analog circuits. Ground for analog circuits. Comparator output for electronic exposure control.
8
EE NR
8
GND VCC1
2
High reference voltage input of the comparator for electronic exposure control. Input of the amplifier for electronic exposure control. This amplifier has 5 times gain.
GND
9
SET NR
200
10
IRIS IN
11
SET UP
VCC1
50 k 200
Low reference voltage input of the comparator for electronic exposure control. Output of the comparator for electronic exposure control.
12
EE UP
12
GND VCC1
40
Synchronous signal input.
5k
13
SYNC
13
GND
5
IR3Y30M/M1
PIN NO. PIN NAME VOLTAGE
VCC1
40 5k
EQUIVALENT CIRCUIT
DESCRIPTION Composite pulse input. (pulse for optical black clamp and pulse for blanking)
14
BLK CLP
14
5k
40
GND VCC1
40
Adjustment for the base clip level in the aperture circuit. Eliminates the low-level noise of aperture signal. When opened, base clip is canceled.
15
BCLIP
15
5k
GND
16
VCC2
VCC2
100
Power supply for output amplifier circuits. Video signal output. At 75 $ terminated : 1 Vp-p (Synchronous level 0.3 Vp-p)
17
17
VIDEO OUT
1.5 V
GND VCC2
Blanking level adjustment. 100 mV when opened.
45 k 5k
18
PEDESTAL
2.5 V
18 100
GND
6
IR3Y30M/M1
PIN NO. PIN NAME VOLTAGE
VCC2
EQUIVALENT CIRCUIT
DESCRIPTION White clip adjustment. 120% when opened.
35 k
15 k
19
WCLIP
3.3 V
19 50 100
GND VCC2
Input for encoder circuit. Black level of input signal is clamped to 2.3 V.
20
CLAMP2
2.3 V
20 5k 5k 50
GND VCC1
50 100
Output for the gain control amplifier.
21
AMP2 OUT
1.0 V
100
21
1m
GND VCC1
Controls the output amplitude at pin No. 21.
39 k 10 k 1.8 k 200 200
22
GAIN CTRL
2.5 V
22
Gain is controlled in the range from 6 to 12 dB. It is approximately 10 dB when this pin is open.
GND
VCC1
50
Feedback clamp detector. Connect capacitor between this pin and GND.
23
C3
1.8 V
23 3p 50 5 k
3p
GND
7
IR3Y30M/M1
PIN NO. PIN NAME VOLTAGE
VCC1
50 200 50
EQUIVALENT CIRCUIT
DESCRIPTION Feedback clamp detector. Connect capacitor between this pin and GND. When the external DL circuit is used, this will be input pin to make the aperture signal.
24
C2
1.8 V
24 3p 50 3p 5k
GND VCC1
40
Adjustment for the horizontal aperture amount. It is approximately 12 dB when this pin is open.
25
APA CTRL
1.8 V
25
30.5 k
19.5 k
100
GND VCC1
Input for signal from pin 28. This signal is used as a main signal when aperture signals are mixed.
200
26
HAPA IN
26 200 100
GND VCC1
Adjustment for built-in delay line. When 200 k$ resistor is connected between this pin and GND, delay line can be turned off.
27
DL ADJ
1.2 V
27
200
4k
10 k
GND VCC1
Gamma and knee processed signal output.
28
GAMMA OUT
2.3 V
28 220
GND
8
IR3Y30M/M1
PIN NO. PIN NAME VOLTAGE
VCC1
1k 40 k 10 k
EQUIVALENT CIRCUIT
DESCRIPTION Knee adjustment. 120% when opened.
29
KNEE ADJ
2.8 V
29 100
GND VCC1
10 k
Gamma correction adjustment. 0.7 when opened.
30
GAMMA ADJ
40 k
10 k
2.0 V
30 200 100
GND
31
GND2
VCC1
50
Ground for analog circuits. Signal output for AGC control. Connect resistor between this pin and GND.
1k
32
AGC DET
2.0 V
32 100
GND VCC1
25
Feedback clamp detector. Connect capacitor between this pin and GND.
33
C1
2.0 V
33
1p
50 1p 10 k
GND VCC1
10 k
Input for gamma and knee signal process.
200
34
AMP1 IN
34 170 1.65 k 250
GND
9
IR3Y30M/M1
PIN NO. PIN NAME VOLTAGE
VCC1
5p 1k 3k
EQUIVALENT CIRCUIT
DESCRIPTION Adjustment for built-in LPF characteristic. When connected resistor is 220 k$ or more between this pin and GND, LPF can be turned off.
35
LPF ADJ
35
200
GND VCC1
100
AGC signal output.
100
36
AGC OUT
2.3 V
36 400
GND VCC1
Reference voltage.
200
37
VREF
2.0 V
37
GND VCC1
22 k 200
Bias for reference voltage. Connect capacitor between this pin and GND.
38
VC
2.0 V
38 8k 20 k
GND VCC1
Gain control for AGC amplifier. Be sure to input the voltage within the range from 2 to 4 V.
5k
39
AGC CTRL
39
50
GND
10
IR3Y30M/M1
PIN NO. PIN NAME VOLTAGE
VCC1
EQUIVALENT CIRCUIT
DESCRIPTION Output of the operation at amplifier for AGC control.
40
AGC OP OUT
200 40
GND VCC1
Adjustment for AGC amplifier maximum gain. Maximum gain is 18 dB when opened. When applied
41
MAX GAIN
22 k
3.3 V
41
28 k 50 200
voltage is 0.62 V or less, AGC circuit turns off and the amplifier is fixed to 0 dB.
GND VCC1
2
The operational amplifier for AGC control.
42
AGC OP IN
200 42
GND VCC1
1k
Input of AGC amplifier. Black level is clamped at 2.0 V.
43
CLAMP1
2.0 V
43 50 1k
GND VCC1
100
CDS signal output.
100
44
CDS OUT
2.4 V
44 750
GND
11
IR3Y30M/M1
PIN NO. PIN NAME VOLTAGE 45 PVCC
PVCC
100 200
EQUIVALENT CIRCUIT
DESCRIPTION Power supply for pulse circuits. Pulse input for sample-hold.
46
FS
46
PGND PVCC
200 200
Pulse input for feed-through level clamp.
47
FCDS
47
PGND
48
PGND
Ground for pulse circuits.
12
IR3Y30M/M1
FUNCTIONAL OPERATION CDS Circuit
The feed-through level of the input signal is clamped by the clamp circuit. Then the signal period is sampled and other periods are held by the sample and hold circuit, so that signals can be obtained.
Exposure Circuit
Signals which have not been processed by AGC are amplified, suppressed by gamma correction, and then output. Control signals can be generated by inputting the above signals to pin 10 after detecting them.
Aperture Circuit
CCD Signal
FCDS FS CDS OUT
The video articulation can be increased by enhancing the signal contour. If the built-in delay line is not used, it can be turned off by using an external resistor of minimum 200 k$ at pin 27. To control the aperture amount, use a base clip.
Gamma Output
Highlight Clip Circuit
Before the AGC circuit, excessive signals of more than approximately 0.5 Vp-p are clipped.
Aperture Signal AMP2 Output
AGC Amplifier Circuit
The amplitude of output signals from the AGC amplifier is externally detected and the gain is controlled with control signals from the AGC operational amplifier. Decreasing voltage at pin 41 to 0.62 V or less causes the amplifier to be fixed to 0 dB.
Output Circuit
A load of 75 $ can be driven directly. In addition, the pedestal level can be controlled vertically. CAUTIONS
LPF Circuit
The characteristics can be controlled with an external resistor at pin 35. Increasing the resistor to 220 k$ or more allows signals passing over the LPF to be output.
Gamma and Knee Corrections Circuits
In order to comply with the characteristics of CRT, the high-bright part is suppressed. Pin 29 and 30 can be used to control this suppression. If voltage at pin 30 is increased to 4 V or more gamma will be 1.
* To control the aperture amount, apply base clip by controlling pin 15. * Avoid connecting or disconnecting an external resistor at pin 27 to prevent the malfunction of the built-in delay line. * Use the shortest possible distance to connect the bypass capacitors between the power supply and GND pins. The addition or removal of any external component should be determined by how the existing components are mounted. * This device is electronically sensitive. Handle only at electrostatically safe work stations.
13
IR3Y30M/M1
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage Input voltage Comparator output voltage Power consumption PD derating ratio Operating temperature Storage temperature TOPR TSTG SYMBOL VCC1, VCC2 PVCC VIA VIP VSD PD CONDITIONS
(Unless otherwise specified, TA = +25 C)
RATING IR3Y30M 7 7 Except for pins 46 (FS) and 47 (FCDS) Pins 46 (FS) and 47 (FCDS) TA +25 C TA > +25 C VCC -0.2 to PVCC + 0.2 VCC 725 5.8 560 4.5 IR3Y30M1 UNIT V V V V V mW mW/C C C
-30 to +75 -30 to +70 -55 to +150
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply voltage H-aperture signal Standard CCD input signal Clamp pulse width Sample-hold pulse width SYMBOL APPLICABLE PINS VCC Pins 6 (VCC1), 16 (VCC2) and 45 (PVCC) VH-AP Pin 26 (HAPA IN) VCCD tFS tFCDS Pin 1 (CCD IN) Pin 46 (FS) Pin 47 (FCDS) RATING 4.75 to 5.25 600 (MAX.) 200 (TYP.) 15 (MIN.) 15 (MIN.) UNIT V mVp-p mVp-p ns ns
14
IR3Y30M/M1
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, TA = +25 C, VCC = 5.0 V, SW conditions/(a), V26 = 2.3 V, V34 = 2.0 V, V39 = 3 V, R27 = 30 k$, R35 = 22 k$)
PARAMETER Supply current CDS Circuit With signal 1 applied to SG1, measure the Low frequency attenuation signal attenuation on TP44. FS = 5 V, FCDS GLF = Signal 2 (FCDS), VA = TP44 amplitude (f = 100 kHz), VB = TP44 amplitude (f = 10 MHz) GLF = 20*LOG (VA/VB) Signal 2 applied to SG1, FS and FCDS, Gain Clamp bias GCDS VCP/BIAS V42 = 3 V, Measure the voltage on TP40B. SW40, SW42/(b) I40 = +200 A V42 = 1 V, I40 = -200 A 3.9 measure the amplitude on TP44. SG1 = 200 mVp-p, f = 10 MHz 2.7 2.9 3.1 V AGC Operational Amplifier Circuit Low level High level AOPL AOPH 1.0 4.1 1.2 V -2 0 2 dB -30 -25 dB SYMBOL CONDITIONS ICC1 Measure pin 6 (VCC1). ICC2 ICC3 Measure pin 16 (VCC2). Measure pin 45 (PVCC). MIN. TYP. 43.0 5.7 4.3 MAX. 54.5 7.8 5.4 UNIT mA mA mA
Exposure Operational Amplifier & Comparator Circuits With V10 = 2.3 V, measure the voltage of V9a (TP8 : L/H) and V11a (TP12 : H/L). Operational amplifier gain GOP With V10 = 2.4 V, measure the voltage of V9b (TP8 : L/H) and V11b (TP12 : H/L). GOP = (V9b-V9a) or (V11b-V11a) SW9, SW10, SW11/(b) Comparator low level High level AGC Circuit Change the amplitude of signal 3 which is applied to SG43, and measure the amplitude Highlight clip level HCL on TP36 when TP36's output signal is clipped. SW43, SW41/(b), Pulse/CLP, V41 = 0 V, R35 = 220 k$ 0.4 0.5 0.6 Vp-p IOPL IOPH Change the voltage of V9 and V11, and measure the voltage on TP8 and TP12. V10 = 2.3 V SW9, SW10, SW11/(b) 4.70 0 4.95 0.2 V 0.40 0.46 0.51 V
15
IR3Y30M/M1
PARAMETER AGC circuit (contd.) AGC maximum gain (1) AGC maximum gain (2) AGC minimum gain AGCOFF gain SYMBOL CONDITIONS Apply signal 3 to SG43 and measure the amplitude on TP36. GA1 to GA4 = 20*LOG (TP36 amplitude/SG43 amplitude) SW41, SW43/(b), Pulse/CLP, R35 = 220 k$ SG43 = 20 mVp-p V39 = 4 V, V41 = 5 V SG43 = 20 mVp-p V39 = 4 V, SW41/(a) SG43 = 400 mVp-p V39 = 2 V, V41 = 5 V SG43 = 200 mVp-p V39 = 4 V, V41 = 0 V MIN. TYP. MAX. UNIT
GAMAX1 GAMAX2 GAMIN GAOFF
27 15.5 -6.5 -2
29 18.0 -3.5 0
31 20.5 dB -0.5 2
Output dynamic range
Apply signal 3 to SG43 and measure the amplitude on TP36. DA SG43 = 50 mVp-p, SW41, SW43/(b), Pulse/CLP, V39 = 4 V, V41 = 5 V, R35 = 220 k$ Apply signal 4 to SG43. Increase the frequency of fA1 0.55 0.75 Vp-p
Frequency characteristic (1)
SG43 = 10 mVp-p 3.5 4.5 MHz SG43 = 200 mVp-p R35 = 220 k$ 7.0 10.0
R35 = 22 k$ signal 4 until the frequency V39 = 4 V components of the signal on TP36 are 3 dB lower than that at f = 100 kHz, and measure the frequency of signal 4. SW41/(b), Pulse/CLP, V41 = 5 V When measuring case (2), adjust the V39 such that the amplitude of the output on
Frequency characteristic (2)
fA2
SG43 = 10 mVp-p R35 = 22 k$ V39 = 4 V f = 9.5 MHz -35 -25 dB
Frequency characteristic (3)
fA3
TP36 is 200 mVp-p. Apply signal 3 to SG43, change V41, and AGC ON/OFF switching voltage
VAGC
measure the voltage of V41 when the gain on TP36 changes from -3.5 to 0 dB. The gain on TP36 : 20*LOG (TP36 amplitude/SG43 amplitude) SG43 = 400 mVp-p, SW43, SW41/(b), Pulse/CLP, V39 = 2 V, R35 = 220 k$
0.4
0.6
0.8
V
Reference voltage 1 Reference voltage 2
VREF VREF2
Measure the voltage on TP37A. With I37 = +500 A, measure the change in voltage on TP37B. SW37/(b) With I37 = -500 A, measure the change in
1.84 0
1.94 0.15
2.04 0.30
V V
Reference voltage 3
VREF3
voltage on TP37B. SW37/(b)
-0.30
-0.15
0
V
16
IR3Y30M/M1
PARAMETER Exposure Circuit Exposure AMP gain Gamma output level Output dynamic range Black level Black level offset 1 Black level offset 2 GI PRE DI BI BIOFF1 BIOFF2 Apply signal 3 to SG43 and measure the amplitude on TP5. SW3, SW4, SW43/(b), Pulse/CLP, BLK SG43 = 200 mVp-p V3 = 5 V, V4 = 5 V SW3/(a) SG43 = 800 mVp-p V3 = 5 V, V4 = 5 V 10.5 0.25 1.5 2.15 -50 -50 11.5 0.32 1.9 2.30 0 0 2.45 50 50 12.5 0.40 dB Vp-p Vp-p V mV SYMBOL CONDITIONS MIN. TYP. MAX. UNIT
Measure the voltage on TP5. SW4/(b), Pulse/CLP, BLK, V4 = 0 V Measure the voltage on TP5. V4 = 5 V SW4/(b), Pulse/CLP, BLK V4 = 0 V Apply signal 4 to SG43. Increase the frequency of signal 4 until the frequency components of the signal on TP5 are 3 dB
Frequency characteristic
fI
lower than that at f = 100 kHz, and measure the frequency of signal 4. SG43 = 200 mVp-p, V4 = 5 V, SW4, SW43/(b), Pulse/CLP, BLK Apply signal 3 to SG43 and measure the
0.7
1.1
MHz
Window OFF output level
OWOFF
amplitude on TP5. SG43 = 200 mVp-p, SW4, SW43/(b), Pulse/CLP, BLK, V4 = 0 V Same as in the window OFF output level
40
70
mVp-p
Window ON switching voltage
VW
measurement. Increase V4, and measure V4 when the amplitude of output signal on TP5 is not changed. With V4 = 5 V, measure input current on pin 4. SW4/(b) Apply signal 3 to SG34 and measure the
1.2
1.4
1.6
V
Window input current AMP1 Circuits AMP1 gain Output dynamic range Black level Gamma gain (1) Gamma gain (2) Gamma gain (3)
IW
0.5
1.2
3.0
A
GAMP1
amplitude on TP32. SW34/(b), Pulse/CLP, BLK, SG34 = 100 mVp-p, Black level = 2 V Same as in the AMP1 gain measurement. Measure output dynamic range on TP32. Measure the voltage on TP32. Pulse/CLP, BLK Apply signal 3 to SG34 and measure the amplitude on SG34 = 100 mVp-p
13
14
15
dB
DAMP1 BAMP1 G1 G2 G3
1.20 1.9 310
1.40 2.0 410 -6.4 2.1 510
Vp-p V mVp-p dB
Gamma & Knee Circuits
SG34 = 30 mVp-p TP28. SW34/(b), Pulse/CLP, BLK, Input black level = 2 V SG34 = 200 mVp-p
1.3
17
IR3Y30M/M1
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT
Gamma & Knee Circuits (contd.) Apply signal 3 to SG34 and measure the Gamma OFF gain GOFF amplitude on TP28. SW29, SW30, SW34/(b), Pulse/CLP, BLK, SG34 = 100 mVp-p, Black level = 2 V, V29 = 5 V, V30 = 5 V Measure the amplitude of SW30/(a) TP28 between BLK level and SW30/(b), black level. Pulse/CLP, BLK V30 = 5 V Apply signal 4 to SG34. Increase the frequency of signal 4 until the frequency components of the signal on TP28 are 3 dB f lower than that at f = 100 kHz, and measure the frequency of signal 4. SW34/(b), Pulse/CLP, BLK, SG34 = 100 mVp-p, Black level = 2 V Aperture & AMP2 Circuits Aperture maximum GAPMAX gain Aperture preset gain Aperture minimum gain Base clip output GAPPRE GAPMIN BCL SW25/(b), V25 = 5 V SW25/(b), V25 = 0 V 6.0 MHz 450 510 580 mVp-p
(1) CL1 Cleaning offset (2) CL2
-50 -50
0 0
50 50 mV
Frequency characteristic
Apply signal 3 to SG26 and measure the amplitude on TP21. SW26A/(b), Pulse/CLP, BLK, SG26 = 100 mVp-p, Black level = 2.3 V
840 740 320 250
1 130 840 420 350 940 520 450 mVp-p
SW15/(b), V15 = 0 V SW25/(b), V25 = 5 V Apply signal 3 to SG34 and measure the amplitude on TP21. SW15, SW23, SW25, SW29, SW30, SW34/(b), Pulse/CLP, BLK,
Delay line output
DLOUT
1 100
1 700
mVp-p
SG34 = 50 mVp-p, Black level = 2 V, V15 = V25 = V29 = V30 = 5 V, V23 = 1.2 V, V26 = 2.3 V Apply signal 3 to SG26 and AMP2 maximum gain GAMP2MAX measure the amplitude on AMP2 minimum gain GAMP2MIN TP21. Pulse/CLP, BLK, Output dynamic range SG26 = 100 mVp-p, V22 = 5 V SG26 = 100 mVp-p, 370 180 2 000 440 230 2 550 510 280 mVp-p
DAMP2
SW15, SW22, SW25, SW26A/(b), V22 = 0 V Input black level = 2.3 V, SG26 = 800 mVp-p, V22 = 5 V V15 = V25 = 0 V Apply signal 4 to SG26. Increase the frequency of signal 4 until the frequency components of the signal on TP21 are 3 dB lower than that at f = 100 kHz, and measure the frequency of signal 4. SW15, SW25, SW26A/(b), V15 = 0 V, V25 = 0 V, Pulse/CLP, BLK, SG26 = 100 mVp-p, Black level = 2.3 V
Frequency characteristic
fAMP2
8.0
MHz
18
IR3Y30M/M1
PARAMETER Encoder Circuit White clip (1) White clip (2) White clip preset Setup (1) Setup (2) Setup preset SYNC level SYMBOL WC1 WC2 WCPRE SUP1 SUP2 SUPPRE VSYNC CONDITIONS Apply signal 3 to SG20 and measure the amplitude on TP17A. SW19/(b), V19 = 5 V SW19/(b), V19 = 0 V SW19/(a) MIN. 1.9 TYP. 2.0 0.85 1.75 230 1.85 280 -310 -150 530 -100 580 -260 -50 630 mV mV 0.95 1.95 V MAX. UNIT
SW20/(b), Pulse/CLP, BLK Measure the amplitude of SW18/(b), V18 = 5 V TP17A between BLK level SW18/(b), V18 = 0 V and black level. SW18/(a) Pulse/CLP, BLK Measure the amplitude of TP17A between SYNC level and black level. Pulse/CLP, BLK, SYNC Apply signal 3 to SG20 and measure the
Gain
GOUT
amplitude on TP17A. SW20/(b), Pulse/CLP, BLK, SG20 = 1 Vp-p Apply signal 3 to SG20 and measure the
-1
0
1
dB
Output dynamic range
DOUT
amplitude of TP17A between SYNC level and white level. SW19, SW20/(b), V19 = 5 V, Pulse/CLP, BLK, SYNC Apply signal 4 to SG20. Increase the frequency of signal 4 until the frequency
2.2
2.5
Vp-p
Frequency characteristic
fOUT
components of the signal on TP17B are 3 dB lower than that at f = 100 kHz, and measure the frequency of signal 4. SG20 = 1 Vp-p, SW17, SW20/(b), Pulse/CLP, BLK, SYNC Apply signal 3 to SG20 and measure the
10
MHz
Output voltage
VOUT
amplitude of TP17B between SYNC level and white level. SG20 = 1.3 Vp-p, SW17, SW20/(b), Pulse/CLP, BLK, SYNC
0.9
1.0
Vp-p
Pulse Circuit Clamp threshold voltage Sample-hold threshold voltage Synchronous signal threshold voltage Blanking threshold voltage Clamp threshold voltage
VFCDS VFS VSYNC VBLK VCP Apply voltages to FCDS, FS, SYNC, BLK and CLP and measure the threshold voltage of each circuit.
1.3 1.5 2.5 1.5 3.5 V
19
IR3Y30M/M1
Measurement Waveforms
Signal 1 Sine wave amplitude : 200 mVp-p Low frequency attenuation : 100 kHz/10 MHz (10 MHz = 0 dB)
Signal 2 (Input) T/2 (FCDS) T/4
2T Input level H level
L level H level T/4 (FS) T = 1/f BLK 11 s Blanking Pulse CLP 5V 3 s 0V Clamp Pulse SYNC 4.7 s Sync Pulse 0V 5V 0V f : sampling rate L level
5V
WINDOW Window pulse Signal 3
0V
Signal 4
100% 50%
20
IR3Y30M/M1
Test Circuit
SG34
~
TP32 R27 B
SG26
~
R35 V34 TP36
V26 V25 A
V30 47 k$
V29 TP28
TP37A 37 0.01 F TP37B V39 TP40A 40 TP40B V41 V42 41 42 38 39
36
35
0.01 F 34 33
32
31
30
29
28
27
26
25 0.01 F 24 V23 23 22 21 20 0.01 F 19 18 17 16 0.01 15 14 13 V22 TP21 SG20 0.01 F
~
V19 TP17B V18 + 56 470 75 $ $ F TP17A + 47 F
10 k$
~
SG43 0.01
43 0.01 F 44 TP44 45 46 100 $ 47 48 1 2 3 4 100 k$ V3 V4 5 6 7 8 TP8 V9 V10 V11 9 10 11 12
+ 47 F 100 $ FS
V15 CLP BLK SYNC
FCDS
10 k$ 10 k$
+ 47 F 0.01 F SG1
~
0.01 F +
TP12
47 F
TP5
5V Switching Polarity
(a) (b)
21
PACKAGES FOR CCD AND CMOS DEVICES
PACKAGES
48 QFP (QFP048-P-1010)
0.75TYP. 36 0.330.1 (1.75) 25 0.150.05
(Unit : mm)
0.15
M
37
24 10.00.2 13.50.4
48
13 (1.75)
1 (1.75) 10.00.2 13.50.4
12 (1.75) 0.850.2 1.450.2 0.10.1
48 QFP (QFP048-P-0707)
0.5TYP. 36 M 37 0.08
0.20.08 (1.0) 25 24 7.00.2 9.00.3
Package base plane
0.150.05
1 (1.0)
7.00.2 9.00.3
12 (1.0)
(1.0)
48
13
0.650.2 1.450.2 0.10.1
22
Package base plane
8.00.2
0.1
(11.5)
0.15

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