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| QUINT 2-INPUT OR/NOR GATE FEATURES s s s s s s s s s Max. propagation delay of 700ps IEE min. of -45mA Industry standard 100K ECL levels Extended supply voltage option: VEE = -4.2V to -5.5V Voltage and temperature compensation for improved noise immunity Internal 75K input pull-down resistors 50% faster than Fairchild 300K Function and pinout compatible with Fairchild F100K Available in 24-pin CERPACK and 28-pin PLCC packages SY100S302 DESCRIPTION The SY100S302 offers five 2-input OR/NOR gates designed for use in high-performance ECL systems. The five gates are controlled by a common Enable signal. All inputs have 75K pull-down resistors and all outputs are buffered. PIN CONFIGURATIONS D1a Oa VEES D2a Oa Ob Ob 11 10 9 8 7 6 5 D1b D2b VEE VEES E D1c D2c 12 13 14 15 16 17 18 4 3 2 1 28 27 26 Oc Oc VCCA VCC VCC Od Od Top View PLCC J28-1 BLOCK DIAGRAM 19 20 21 22 23 24 25 D2d D1e VEES D2e Oe Oe D1d D1c E VEE D2b D1a D2a D1b D2b D1c D2c D1d D2d D1e D2e Oa Oa Ob Ob Oc Oc Od VCC VCCA D1d D2d D1e D2e Oe Oe 1 2 3 4 5 6 24 23 22 21 20 19 18 Top View Flatpack F24-1 17 16 15 14 D1b D2c D2a D1a Oa Oa Ob Ob 13 7 8 9 10 11 12 Od Oc Oc Od Od Oe Oe Pin PIN NAMES Function Data Inputs (n-1...5) Enable Input Data Outputs Complementary Data Outputs VEE Substrate VCCO for ECL Outputs E Dna - Dne E Oa - Oe Oa - Oe VEES VCCA Rev.: G Amendment: /0 1 Issue Date: July, 1999 Micrel SY100S302 TRUTH TABLE(1) D1X L L L L H H H H D2X L L H H L L H H E L H L H L H L H OX L H H H H H H H OX H L L L L L L L NOTE: 1. H = High Voltage Level L = Low Voltage Level DC ELECTRICAL CHARACTERISTICS VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND Symbol IIH IEE Parameter Input HIGH Current, All Inputs Power Supply Current Min. -- -45 Typ. -- -28 Max. 200 -21 Unit A mA Condition VIN = VIH (Max.) Inputs Open AC ELECTRICAL CHARACTERISTICS CERPACK VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND TA = 0C Symbol tPLH tPHL tPLH tPHL tTLH tTHL Parameter Propagation Delay Data to Output Propogation Delay Enable to Output Transition Time 20% to 80%, 80% to 20% Min. 300 250 300 Max. 750 950 900 TA = +25C Min. 300 250 300 Max. 750 950 900 TA = +85C Min. 300 250 300 Max. 750 950 900 Unit ps ps ps Condition PLCC VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND TA = 0C Symbol tPLH tPHL tPLH tPHL tTLH tTHL Parameter Propagation Delay Data to Output Propogation Delay Enable to Output Transition Time 20% to 80%, 80% to 20% Min. 250 250 300 Max. 700 900 900 TA = +25C Min. 250 250 300 Max. 700 900 900 TA = +85C Min. 250 250 300 Max. 700 900 900 Unit ps ps ps Condition 2 Micrel SY100S302 TIMING DIAGRAM 0.7 0.1 ns INPUT 80% 50% 20% -1.69V TRUE tPHL tPLH 0.7 0.1 ns -0.95V 50% OUTPUT tPLH tPHL 80% 50% 20% tTLH tTHL COMPLEMENT Propagation Delay and Transition Times NOTE: VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND PRODUCT ORDERING CODE Ordering Code SY100S302FC SY100S302JC SY100S302JCTR Package Type F24-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial 3 Micrel SY100S302 24 LEAD CERPACK (F24-1) Rev. 03 4 Micrel SY100S302 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 5 |
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