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DATA SHEET
PD16732A, 16732B
384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64-GRAY SCALES)
MOS INTEGRATED CIRCUIT
DESCRIPTION
The PD16732A, 16732B are a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output dynamic range is as large as VSS2 + 0.1 V to VDD2 - 0.1 V, level inversion operation of the LCD's common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a maximum clock frequency of 65 MHz when driving at 3.0 V, 45 MHz when driving at 2.3 V, this driver is applicable to XGA-standard TFT-LCD panels and SXGA TFT-LCD panels by input display signal 2 systems (Clock divide).
FEATURES
* CMOS level input (2.3 V to 3.6 V) * 384 Outputs * Input of 6 bits (gradation data) by 6 dots * Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (R-DAC) * High-speed data transfer: fMAX. = 65 MHz (internal data transfer speed when operating at VDD1 = 3.0 V) * Output dynamic range VSS2 + 0.1 V to VDD2 - 0.1 V * Apply for dot-line inversion, n-line inversion and column line inversion * Output Voltage polarity inversion function (POL) * Display data inversion function (POL2) * Low power control function (LPC) * Logic power supply voltage (VDD1) : 2.3 V to 3.6 V * Driver power supply voltage (VDD2) : 8.5 0.5 V * Different point between PD16732A, 16732B : The ladder resistors value(Refer to 5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE)
ORDERING INFORMATION
Part Number Package TCP (TAB package) TCP (TAB package)
PD16732AN-xxx PD16732BN-xxx
Remark
The TCP's external shape is customized. salesperson.
To order the required shape, please contact an NEC
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S13972EJ3V0DS00 (3rd edition) Date Published August 1999 NS CP(K) Printed in Japan
The mark 5 shows major revised points.
(c)
1999
PD16732A, 16732B
1. BLOCK DIAGRAM
STHR R,/L CLK STB C1 C2 STHL VDD1 VSS1 C63 C64
64-bit bidirectional shift register
D00 - D05 D10 - D15 D20 - D25 D30 - D35 D40 - D45 D50 - D55 POL2
Data register
POL
Latch
VDD2 Level shifter VSS2
V0 - V9
D/A converter
Voltage follower output
S1
S2
S3
S384
Remark /xxx indicates active low signal.
2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S1 S2 S383 S384
V0 V4 V5 V9 Multiplexer
5
6-bit D/A converter 5
POL
2
Data Sheet S13972EJ3V0DS00
PD16732A, 16732B
3. PIN CONFIGURATION ( PD16732AN-xxx, PD16732BN-xxx : TCP (TAB package) )
STHL D55 D54 D53 D52 D51 D50 D45 D44 D43 D42 D41 D40 D35 D34 D33 D32 D31 D30 VDD1 R,/L V9 V8 V7 V6 V5 VDD2 VSS2 Bcont V4 V3 V2 V1 V0 VSS1 LPC CLK STB POL POL2 D25 D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 STHR
S384 S383 S382 S381
Copper Foil Surface
S4 S3 S2 S1
Remark This figure does not specify the TCP package.
Data Sheet S13972EJ3V0DS00
3
PD16732A, 16732B
4. PIN FUNCTIONS
(1/2)
Pin Symbol S1 to S384 D00 to D05 D10 to D15 D20 to D25 D30 to D35 D40 to D45 D50 to D55 R,/L Shift direction control input These refer to the start pulse input/output pins when driver ICs are connected in cascade. The shift directions of the shift registers are as follows. R,/L = H : STHR input, S1 S384, STHL output R,/L = L : STHL input, S384 S1, STHR output STHR Right shift start pulse input/output STHL Left shift start pulse input/output CLK Shift clock input R,/L = H : Becomes the start pulse input pin. R,/L = L : Becomes the start pulse output pin. R,/L = H : Becomes the start pulse output pin. R,/L = L : Becomes the start pulse input pin. Refers to the shift register's shift clock input. The display data is incorporated into the data register at the rising edge. At the rising edge of the 64th clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. STB Latch input The contents of the data register are transferred to the latch circuit at the rising edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure input of one pulse per horizontal period. POL Polarity input POL = L : The S2n-1 output uses V0 to V4 as the reference supply. The S2n output uses V5 to V9 as the reference supply. POL = H: The S2n-1 output uses V5 to V9 as the reference supply. The S2n output uses V0 to V4 as the reference supply. S2n-1 indicates the odd output: and S2n indicates the even output. Input of the POL signal is allowed the setup time (tPOL-STB) with respect to STB's rising edge. POL2 Data inversion POL2 = H : Display data is inverted. POL2 = L : Display data is not inverted LPC Low power control input The current consumption is lowered by controlling the constant current source of the output amplifier. In low power mode (LPC = "L"), the VDD2 of static current consumption can be reduced to two thirds of the normal current consumption. This pin is pulled up to the VDD1 power supply inside the IC. LPC = H or Open : Normal power mode LPC = L : Low power mode Pin Name Driver output Display data input Description The D/A converted 64-gray-scale analog voltage is output. The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). DX0: LSB, DX5: MSB
*
4
Data Sheet S13972EJ3V0DS00
PD16732A, 16732B
(2/2)
Pin Symbol Bcont Pin Name Bias control Description This pin can be used to finely control the bias current inside the output amplifier. In cases when fine-control is necessary, connect this pin to the stabilized ground potential (VSS2) via an external resistor of 10 to 100k (per IC). When this fine-control function is not required, leave this pin open. Refer to 9. CURRENT CONSUMPTION REDUCTION FUNCTION V0 to V9
-corrected power
supplies
Input the -corrected power supplies from outside by using operational amplifier. Make sure to maintain the following relationships. During the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. VDD2 - 0.1 V> V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > V8 > V9 > VSS2 + 0.1 V
VDD1 VDD2 VSS1 VSS2
Logic power supply Driver power supply Logic ground Driver ground
2.3 V to 3.6 V 8.5 V 0.5 V Grounding Grounding
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order. Reverse this sequence to shut down. (Simultaneous power application to VDD2 and V0 to V9 is possible.) 2. To stabilize the supply voltage, please be sure to insert a 0.1 F bypass capacitor between VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of a bypass capacitor of about 0.01 F is also advised between the -corrected power supply terminals (V0, V1, V2, ***, V9) and VSS2.
Data Sheet S13972EJ3V0DS00
5
PD16732A, 16732B
5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
This product incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the LCD's counter electrode (common electrode) voltage. The D/A converter consists of ladder resistors and switches. The ladder resistors (r0 to r62) are designed so that the ratio of LCD panel -compensated voltages to V0' to V63' and V0'' to V63'' is almost equivalent. For the 2 sets of five -compensated power supplies, V0 to V4 and V5 to V9, respectively, input gray scale voltages of the same polarity with respect to the common voltage. When fine-gray scale voltage precision is not necessary, there is no need to connect a voltage follower circuit to the -compensated power supplies V1 to V3 and V6 to V8. Figure 5-1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and VSS2, common electrode potential VCOM, and -corrected voltages V0 to V9 and the input data. Be sure to maintain the voltage relationships of VDD2 - 0.1 V> V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > V8 > V9 > VSS2 + 0.1 V. Figures 5-2 and 5-3 show the relationship between the input data and the output data. This driver IC is designed for only single-sided mounting. Therefore, please do not use it for -corrected power supply level inversion in double-sided mounting. Figure 5-1. Relationship between Input Data and - corrected Power Supply -
PD16732A
0.1 V VDD2 V0
16
PD16732B
0.1 V VDD2 V0
16
V1 V2 V3 V4 VCOM V5 V6 V7 V8
16 16 15 Split interval 15 16 16 16
V1 V2 V3 V4 VCOM V5
16 16 15
Split interval
15
V6 V7 V8 V9 0.1 V VSS2
16 16 16
V9 0.1 V VSS2 00 10 20 30 Input data (HEX) 3F
00
10
20 30 Input data (HEX)
3F
6
Data Sheet S13972EJ3V0DS00
PD16732A, 16732B
Figure 5-2. Relationship between Input Data and Output Voltage (1/2) - VDD2 - 0.1 V> V0 > V1 > V2 > V3 > V4 > V5, POL2 = L
V0 r0 V1' r1 V2' r2 V3' r3
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 V0' V1' V2' V3' V4' V5' V6' V7' V8' V9' V10' V11' V12' V13' V14' V15' V16' V17' V18' V19' V20' V21' V22' V23' V24' V25' V26' V27' V28' V29' V30' V31' V32' V33' V34' V35' V36' V37' V38' V39' V40' V41' V42' V43' V44' V45' V46' V47' V48' V49' V50' V51' V52' V53' V54' V55' V56' V57' V58' V59' V60' V61' V62' V63'
V0'
Data DX5 DX4 DX3 DX2 DX1 DX0
Output Voltage 732A V0 V1+(V0-V1)x V1+(V0-V1)x V1+(V0-V1)x V1+(V0-V1)x V1+(V0-V1)x V1+(V0-V1)x V1+(V0-V1)x V1+(V0-V1)x V1+(V0-V1)x V1+(V0-V1)x V1+(V0-V1)x V1+(V0-V1)x V1+(V0-V1)x V1+(V0-V1)x V1+(V0-V1)x V1 V2+(V1-V2)x V2+(V1-V2)x V2+(V1-V2)x V2+(V1-V2)x V2+(V1-V2)x V2+(V1-V2)x V2+(V1-V2)x V2+(V1-V2)x V2+(V1-V2)x V2+(V1-V2)x V2+(V1-V2)x V2+(V1-V2)x V2+(V1-V2)x V2+(V1-V2)x V2+(V1-V2)x V2 V3+(V2-V3)x V3+(V2-V3)x V3+(V2-V3)x V3+(V2-V3)x V3+(V2-V3)x V3+(V2-V3)x V3+(V2-V3)x V3+(V2-V3)x V3+(V2-V3)x V3+(V2-V3)x V3+(V2-V3)x V3+(V2-V3)x V3+(V2-V3)x V3+(V2-V3)x V3+(V2-V3)x V3 V4+(V3-V4)x V4+(V3-V4)x V4+(V3-V4)x V4+(V3-V4)x V4+(V3-V4)x V4+(V3-V4)x V4+(V3-V4)x V4+(V3-V4)x V4+(V3-V4)x V4+(V3-V4)x V4+(V3-V4)x V4+(V3-V4)x V4+(V3-V4)x V4+(V3-V4)x V4 7250/8050 6500/8050 5800/8050 5150/8050 4550/8050 4000/8050 3450/8050 2950/8050 2450/8050 2050/8050 1650/8050 1300/8050 950/8050 600/8050 300/8050 2450/2750 2200/2750 1950/2750 1700/2750 1500/2750 1300/2750 1100/2750 950/2750 800/2750 650/2750 500/2750 400/2750 300/2750 200/2750 100/2750 1500/1600 1400/1600 1300/1600 1200/1600 1100/1600 1000/1600 900/1600 800/1600 700/1600 600/1600 500/1600 400/1600 300/1600 200/1600 100/1600 3350/3450 3250/3450 3150/3450 3050/3450 2950/3450 2800/3450 2650/3450 2500/3450 2300/3450 2100/3450 1850/3450 1600/3450 1300/3450 800/3450
rn 732B 4585/6351 3849/6351 3283/6351 2774/6351 2378/6351 2038/6351 1755/6351 1472/6351 1246/6351 1020/6351 850/6351 680/6351 510/6351 340/6351 170/6351 2280/2432 2128/2432 1976/2432 1824/2432 1672/2432 1520/2432 1368/2432 1216/2432 1064/2432 912/2432 760/2432 608/2432 456/2432 304/2432 152/2432 2340/2496 2184/2496 2028/2496 1872/2496 1716/2496 1560/2496 1404/2496 1248/2496 1092/2496 936/2496 780/2496 624/2496 468/2496 312/2496 156/2496 4397/4572 4222/4572 4047/4572 3872/4572 3697/4572 3465/4572 3233/4572 3001/4572 2769/4572 2480/4572 2135/4572 1733/4572 1331/4572 872/4572 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r47 r48 r49 r50 r51 r52 r53 r54 r55 r56 r57 r58 r59 r60 r61 r62
() 732A 732B 800 750 700 650 600 550 550 500 500 400 400 350 350 350 300 300 300 250 250 250 200 200 200 150 150 150 150 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 150 150 150 200 200 250 250 300 500 800 1766 736 566 509 396 340 283 283 226 226 170 170 170 170 170 170 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 156 156 156 156 156 156 156 156 156 156 156 156 156 156 156 156 175 175 175 175 175 232 232 232 232 289 345 402 402 459 872
r14 V15' r15 V1 r16 V17' r17 V16'
r46 r47 V3 r48 V49' r49 V47' V48'
r60 r61 r62 V4 V63' V61' V62'
rtotal 15850 15851
Caution There is no connection between V4 and V5 terminal in the chip.
Data Sheet S13972EJ3V0DS00
7
PD16732A, 16732B
Figure 5-3. Relationship between Input Data and Output Voltage (2/2) - V4 > V5 > V6 > V7 > V8 > V9 > VSS2 + 0.1 V, POL2 = L
V5 V63'' r62 V62'' r61 V61'' r60 V60'' r59
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 V0'' V1'' V2'' V3'' V4'' V5'' V6'' V7'' V8'' V9'' V10'' V11'' V12'' V13'' V14'' V15'' V16'' V17'' V18'' V19'' V20'' V21'' V22'' V23'' V24'' V25'' V26'' V27'' V28'' V29'' V30'' V31'' V32'' V33'' V34'' V35'' V36'' V37'' V38'' V39'' V40'' V41'' V42'' V43'' V44'' V45'' V46'' V47'' V48'' V49'' V50'' V51'' V52'' V53'' V54'' V55'' V56'' V57'' V58'' V59'' V60'' V61'' V62'' V63'' Data DX5 DX4 DX3 DX2 DX1 DX0 Output Voltage 732A V9 V9+(V8-V9)x V9+(V8-V9)x V9+(V8-V9)x V9+(V8-V9)x V9+(V8-V9)x V9+(V8-V9)x V9+(V8-V9)x V9+(V8-V9)x V9+(V8-V9)x V9+(V8-V9)x V9+(V8-V9)x V9+(V8-V9)x V9+(V8-V9)x V9+(V8-V9)x V9+(V8-V9)x V8 V8+(V7-V8)x V8+(V7-V8)x V8+(V7-V8)x V8+(V7-V8)x V8+(V7-V8)x V8+(V7-V8)x V8+(V7-V8)x V8+(V7-V8)x V8+(V7-V8)x V8+(V7-V8)x V8+(V7-V8)x V8+(V7-V8)x V8+(V7-V8)x V8+(V7-V8)x V8+(V7-V8)x V7 V7+(V6-V7)x V7+(V6-V7)x V7+(V6-V7)x V7+(V6-V7)x V7+(V6-V7)x V7+(V6-V7)x V7+(V6-V7)x V7+(V6-V7)x V7+(V6-V7)x V7+(V6-V7)x V7+(V6-V7)x V7+(V6-V7)x V7+(V6-V7)x V7+(V6-V7)x V7+(V6-V7)x V6 V6+(V5-V6)x V6+(V5-V6)x V6+(V5-V6)x V6+(V5-V6)x V6+(V5-V6)x V6+(V5-V6)x V6+(V5-V6)x V6+(V5-V6)x V6+(V5-V6)x V6+(V5-V6)x V6+(V5-V6)x V6+(V5-V6)x V6+(V5-V6)x V6+(V5-V6)x V5 800/8050 1550/8050 2250/8050 2900/8050 3500/8050 4050/8050 4600/8050 5100/8050 5600/8050 6000/8050 6400/8050 6750/8050 7100/8050 7450/8050 7750/8050 300/2750 550/2750 800/2750 1050/2750 1250/2750 1450/2750 1650/2750 1800/2750 1950/2750 2100/2750 2250/2750 2350/2750 2450/2750 2550/2750 2650/2750 100/1600 200/1600 300/1600 400/1600 500/1600 600/1600 700/1600 800/1600 900/1600 1000/1600 1100/1600 1200/1600 1300/1600 1400/1600 1500/1600 100/3450 200/3450 300/3450 400/3450 500/3450 650/3450 800/3450 950/3450 1150/3450 1350/3450 1600/3450 1850/3450 2150/3450 2650/3450 rn 732B 1766/6351 2502/6351 3068/6351 3577/6351 3973/6351 4313/6351 4596/6351 4879/6351 5105/6351 5331/6351 5501/6351 5671/6351 5841/6351 6011/6351 6181/6351 152/2432 304/2432 456/2432 608/2432 760/2432 912/2432 1064/2432 1216/2432 1368/2432 1520/2432 1672/2432 1824/2432 1976/2432 2128/2432 2280/2432 156/2496 312/2496 468/2496 624/2496 780/2496 936/2496 1092/2496 1248/2496 1404/2496 1560/2496 1716/2496 1872/2496 2028/2496 2184/2496 2340/2496 175/4572 350/4572 525/4572 700/4572 875/4572 1107/4572 1339/4572 1571/4572 1803/4572 2092/4572 2437/4572 2839/4572 3241/4572 3700/4572 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r47 r48 r49 r50 r51 r52 r53 r54 r55 r56 r57 r58 r59 r60 r61 r62 () 732A 732B 800 750 700 650 600 550 550 500 500 400 400 350 350 350 300 300 300 250 250 250 200 200 200 150 150 150 150 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 150 150 150 200 200 250 250 300 500 800 1766 736 566 509 396 340 283 283 226 226 170 170 170 170 170 170 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 152 156 156 156 156 156 156 156 156 156 156 156 156 156 156 156 156 175 175 175 175 175 232 232 232 232 289 345 402 402 459 872
r49 V49'' r48 V6 r47 V47'' r46 V48''
r17 V17'' r16 V8 r15 V15'' r14 V16''
r2 V2'' r1 V1'' r0 V9 V0''
rtotal 15850 15851
Caution There is no connection between V4 and V5 terminal in the chip.
8
Data Sheet S13972EJ3V0DS00
PD16732A, 16732B
6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN
Data format: 6 bits x 2 RGBs (6 dots) Input width : 36 bits (2-pixel data) R,/L = H (Right shift)
Output Data S1 D00 to D05 S2 D10 to D15 S3 D20 to D25 S4 D30 to D35 xxx xxx S383 D40 to D45 S384 D50 to D55
R,/L = L (Left shift)
Output Data S1 D00 to D05 S2 D10 to D15 S3 D20 to D25 S4 D30 to D35 xxx xxx S383 D40 to D45 S384 D50 to D55
POL L H
S2n-1
Note
S2n
Note
V0 to V4 V5 to V9
V5 to V9 V0 to V4
Note S2n-1 (Odd output), S2n (Even output) 5
7. RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM
The output voltage is written to the LCD panel synchronized with the STB falling edge.
STB
POL
S2n-1
Selected voltage V0 to V4
Selected voltage V5 to V9
Selected voltage V0 to V4
S2n
Selected voltage V5 to V9
Selected voltage V0 to V4
Selected voltage V5 to V9
Hi-Z
Hi-Z
Hi-Z
Data Sheet S13972EJ3V0DS00
9
PD16732A, 16732B
8. RELATIONSHIP BETWEEN STB, CLK, AND OUTPUT WAVEFORM
The output voltage is written to the LCD panel synchronized with the STB falling edge. Figure 8-1. Output Circuit Block Diagram -
Output Amp
DAC
+
VAMP(IN) SW1 VOUT
Figure 8-2. Output Circuit Timing Waveform -
[1]
CLK (External Input) STB (External Input) SW1 : ON
[2]
SW1 : OFF
SW1 : ON
VAMP(IN)
VOUT (External Output) Output Hi-Z Output
Remarks 1. STB = L : SW1 = ON STB = H : SW1 = OFF 2. STB = "H" is acknowledged at timing [1]. 3. The display data latch is completed at timing [2] and the input voltage (Vamp (in) : gray-scale level voltage) of the output amplifier changes.
10
Data Sheet S13972EJ3V0DS00
PD16732A, 16732B
9. CURRENT CONSUMPTION REDUCTION FUNCTION
The PD16732A and 16732B have a low power control function (LPC) which can switch the bias current of the output amplifier between two levels and a bias control function (Bcont) which can be used to finely control the bias current. The bias current of the output amplifier can be switched between two levels using this pin. (Bcont: Open) LPC = H or Open: Normal power mode LPC = L: Low power mode 5 The VDD2 of static current consumption can be reduced to two thirds of that in normal mode. Input a stable DC current (VDD1/VSS1) to this pin. It is possible to fine-control the current consumption by using the bias current control function (Bcont pin). When using this function, connect this pin to the stabilized ground potential (VSS2) via an external resistor (REXT). When not using this function, leave this pin open. Refer to the table below for the percentage of current regulation when using the bias current control function. Figure9-1. Bias Current Control Function (Bcont) -
PD16732A,16732B
Bcont LPC
REXT
H/L
VSS2
Refer to the table below for the percentage of current regulation when using the bias current control function. 5 Talbe9-1. Current Consumption Regulation Percentage Compared to Normal Mode -
REXT (Open) 50 k 20 k 10 k Current Consumption Regulation Percentage LPC = H 100 % 110 % 115 % 120 % LPC = L 65 % 70 % 80 % 85 %
VDD1 = 3.3 V VDD2 = 8.7 V LPC = 3.3 V/0 V
Remark The above current consumption regulation percentages are not product-characteristic guaranteed as they are based on the results of simulation. Caution Because the low-power and bias-current control functions control the bias current in the output amplifier and regulate the over-all current consumption of the driver IC, when this occurs, the characteristics of the output amplifier will simultaneously change. Therefore, when using these functions, be sure to sufficiently evaluate the picture quality.
Data Sheet S13972EJ3V0DS00
11
PD16732A, 16732B
Figure9-2. Output wave form (LPC = L) -
Bcont = Open
Bcont = 1.0 k
Output Voltage(1 V/div)
Time (4 s / div) Bcont = 10 k Bcont = 50 k
[1] [2]
[1]
[2]
RL VIN
+
RL
RL
RL
RL RL = 1 k CL = 15 pF CL CL
CL
CL
CL
12
Data Sheet S13972EJ3V0DS00
PD16732A, 16732B
Figure9-3. Output wave form (LPC = H) -
Bcont = Open
Bcont = 1.0 k
Output Voltage(1 V/div)
Time (4 s / div)
Bcont = 10 k
Bcont = 50 k
Data Sheet S13972EJ3V0DS00
13
PD16732A, 16732B
10. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25 C, VSS1 = VSS2 = 0 V)
Parameter Logic Part Supply Voltage Driver Part Supply Voltage Logic Part Input Voltage Driver Part Input Voltage Logic Part Output Voltage Driver Part Output Voltage Operating Ambient Temperature Storage Temperature Symbol VDD1 VDD2 VI1 VI2 VO1 VO2 TA Tstg Rating -0.5 to +4.0 -0.5 to +10.0 -0.5 to VDD1 + 0.5 -0.5 to VDD2 + 0.5 -0.5 to VDD1 + 0.5 -0.5 to VDD2 + 0.5 -10 to +75 -55 to +125 Unit V V V V V V C C
Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings. Recommended Operating Range (TA = -10 to +75 C, VSS1 = VSS2 = 0 V)
Parameter Logic Part Supply Voltage Driver Part Supply Voltage High-Level Input Voltage Low-Level Input Voltage Symbol VDD1 VDD2 VIH VIL V0 to V9 VO fMAX. VDD1 = 2.3 V to 3.6 V VDD1 = 3.0 V to 3.6 V Conditions MIN. 2.3 8.0 0.7 VDD1 0 VSS2 + 0.1 VSS2 + 0.1 45 65 8.5 TYP. MAX. 3.6 9.0 VDD1 0.3 VDD1 VDD2 - 0.1 VDD2 - 0.1 Unit V V V V V V MHz MHz
-Corrected Voltage
Driver Part Output Voltage Maximum Clock Frequency
14
Data Sheet S13972EJ3V0DS00
PD16732A, 16732B
Electrical Characteristics (TA = -10 to +75 C, VDD1 = 2.3 V to 3.6 V, VDD2 = 8.5 V 0.5 V, VSS1 = VSS2 = 0 V, Unless otherwise specified, the input level is defined to be LPC = H or Open, Bcont = Open)
Parameter Input Leak Current High-Level Output Voltage Low-Level Output Voltage Symbol IIL VOH VOL I STHR (STHL), IOH = 0 mA STHR (STHL), IOL = 0 mA V0 to V4 = V5 to V9 = 4.0 V Driver Output Current IVOH IVOL Output Voltage Deviation Output swing difference deviation Output Voltage Range Logic Part Dynamic Current Consumption Driver Part Dynamic Current Consumption VO VP-P V0 pin, V5 pin V4 pin, V9 pin
Note Note
Condition
MIN.
TYP.
MAX. 1.0
Unit
A
V
VDD1 - 0.1 0.1 126 -504 252 -252 504 -126 -30 30 7 2 20 15
V
-Corrected Supply Current
A A A A
mV mV
VX = 7.0 V, VOUT = 6.5 V VX = 1.0 V, VOUT = 1.5 V
VDD1 = 3.3 V, VDD2 = 8.5 V, VOUT = 2.0 V, 4.25 V, 6.5 V
VO IDD1
All Input data VDD1, with no load
0.1 3.0
VDD2 - 0.1 6.0
V mA
IDD21
VDD2 = 8.5 V 0.5 V, with no load LPC = H, Bcont = Open
3.0
6.0
mA
IDD22
VDD2 = 8.5 V 0.5 V, with no load LPC = L, Bcont = Open
2.0
4.0
mA
Notes1. VX refers to the output voltage of analog output pins S1 to S384. 2. VOUT refers to the voltage applied to analog output pins S1 to S384. Cautions 1. The STB cycle is defined to be 20 s at fCLK = 40 MHz. 2. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern. 3. Refers to the current consumption per driver when cascades are connected under the assumption of XGA single-sided mounting (8 units).
Data Sheet S13972EJ3V0DS00
15
PD16732A, 16732B
Switching Characteristics (TA = -10 to +75 C, VDD1 = 2.3 V to 3.6 V, VDD2 = 8.5 V 0.5 V, VSS1 = VSS2 = 0 V, Unless otherwise specified, the input level is defined to be LPC = H or Open, Bcont = Open)
Parameter Start Pulse Delay Time Symbol tPLH1 Condition CL = 10 pF, VDD1 = 2.3 V to 3.6 V CL = 10 pF, VDD1 = 3.0 V to 3.6 V Driver Output Delay Time tPLH2 tPLH3 tPHL2 tPHL3 Input Capacitance CI1 STHR (STHL) excluded, TA = +25C STHR (STHL),TA = +25C CL = 75 pF, RL = 5 k 2.5 5 2.5 5 5 5 8 5 8 10 7 10.5 ns MIN. TYP. 10 MAX. 17 Unit ns
s s s s
pF
CI2
8
10
pF

RL Output CL= 15 pF CL CL CL CL CL RL RL RL RL RL= 1 k
16
Data Sheet S13972EJ3V0DS00
PD16732A, 16732B
Timing Requirement (TA = -10 to +75 C, VDD1 = 2.3 V to 3.6 V, VSS1 = VSS2 = 0 V, tr = tf = 8.0 ns)
Parameter Clock Pulse Width Symbol PWCLK Condition VDD1 = 2.3 V to 3.6 V VDD1 = 3.0 V to 3.6 V Clock Pulse High Period Clock Pulse Low Period PWCLK(H) PWCLK(L) VDD1 = 2.3 V to 3.6 V VDD1 = 3.0 V to 3.6 V Data Setup Time Data Hold Time Start Pulse Setup Time Start Pulse Hold Time POL2 Setup Time POL2 Hold Time Start Pulse Low Period STB Pulse Width tSETUP1 tHOLD1 tSETUP2 tHOLD2 tSETUP3 tHOLD3 tSPL PWSTB MIN. 22 15 4 6 4 4 0 4 0 4 0 6 2 4 Data Invalid Period Last Data Timing CLK-STB Time STB-CLK Time tINV tLDT tCLK-STB tSTB-CLK CLK STB STB CLK VDD1 = 2.3 V to 3.6 V STB CLK VDD1 = 3.0 V to 3.6 V Time Between STB and Start Pulse POL-STB Time tSTB-STH tPOL-STB tSTB-POL STB STHR(STHL) POL or STB STB POL or 2 -5 6 CLK ns ns 6 ns 1 2 6 9 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns CLK
s
CLK CLK ns ns
*
STB-POL Time
Data Sheet S13972EJ3V0DS00
17
* 11. SWITCHING CHARACTERISTICS WAVEFORM
18
Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
PWCLK(L) PWCLK CLK tSETUP2 STHR (1st Dr.) tSETUP1 Dn0 to Dn5 INVALID D1 to D6 tHOLD1 D373 to D378 D379 to D384 D385 to D390 D3067 to D3072 tSTB-STH VDD1 INVALID D1-D6 D7-D12 VSS1 1 tHOLD2 2 PWCLK(H) 3 64 65 66 513 514 tCLK-STB tSTB-CLK tSPL VDD1 VSS1 1 2 90% 10% tr tf VDD1 VSS1 D7 to D12 tHOLD3 VDD1 POL2 INVALID tPLH1 STHL (1st Dr.) tINV tLDT STB VSS1 tPOL-STB POL VSS1 tPLH3 Hi-Z tPLH2 tSTB-POL VDD1 PWSTB VDD1 VDD1 VSS1 INVALID VSS1
Data Sheet S13972EJ3V0DS00
tSETUP3
PD16732A, 16732B
VOUT
Target Voltage +0.1 VDD2 6-bit accuracy
tPHL2 tPHL3
PD16732A, 16732B
12. RECOMMENDED SOLDERING CONDITIONS
The following conditions must be met for soldering conditions of the PD16732A, 16732B. For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions.
PD16732AN-xxx, PD16732BN-xxx : TCP (TAB package) xxx
Mounting Condition Thermocompression Mounting Method Soldering Condition Heating tool 300 to 350C: heating for 2 to 3 seconds: pressure 100g (per solder) Temporary bonding 70 to 100C: pressure 3 to 8 kg/cm : time 3 to 5 seconds. 2 Real bonding 165 to 180C: pressure 25 to 45 kg/cm : time 30 to 40 seconds. (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite, Ltd.)
2
ACF (Adhesive Conductive Film)
Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more packaging methods at a time.
Data Sheet S13972EJ3V0DS00
19
PD16732A, 16732B
[MEMO]
20
Data Sheet S13972EJ3V0DS00
PD16732A, 16732B
[MEMO]
Data Sheet S13972EJ3V0DS00
21
PD16732A, 16732B
[MEMO]
22
Data Sheet S13972EJ3V0DS00
PD16732A, 16732B
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S13972EJ3V0DS00
23
PD16732A, 16732B
Reference Documents NEC Semiconductor Device Reliability / Quality Control System (C10983E) Quality Grades to NEC's Semiconductor Devices (C11531E)
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98. 8

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