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19-2014; Rev 2; 7/01
ILABLE N KIT AVA VALUATIO E
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer
General Description
The MAX2306/MAX2308/MAX2309 are IF receivers designed for dual-band, dual-mode, and single-mode N-CDMA and W-CDMA cellular phone systems. The signal path consists of a variable-gain amplifier (VGA) and I/Q demodulator. The devices feature guaranteed +2.7V operation, a gain control range of over 110dB, and high input IP3 (-31dBm at 35dB gain, 3.4dBm at -35dB gain). Unlike similar devices, the MAX2306 family of receivers includes dual oscillators and synthesizers to form a self-contained IF subsystem. The synthesizer's reference and RF dividers are fully programmable through a 3-wire serial bus, enabling dual-band system architectures using any common reference and IF frequency. The differential baseband outputs have enough bandwidth to suit both N-CDMA and W-CDMA systems, and offer saturated output levels of 2.7Vp-p at a low +2.75V supply voltage. Including the low-noise voltage-controlled oscillator (VCO) and synthesizer, the MAX2306 draws only 26mA from a +2.75V supply in CDMA (differential IF) mode. The MAX2306/MAX2308/MAX2309 are available in 28pin QFN packages.
Features
o Complete IF Subsystem Includes VCO and Synthesizer o Supports Dual-Band, Triple-Mode Operation o VGA with >110dB Gain Control o Quadrature Demodulator o High Output Level (2.7V) o Programmable Charge-Pump Current o Supports Any IF Frequency Between 40MHz and 300MHz o 3-Wire Programmable Interface o Low Supply Voltage (+2.7V)
MAX2306/MAX2308/MAX2309
Ordering Information
PART MAX2306EGI MAX2308EGI MAX2309EGI TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 28 QFN-EP* 28 QFN-EP* 28 QFN-EP*
Applications
Single/Dual/Triple-Mode CDMA Handsets Globalstar Dual-Mode Handsets Wireless Data Links W-CDMA Handsets Wireless Local Loop (WLL)
*Exposed paddle Pin Configurations appear at end of data sheet. Block Diagram appears at end of data sheet.
Selector Guide
PART MODE AMPS, Cellular CDMA, PCS CDMA AMPS, Cellular CDMA, PCS CDMA External AMPS, Cellular CDMA, PCS CDMA DESCRIPTION Dual Band, Triple Mode with Two IF VCOs INPUT RANGE
MAX2306
40MHz to 300MHz
MAX2308
Dual Band, Triple Mode with Common IF VCO
70MHz to 300MHz
MAX2309
Dual Band, Triple Mode (Drives External AMPS Discriminator)
70MHz to 300MHz
________________________________________________________________ Maxim Integrated Products
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2306/MAX2308/MAX2309
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +6.0V SHDN to GND.............................................-0.3V to (VCC + 0.3V) STBY, BUFEN, MODE, EN, DATA, CLK, DIVSEL ...........................................-0.3V to (VCC + 0.3V) VGC to GND...............-0.3V, the lesser of +4.2V or (VCC + 0.3V) AC Signals TANKH , TANKL , REF, FM , CDMA .................................................1.0V peak Digital Input Current SHDN, MODE, DIVSEL, BUFEN, DATA, CLK, EN, STBY .....................................10mA Continuous Power Dissipation (TA = +70C) 28-Pin QFN (derate 28.5mW/C above TA = +70C)...........2W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +3.6V, MODE = DIVSEL = SHDN = STBY = BUFEN = high, differential output load = 10k, TA = -40C to +85C, registers set to default power-up settings. Typical values are at VCC = +2.75V and TA = +25C, unless otherwise noted.)
PARAMETER SYMBOL CDMA mode FM_IQ mode Supply Current (Note 1) FM_I mode STANDBY (VCO_H) STANDBY (VCO_L) CONDITIONS TA = +25C TA = -40C to +85C TA = +25C TA = -40C to +85C TA = +25C TA = -40C to +85C TA = +25C TA = -40C to +85C TA = +25C TA = -40C to +85C 3.5 1.5 4 2.0 0.5 IIH IIL 0.5V < VVGC < 2.3V SHDN = low 47k load 47k load I+ to I- and Q+ to Q-, PLL locked VCC = +2.75V -20 1.5 VCC - 1.4 2.0 0.5 +20 -5 2 2 5 1 10 5.8 A mA V V A A A A V V mV V 11.4 12.3 24.7 25.4 MIN TYP 25.9 MAX 37.5 41.5 36.7 40.6 35.7 39.5 18.8 20.7 18.4 20.3 mA UNITS
ICC
Addition for LO out (BUFEN = low) Shutdown Current Register Shutdown Current Logic High Logic Low Logic High Input Current Logic Low Input Current VGC Control Input Current VGC Control Input Current During Shutdown Lock Indicator High (locked) Lock Indicator Low (unlocked) DC Offset Voltage Common-Mode Output Voltage ICC ICC SHDN = low
2
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer
AC ELECTRICAL CHARACTERISTICS
(MAX2306/MAX2308/MAX2309 EV kit, VCC = +2.75V, registers set to default power-up states except M1 = M2 = 306, R1 = R2 = 16, fIN = 183.7MHz, fREF = 19.2MHz, 0.6Vp-p synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN = high, VGC set for +35dB voltage gain, differential output load = 10k, all power levels referred to 50, TA = +25C, unless otherwise noted.)
PARAMETER Input Frequency Reference Frequency Frequency Reference Signal Level SIGNAL PATH, CDMA MODE Gain = -35dB, (Note 3) Input 3rd-Order Intercept IIP3 Gain = +35dB, TA = -40C to +85C (Notes 4, 5) Gain = -35dB Gain = +35dB (Note 6) AV AV NF Gain = -35dB Gain = +35dB 57 -38 -9 -44 -14.8 -49 -56 61 62.9 6.36 -6.5 -40.2 -20 -44 -56.7 56 59.5 2.5 4.2 TA = -40C to +85C (Note 5) VSAT FVCO_L FVCO_H PLO M1, M2 M1, M2 R1, R2 16383 2 Differential (Note 2) (Note 2) RL = 50, BUFEN = low 80 135 -13.7 256 28 40 1 2.7 300 600 -52 -32 dBm -51 3.4 -31.0 dBm SYMBOL fIN fREF VREF 0.2 (Note 2) CONDITIONS MIN 40 TYP MAX 300 39 UNITS MHz MHz Vp-p
MAX2306/MAX2308/MAX2309
Input 1dB Compression Input 0.25dB Desensitization Minimum Voltage Gain Maximum Voltage Gain DSB Noise Figure SIGNAL PATH, FM_IQ MODE
P1dB
dBm dBm dB dB dBm
VVGC = 0.5V (Note 5) VVGC = 2.3V (Note 5) Gain = -35dB Gain = +35dB Gain = -35dB, (Note 7)
Input 3rd-Order Intercept
IIP3
Gain = +35dB, TA = -40C to +85C (Notes 5, 8) Gain = -35dB Gain = +35dB VVGC = 0.5V (Note 5) VVGC = 2.3V (Note 5) Normalized to +25C
Input 1dB Compression Minimum Voltage Gain Maximum Voltage Gain Gain Variation Over Temperature Baseband 0.5dB Bandwidth Quadrature Suppression LO to Baseband Leakage Saturated Output Level PHASE-LOCKED LOOP VCO Tune Range LO_OUT Output Power VCO Minimum Divide Ratio VCO Maximum Divide Ratio REF Minimum Divide Ratio
P1dB AV AV
dBm dB dB dB MHz dB mVp-p Vp-p
SIGNAL PATH, CDMA AND FM_IQ MODE
MHz dBm
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2306/MAX2308/MAX2309
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2306/MAX2308/MAX2309 EV kit, VCC = +2.75V, registers set to default power-up states except M1 = M2 = 306, R1 = R2 = 16, fIN = 183.7MHz, fREF = 19.2MHz, 0.6Vp-p synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN = high, VGC set for +35dB voltage gain, differential output load = 10k, all power levels referred to 50, TA = +25C, unless otherwise noted.)
PARAMETER REF Maximum Divide Ratio Minimum Phase Detector Comparison Frequency Maximum Phase Detector Comparison Frequency SYMBOL R1, R2 (Note 5) (Note 5) 1kHz offset, TA = -40C to +85C 12.5kHz offset, TA = -40C to +85C Phase Noise 30kHz offset, TA = -40C to +85C 120kHz offset, TA = -40C to +85C 900kHz offset, TA = -40C to +85C TURBO LOCK Acquisition, CPX = XX, TC =1 Locked, CPX = 00 Charge-Pump Source/Sink Current Locked, CPX = 01 Locked, CPX = 10 Locked, CPX = 11 Charge-Pump Source/Sink Matching Locked, all values of CPX, 0.5V < VCP < VCC - 0.5V 1480 105 150 210 300 2100 150 210 300 425 0.2 2650 190 265 380 530 10 % A 1500 -79.6 -94.6 -105 -115.3 -125 dBc/Hz CONDITIONS MIN 2047 20 kHz kHz TYP MAX UNITS
FM_IQ and FM_I modes are not available on MAX2309. Recommended operating frequency range. Contact factory for operating frequency outside this range. f1 = 183.7MHz, f2 = 183.71MHz, Pf1 = Pf2 = -15dBm. f1 = 183.7MHz, f2 = 183.71MHz, Pf1 = Pf2 = -50dBm. Guaranteed by design. Small-signal gain at 200kHz below the LO frequency will be reduced by less than 0.25dB when an interfering signal at 1.25MHz below the LO frequency is applied at the specified level. Note 7: f1 = 183.7MHz, f2 = 183.71MHz, Pf1 = Pf2 = -23dBm. Note 8: f1 = 183.7MHz, f2 = 183.71MHz, Pf1 = Pf2 = -55dBm. Note 1: Note 2: Note 3: Note 4: Note 5: Note 6:
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer
Typical Operating Characteristics
(MAX2306/MAX2308/MAX2309 EV kits, VCC = +2.75V, registers set to default power-up states, fIN = 183.7MHz, fREF = 19.2MHz, synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN = high, VGC set for +35dB voltage gain, differential output load = 10k, all power levels referred to 50, TA = +25C, unless otherwise noted.)
RECEIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX2306/8/9 toc01
MAX2306/MAX2308/MAX2309
RECEIVE SHUTDOWN CURRENT vs. SUPPLY VOLTAGE
MAX2306/8/9 toc02
GAIN vs. VGC
60 40 GAIN (dB) 20 0 -20 TA = +25C TA = -40C TA = +85C
MAX2306/8/9 toc03
35.00 32.50 SUPPLY CURRENT (mA) TA = +85C 30.00 27.50 25.00 22.50 20.00 2.5 3.0 3.5 4.0 4.5 5.0 TA = +25C
0.014 0.012 SHUTDOWN CURRENT (mA) 0.010 0.008 TA = +25C 0.006 0.004 0.002 0 TA = -40C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TA = +85C
80
TA = -40C
-40 -60 -80 5.5 0.5 1.0
5.5
1.5
2.0
2.5
3.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
VGC (V)
GAIN vs. INPUT FREQUENCY
MAX2306/8/9 toc04
GAIN vs. BASEBAND FREQUENCY
MAX2306/8/9 toc05
THIRD-ORDER INPUT INTERCEPT vs. GAIN
TA = -40C
MAX2306/8/9 toc06
60 55 50 45 GAIN (dB) 40 35 30 25 20 15 0 100 200 300 400 VGC = 2.5V
60.0 59.5 RELATIVE GAIN (dB) 59.0 58.5 58.0 57.5 57.0 56.5 56.0
10 0 -10 IIP3 (dBm)
TA = +85C -20 -30 -40 -50 -60 TA = +25C
500
0
2
4
6
8
10 12 14 16 18 20
-60
-40
-20
0
20
40
60
80
FREQUENCY (MHz)
FREQUENCY (MHz)
GAIN (dB)
NOISE FIGURE vs. GAIN
MAX2306/8/9 toc07
NOISE FIGURE vs. TEMPERATURE
GAIN = 50dB
MAX2306/8/9 toc08
VCO VOLTAGE vs. TIME
MAX2306/8/9 toc09
70 60 50 NF (dB) 40 30 20 10
7.4 7.2 7.0 NF (dB) 6.8 6.6 6.4 6.2 6.0
SHDN VCO VOLTAGE
1V/div LOCK
LOCK TIME 1.83ms
0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 GAIN (dB)
-40
-20
0
20
40
60
80
100
500s/div
TEMPERATURE (C)
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2306/MAX2308/MAX2309
Typical Operating Characteristics (continued)
(MAX2306/MAX2308/MAX2309 EV kits, VCC = +2.75V, registers set to default power-up states, fIN = 183.7MHz, fREF = 19.2MHz, synthesizer locked with passive 3rd-order lead-lag loop filter, SHDN = high, VGC set for +35dB voltage gain, differential output load = 10k, all power levels referred to 50, TA = +25C, unless otherwise noted.)
IF PORT PARALLEL RESISTANCE vs. FREQUENCY
MAX2306/8/9 toc10
IF PORT PARALLEL CAPACITANCE vs. FREQUENCY
EQUIVALENT PARELLEL CAPACITANCE (pF) MEASURED DIFFERENTIALLY 1.1 1.0 0.9 FM PORT 0.8 0.7 0.6 0.5 CDMA PORT
MAX2306/8/9 toc11
2500 EQUIVALENT PARELLEL RESISTANCE () 2300 2100 1900 1700 1500 1300 1100 900 700 500 0 100 200 300 400 500 FM PORT MEASURED DIFFERENTIALLY CDMA PORT
1.2
600
0
100
200
300
400
500
600
FREQUENCY (MHz)
FREQUENCY (MHz)
TANK PORT PARALLEL RESISTANCE vs. FREQUENCY
MAX2306/8/9 toc12
TANK PORT PARALLEL CAPACITANCE vs. FREQUENCY
1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 80 EQUIVALENT PARELLEL CAPACITANCE () TANK
MAX2306/8/9 toc13
-240 EQUIVALENT PARELLEL RESISTANCE () MEASURED DIFFERENTIALLY -260 -280 -300 -320 -340 -360 -380 -400 80 160 240 320 400 480 FREQUENCY (MHz) 560 TANKL TANKH
TANKL
MEASURED DIFFERENTIALLY 160 240 320 400 400 560
FREQUENCY (MHz)
LOOUT PORT S11 vs. FREQUENCY
MAX2310 toc14
START: 10MHz STOP: 600MHz
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer
Pin Description
PIN MAX2306 1, 28 -- 2, 3 -- 4 MAX2308 -- 1, 4 2, 3 -- -- MAX2309 -- -- 1, 2 3 -- NAME TANKL+, TANKLN.C. TANKH+, TANKHBUFEN MODE FUNCTION Differential Tank Input for Low-Frequency Oscillator No Connection. Must be left open-circuit. Differential Tank Input for High-Frequency Oscillator LO Buffer Amplifier--active low Mode Select. High selects CDMA mode; low selects FM mode. Internal VCO Output. Depending on setting of BD bit, LOOUT is either the VCO frequency (twice the IF frequency) or one-half the VCO frequency (equal to the IF frequency). +2.7V to +5.5V Supply Ground Reference Frequency Input Shutdown Input--active low. Low powers down entire device, including registers and serial interface. Differential In-Phase Baseband Output, or FM signal output if FM_I mode is selected. Lock Output--open-collector pin. Logic high indicates phase-locked condition. Differential Quadrature-Phase Baseband Output. Disabled if FM_I mode is selected. Clock input of the 3-wire serial bus Enable Input. When low, input shift register is enabled. Data input of the 3-wire serial bus. +2.7V to +5.5V Supply VGA Gain Control Input. Control voltage range is 0.5V to 2.3V. Differential CDMA Input. Active in CDMA mode. Differential Positive Input. Active in FM mode. Differential Negative Input for FM signal. Bypass to GND for single-ended operation. Standby Input--active low. Low powers down VGA and demodulator while keeping VCO, PLL, and serial bus on. Bypass Node. Must be capacitively decoupled (bypassed) to pin 17.
MAX2306/MAX2308/MAX2309
-- 5 6 7 8 9, 10 11 12, 13 14 15 16 17 18 19, 20 21 22 -- 23, 24
-- 5 6 7 8 9, 10 11 12, 13 14 15 16 17 18 19, 20 21 22 -- 23, 24
4 5 6 7 8 9, 10 11 12, 13 14 15 16 17 18 19, 20 -- -- 22 23, 24
LOOUT VCC GND REF SHDN IOUT+, IOUTLOCK QOUT-, QOUT+ CLK EN DATA VCC VGC CDMA-, CDMA+ FM+ FMSTBY BYP
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2306/MAX2308/MAX2309
Pin Description (continued)
PIN MAX2306 25 26 27 -- -- MAX2308 25 26 27 28 -- Exposed Paddle MAX2309 25 26 27 21 28 NAME BYP CP_OUT GND N.C. DIVSEL EP FUNCTION Bypass Node. Must be capacitively decoupled (bypassed) to ground. Charge-Pump Output Ground No Connection High selects M1/R1; low selects M2/R2. Ground
_______________Detailed Description
MAX2306
The MAX2306 is intended for dual-band (PCS and cellular) and dual-mode code division multiple access (CDMA) and FM applications (Figure 1). The device includes an IF variable-gain amplifier, quadrature demodulator, dual VCOs, and dual-frequency synthesizers (Functional Diagram). Dual VCOs are provided for applications using different IF frequencies for each mode or band of operation. The analog FM output signal can be configured for conversion to the I channel, or it may be converted in quadrature to both the I and Q channels. The MAX2306's operation modes are described in Table 1. These modes are set by programming the control register and setting logic levels on control pins. If MODE is left floating, the internal register controls the operation. If driven high or low, mode will override certain register bits, as shown in Table 1.
tems implementing traditional limiting IF stages for FM demodulation in dual-mode phones as well as for the transmit LO in TDD systems. This buffered output can be configured for the VCO frequency (twice the IF frequency) or one-half the VCO frequency (IF frequency). The BUFEN pin enables this feature. A standby mode, in which only the VCO and synthesizer are operational, can be selected through the serial interface or the STBY pin. The MAX2309's operational modes are described in Table 3. These modes are set by programming the control register and/or setting logic levels on control pins. If the control pins (STBY, BUFEN, DIVSEL) are left floating, the internal register controls the operational mode. If driven high or low, the control pins will override certain register bits, as shown in Table 3.
Applications Information
Variable-Gain Amplifier and Demodulator
The MAX2306 family provides a VGA with exceptional gain range. The MAX2306/MAX2308 support multimode applications with dual differential inputs, selectable with the IN_SEL (IS) control bit. On the MAX2306, this function can be controlled with the MODE pin, which overrides the IS control bit. The VGA's gain is controlled over a 110dB range with the VGC pin. The output of the VGA drives the RF ports of a quadrature demodulator. The MAX2306/MAX2308 provide two types of FM demodulation, controlled by the FM_TYPE (FT) control bit. When FM_TYPE is "1," the signal is passed through both the I and Q signal paths for subsequent lowpass filtering and A/D conversion at baseband. If FM_TYPE is "0," the FM signal is passed through the I mixer only.
MAX2308
The MAX2308 supports dual-band, triple mode with common IF VCO. As with the MAX2306, the FM mode can be configured for conversion to the I port or quadrature conversion to both the I and Q ports (Figure 2). The MAX2308's operational modes are described in Table 2. These modes are set by programming the control register.
MAX2309
The MAX2309 quadrature demodulators are simplified versions of the MAX2306 that can be used in singlemode CDMA or triple mode using an external FM discriminator (Figure 3). The MAX2309 VCO is optimized for the 67MHz to 300MHz IF frequency range. The MAX2309 includes a buffered output for the VCO. The buffered VCO output can be used to support sys8
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2306/MAX2308/MAX2309
47pF 2.4k 0.01F 0.068F 0.01F BYP CP_OUT GND 10k 33pF TANKL+ 2pF 10k 33pF 33nH BYP BYP FMFM+ CDMA+ FM 0.01F 0.1F 0.01F VCC
MAX2306
TANKLCDMATANKH+ VGC
680
CDMA
10k
33pF
DAC 47pF
2pF 10k 33pF
33nH TANKHMODE
VCC
VCC DATA EN 3-WIRE
VCC 47pF
VCC GND REF SHDN IOUT+
CLK
QOUT+ 10k Q
I
10k IOUTQOUTLOCK
47k
VCC
Figure 1. MAX2306 Typical Operating Circuit
Voltage-Controlled Oscillator, Buffers, and Quadrature Generation
The LO signal for downconversion is provided by a voltage-controlled oscillator (VCO) consisting of an onchip differential oscillator, and an off-chip high-Q resonant network. Figure 4 shows a simplified schematic of the VCO oscillator. Multiband operation is supported by the MAX2306 with dual VCOs. VCO_H and VCO_L are selectable with the MODE pin or the VCO_SEL (VS) control bit. They oscillate at twice the desired LO frequency. For applications requiring an external LO, the VCOs can be bypassed with the VCO_BYP (VB) control bit.
The MAX2309 buffers the output of the VCO and provides this signal at the LOOUT pin. This signal is enabled by the BUFEN (BE) control bit or by the BUFEN control pin. The frequency of this signal is selected by the BUF_DIV (BD) control bit, and can be either the VCO frequency or half the VCO frequency. Quadrature downconversion is realized by providing inphase (I) and quadrature-phase (Q) components of the LO signal to the LO ports of the demodulator described above. The quadrature LO signals are generated by dividing the VCO output frequency using two latches.
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CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2306/MAX2308/MAX2309
Table 1. MAX2306 Control Register States
PINS M S B M CONTROL REGISTER S B L S B
TEST_MODE
VCO_BYP
VCO_SEL
FM_TYPE
TEST_EN
BUF_DIV
CP POL
DIVSEL
IN_SEL
BUFEN
MODE
SHDN
SHUTDOWN SHUTDOWN STANDBY CDMA CDMA FM_IQ FM_IQ FM_I FM_I
Shutdown pin completely powers down the chip 0 in shutdown register bit leaves serial port active 0 in standby register bit turns off VGA and modulator only Mode pin overrides VCO_SEL, DIVSEL, and IN_SEL to high Floating mode pin returns control to register Mode pin overrides VCO_SEL, DIVSEL, and IN_SEL to low Floating mode pin returns control to register Mode pin overrides VCO_SEL, DIVSEL, and IN_SEL to low Floating pins return control to register
L H H H H H H H H L
X X X H F L F L F
X X X
X X X
X X 0 0 0 0 0 0 0
X X
X X
X X
X X
X X X
X X X X X X X X X
X X
X X
X X 0
X 1 X
X 1 X
X X X X
X X 0 0 1 1
X 1 X 0 X 0
1 1 1 1 1 1
X
X
X X
Note: H = high, L = low, F = floating pin, X = don't care, Blank = independent parameter, 1 = logic high, 0 = logic low.
The appropriate latch outputs provide I and Q signals at the desired LO frequency.
Synthesizer
The VCO's output frequency is controlled by an internal phase-locked-loop (PLL) dual-modulus synthesizer. The loop filter is off-chip to simplify loop design for emerging applications. The tunable resonant network is also off-chip for maximum Q and for system design flexibility. The VCO output frequency is divided down to the desired comparison frequency with the M counter. The M counter consists of a 4-bit A swallow counter and a 10-bit P counter. A reference signal is provided from an external source and is divided down to the comparison frequency with the R counter. The two divided signals are compared with a three-state digital phase-frequen10
cy detector. The phase-detector output drives a charge-pump as well as lock-detect logic and turbocharge control logic. The charge-pump output (CP_OUT) pin is processed by the loop filter and drives the tunable resonant network, altering the VCO frequency and closing the loop. Multimode applications are supported by two independent programmable registers each for the M counter (M1, M2), the R counter (R1, R2), and the charge-pump output current magnitude (CP1, CP2). The DIVSEL (DS) bit selects which set of registers is used. It can be overridden by the MAX2306's MODE pin or the MAX2309's DIVSEL pin. Programming these registers is discussed in the 3-Wire Interface and Registers section.
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SHDN X 0 1 1 1 1 1 1 1
STBY
OPERATIONAL MODE
ACTION RESULT
TURBOCHARGE
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2306/MAX2308/MAX2309
Table 2. MAX2308 Control Register States
P I N M S B M S CONTROL REGISTER B L S B
TEST_MODE
VCO_BYP
VCO_SEL
FM_TYPE
TEST_EN
BUF_DIV
CP_POL
DIVSEL
IN_SEL
BUFEN
SHDN
SHUTDOWN SHUTDOWN STANDBY CDMA FM_IQ FM_I
Shutdown pin completely shuts down chip 0 in shutdown register bit leaves serial port active 0 in standby pin turns off VGA and modulator only CDMA operation FM IQ quadrature operation FM I operation
L H H H H H
X X
X X
X X 0 0 0 0
X X
X X
X X
X X 0 0 0 0
X X X X X X
X X X X X X
X X
X X
X X 0
X 0 1
1 0 0
1 1 1
Note: H = high, L = low, 1 = logic high, 0 = logic low, X = don't care, blank = independent parameter
When the part initially powers up or changes state, the synthesizer acquisition time can be reduced by using the Turbo feature, enabled by the TURBOCHARGE (TC) control bit. Turbo functionality provides a larger charge-pump current during acquisition mode. Once the VCO frequency is acquired, the charge-pump output current magnitude automatically returns to the preprogrammed state to maintain loop stability and minimize spurs in the VCO output signal. The lock detect output indicates when the PLL is locked with a logic high.
Whenever the M or R divide register value is programmed and downloaded, the control register must also be subsequently updated. This prevents turbolock from going active when not desired. The SHDN control bit is notable because it differs from the SHDN pin. When the SHDN control bit is low, the registers and serial interface are left active, retaining the values stored in the latches, while the rest of the device is shut off. In contrast, the SHDN pin, when low, shuts down everything, including the registers and serial interface. See Functional Diagram.
3-Wire Interface and Registers
The MAX2306 family incorporates a 3-wire interface for synthesizer programming and device configuration (Figure 5). The 3-wire interface consists of clock, data, and enable signals. It controls the VCO dividers (M1 and M2), reference frequency dividers (R1 and R2), and a 13-bit control register. The control register is used to set up the operational modes (Table 4). The input shift is 17 data bits long and requires a total of 18 clock bits (Figure 6). A single clock pulse is required before enable drops low to initialize the data bus.
Registers
Figure 7 shows the programming logic. The 17-bit shift register is programmed by clocking in data at the rising edge of CLK. Before the shift register is able to accept data, it must be initialized by driving it with at least one full clock cycle at the CLK input with EN high (see Figure 6). Pulling enable low will allow data to be clocked into the shift register; pulling enable high loads the register addressed by A0, A1, and A2, respectively (Figure 7). Table 5 lists the power-on default values of all registers. Table 6 lists the charge-pump current, depending on CP0 and CP1.
11
______________________________________________________________________________________
SHDN X L 1 1 1 1
OPERATIONAL MODE
ACTION RESULT
TURBOCHARGE
STBY
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2306/MAX2308/MAX2309
47pF
2.4k 0.01F BYP 0.068F 0.01F BYP 0.01F VCC 0.01F BYP 0.01F FMTANKH+ FM+ 2pF 10k 33pF TANKHCDMAVGC VCC 47pF GND REF SHDN I_OUT+ 10k I_OUTQ_OUTLOCK 47k DATA EN CLK Q_OUT+ 10k Q 3-WIRE VCC VCC VCC 47pF DAC 680 CDMA 33nH CDMA+ FM VCC
MAX2308
CP_OUT 10k 33pF GND
VCC
Figure 2. MAX2308 Typical Operating Circuit
12
______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2306/MAX2308/MAX2309
Table 3. MAX2309 Control Register States
PINS M S B CONTROL REGISTER L S B
TEST_MODE
VCO_BYP
VCO_SEL
FM_TYPE
TES_TEN
BUF_DIV
CP_POL
DIVSEL
DIVSEL
IN_SEL
BUFEN
BUFEN
SHDN
SHUTDOWN
Shutdown pin completely powers down the chip 0 in shutdown register bit leaves serial bus active 0 in standby pin turns off VGA and modulator only 0 in standby register bit turns off VGA and modulator only DIVSEL pin overrides DIVSEL register bit If DIVSEL pin is floated, then register bit selects divider BUFEN pin controls the LO buffer and overrides the bit If pin is floated, then BUFEN register bit controls buffer
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SHUTDOWN
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
STANDBY
H
L
0
X
X
STANDBY DIVIDER SELECT DIVIDER SELECT LO BUFFER ENABLE LO BUFFER ENABLE
H
H/ L H/ L F
H
0
X
0
H
H
0
X 1/ 0
X
H
H
0
X
H/ L
H
0
X
X
H
F
0
X
1/ 0
Note: H = high, L = low, 1 = logic high, 0 = logic low, X = don't care, blank = independent parameter.
______________________________________________________________________________________
SHDN X 0 1 1 1 1 1 1 13
STBY
STBY
OPERATIONAL MODE
ACTION RESULT
TURBOCHARGE
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2306/MAX2308/MAX2309
47pF 0.068F 0.01F 2.4k 0.01F CP_OUT GND 10k 33pF DIVSEL TANKH+ 2pF 10k 33pF 33nH CDMA+ 680 CDMA BYP STBY BYP BYP 0.01F VCC 0.01F VCC
MAX2309
TANKHCDMAVGC VCC DATA EN CLK QOUT+ 10k IOUTQOUTLOCK 47k Q 3-WIRE VCC DAC 47pF
DISCRIMINATOR
BUFEN LOOUT
455kHz
VCC 47pF
VCC GND REF SHDN IOUT+
LIMITER
I
10k
FM
VCC
Figure 3. MAX2309 Typical Operating Circuit
14
______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2306/MAX2308/MAX2309
VCC
800A
D1 R1 TANK_+ RL CF RB RB CF RL TANK_-
RE
RE
Figure 4. Voltage-Controlled Oscillators
VCO_H
14-BIT M1 COUNTER (00) DATA CLK EN START BIT M U X 16-BIT DATA/ADDRESS REGISTER (11X) 13-BIT CONTROL REGISTER CP2 (01) (010) (011) 2-BIT CP2 11-BIT R2 COUNTER 2-BIT CP1 11-BIT R1 COUNTER FREF CPOUT CPI
VCO_L
14-BIT M2 COUNTER
Figure 5. 3-Wire Control Block Diagram
______________________________________________________________________________________
15
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2306/MAX2308/MAX2309
MSB DATA *SB *START BIT MUST BE LOGIC HIGH. LSB
CLK RISE AND FALL REQUIRED PRIOR TO EN GOING LOW. EN
Figure 6. 3-Wire Interface Timing Diagram
Table 4. Control Register, Default State: 0B57h, Address: 110b
BIT ID TM BIT NAME TEST_MODE POWERUP STATE 0 BIT LOCATION 0 = LSB 12 FUNCTION Must be 0 for normal operation. Logic "1" causes the charge-pump output CP_OUT to source current when fREF/R > fVCO/M. This state is used when the VCO tune polarity is such that increasing voltage produces increasing frequency. Logic "0" causes CP_OUT to source current when fVCO/M > fREF/R. This state is used when increasing tune voltage causes the VCO frequency to decrease. Must be 0 for normal operation. Logic "1" activates turbocharge mode, which provides rapid frequency acquisition in the PLL. Logic "1" selects M1/R1 divide ratios. Logic "0" selects M2/R2. Logic "1" bypasses the VCO inputs for external VCO operation. Logic "1" selects VCO_H. Logic "0" selects VCO_L. Logic "1" selects divide-by-2 on LOOUT port. Logic "0" bypasses divider. Logic "1" disables LOOUT. Logic "0" enables LOOUT. Active in FM mode. Logic "0" selects quadrature demodulator for FM mode. Logic "1" selects downconversion to I port. Logic "0" selects FM input port. Logic "1" selects CDMA input. Logic "0" enables standby mode, which shuts down the VGA and demodulator stages, leaving the VCO locked and the registers active. Logic "0" enables register-based shutdown. This mode shuts down everything except the M and R latches and the serial bus.
POL
CP_POL
1
11
TE TC DS VB VS BD BE FT IS SB
TEST_ENABLE TURBO_CHARGE DIV_SEL VCO_BYP VCO_SEL BUF_DIV BUFEN FM_TYPE IN_SEL STBY
0 1 1 0 1 0 1 0 1 1
10 9 8 7 6 5 4 3 2 1
SD
SHDN
1
0
16
______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2306/MAX2308/MAX2309
ADDRESS DECODED START BIT SHIFT REGISTER 1 A2/M0 A2/M0 A1 A1 A0 A0 DATA
M1 REGISTER
M113
M1/0
0
0
M2 REGISTER
M213
M2/0
0
1
CP1 AND R1 REGISTERS
CP1/1 CP1/0 R1/10
R1/0
0
1
0
CP2 AND R2 REGISTERS
CP2/1 CP2/0 R2/10
/1
R2/0
0
1
1
CTRL REGISTER
TM
POL
TE
TC
DS
VB
VS
BD
BE
FT
IS
SB
SD
1
1
0
Figure 7. Programming Logic
Table 5. Register Defaults
REGISTER M1 M2 R1 R2 CTRL CP0 CP1 DEFAULT 10519DEC 4269DEC 492DEC 492DEC 0B57HEX 11BIN 11BIN
Table 6. Charge-Pump Control Bits
CP1 0 0 1 1 CP0 0 1 0 1 CHARGE-PUMP CURRENT AFTER ACQUISITION (A) 150 210 300 425
Chip Information
TRANSISTOR COUNT: 6422
______________________________________________________________________________________
17
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2306/MAX2308/MAX2309
Functional Diagram
MAX2306 MAX2308 MAX2309
EN CLK DATA
CDMA+ CDMAMAX2306 MAX2308 FM+ FMM1 REGISTER 00 14 FT VGC IOUT+ IOUT-
SB 1 SHIFT REGISTER
LOGIC
/2 QOUT+ QOUT-
M2 REGISTER 2 010
01
14
CP1
R1 REGISTER
MAX2309
11 DIVSEL
MAX2306 MODE IS VS
2
CP2
R2 REGISTER
011
11
TM POL TE
TC
DS
VB
VS
BD BE
FT
IS
SB
SD 110
DS VCO_L 14 14 TANKL+
CONTROL 2 2 11 11
2
11 R COUNTER
14 M COUNTER VB
TANKL-
REF POL O DET LOCK DET TANKH+ TANKH-
TURBO CONTROL 2 CHARGE PUMP
TC
VCO_H
LOCK
SHDN
BIAS CP_OUT
/2
LO_OUT BUFEN
STBY MAX2309 SB SD
BD
BE MAX2309
18
______________________________________________________________________________________
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer
Block Diagram
MAX2306/MAX2308/MAX2309
DAC VCC
AVCC BYP BYP FMFM+ CDMA+ CDMAVGA DATA EN CLK
QOUT+ QOUT- LOCK VCC
0 90 /2
MAX2306
/M CHARGE PUMP PHASE DETECTOR /R BYP CP_OUT AGND TANKL+ TANKLTANKH+ TANKHREF MODE DVCC SHDN IOUT+ IOUT-
______________________________________________________________________________________
19
CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer MAX2306/MAX2308/MAX2309
Pin Configurations
TOP VIEW
CP_OUT CP_OUT TANKL-
GND
GND
N.C.
BYP
BYP
BYP
BYP
BYP
BYP
FM-
28
27
26
25
24
23
22
28
27
26
25
24
23
TANKL+ TANKH+ TANKHMODE VCC GND REF
1 2 3 4 5 6 7 10 11 12 13 14 8 9
21 20 19
FM+ CDMA+ CDMAVGC VCC DATA EN
N.C. TANKH+ TANKHN.C. VCC GND REF
1 2 3 4 5 6 7 10 11 12 13 14 8 9
22
*
*
*
FM-
*
21 20 19
FM+ CDMA+ CDMAVGC VCC DATA EN
MAX2306
18 17 16 15
MAX2308
18 17 16 15
CLK
LOCK
SHDN
IOUT+
QOUT-
QOUT+
SHDN
IOUT-
IOUT+
IOUT-
LOCK
QOUT-
QFN-EP
CP_OUT DIVSEL
QFN-EP
28
27
26
25
24
23
TANKH+ TANKHBUFEN LOOUT VCC GND REF
1 2 3 4 5 6 7 10 11 12 13 14 8 9
22
*
STBY
GND
BYP
BYP
BYP
*
21 20 19
N.C. CDMA+ CDMAVGC VCC DATA EN
MAX2309
18 17 16 15
SHDN
IOUT+
IOUT-
LOCK
QOUT-
QFN-EP
*ELECTRICALLY CONNECTED TO THE EXPOSED PADDLE.
QOUT+
CLK
*
*
Package Information
For the latest package outline information, go to www.maxim-ic.com/packages.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
QOUT+
CLK
*
*
*
*

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