 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| WM8190 (8 + 6) Bit Output 14-bit CIS/CCD AFE/Digitiser Advanced Information, August 1999, Rev 3.0 DESCRIPTION The WM8190 is a 14-bit analogue front end/digitiser IC which processes and digitises the analogue output signals from CCD sensors or Contact Image Sensors (CIS) at pixel sample rates of up to 6MSPS. The device includes three analogue signal processing channels each of which contains Reset Level Clamping, Correlated Double Sampling and Programmable Gain and Offset adjust functions. Three multiplexers allow single channel processing. The output from each of these channels is time multiplexed into a single high-speed 14-bit Analogue to Digital Converter. The digital output data is available in 8, 7 or 4-bit wide multiplexed format, with no missing codes. An internal 4-bit DAC is supplied for internal reference level generation. This may be used during CDS to reference CIS signals or during Reset Level Clamping to clamp CCD signals. An external reference level may also be supplied. ADC references are generated internally, ensuring optimum performance from the device. Using an analogue supply voltage of 5V and a digital interface supply of either 5V or 3.3V, the WM8190 typically only consumes 250mW when operating from a single 5V supply. FEATURES * * * * * * * * * * * * * * 14-bit ADC No missing codes guaranteed 6MSPS conversion rate Low power - 250mW typical 5V single supply or 5V/3.3V dual supply operation Single or 3 channel operation Correlated double sampling Programmable gain (8-bit resolution) Programmable offset adjust (8-bit resolution) Programmable clamp voltage 8,7 or 4-bit wide multiplexed data output formats Internally generated voltage references 28-pin SOIC package Serial control interface APPLICATIONS * * * * Flatbed and sheetfeed scanners USB compatible scanners Multi-function peripherals High-performance CCD sensor interface BLOCK DIAGRAM VRLC/VBIAS (26) VSMP (5) MCLK (7) AVDD (21) DVDD1 DVDD2 (3) (10) VRT VRX V R B (24) (25) (23) CL RS VS TIMING CONTROL R G B VREF/BIAS M U X 8 WM8190 (4) OEB OFFSET DAC + PGA 8 RINP (1) RLC M U X CDS R G B M U X + I/P SIGNAL POLARITY ADJUST M U X 14BIT ADC DATA I/O PORT (13) (14) (15) (16) (17) (18) (19) (20) OP[0] OP[1] OP[2] OP[3] OP[4] OP[5] OP[6] OP[7]/SDO GINP (28) RLC CDS 8 + OFFSET DAC PGA 8 + I/P SIGNAL POLARITY ADJUST BINP (27) RLC CDS 8 + OFFSET DAC PGA 8 + I/P SIGNAL POLARITY ADJUST RLC DAC 4 CONFIGURABLE SERIAL CONTROL INTERFACE (9) SEN (12) SCK (11) SDI (6) RLC/ACYC (22) AGND1 (2) AGND2 (8) DGND WOLFSON MICROELECTRONICS LTD Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk http://www.wolfson.co.uk Advanced Information data sheets contain preliminary data on new products in the preproduction phase of development. Supplementary data will be published at a later date. (c)1999 Wolfson Microelectronics Ltd. WM8190 PIN CONFIGURATION RINP AGND2 DVDD1 OEB VSMP RLC/ACYC MCLK DGND SEN DVDD2 SDI SCK OP[0] OP[1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GINP BINP VRLC/VBIAS VRX VRT VRB AGND1 AVDD OP[7]/SDO OP[6] OP[5] OP[4] OP[3] OP[2] Advanced Information ORDERING INFORMATION DEVICE XWM8190CDW/V TEMP. RANGE 0 to 70 C o PACKAGE 28-pin SOIC PIN DESCRIPTION PIN 1 2 3 4 5 6 7 8 9 10 11 12 NAME RINP AGND2 DVDD1 OEB VSMP RLC/ACYC MCLK DGND SEN DVDD2 SDI SCK TYPE Analogue input Supply Supply Digital input Digital input Digital input Digital input Supply Digital input Supply Digital input Digital input DESCRIPTION Red channel input video. Analogue ground (0V). Digital supply (5V) for logic and clock generator. This must be operated at the same potential as AVDD. Output Hi-Z control, all digital outputs disabled when OEB = 1. Video sample synchronisation pulse. RLC (active high) selects reset level clamp on a pixel-by-pixel basis - tie high if used on every pixel. ACYC autocycles between R, G, B inputs. Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or any multiple of 2 thereafter depending on input sample mode). Digital ground (0V). Enables the serial interface when high. Digital supply (5V/3.3V), all digital I/O pins. Serial data input. Serial clock. Digital multiplexed output data bus. ADC output data (d13:d0) and error flags (F) are available in three multiplexed formats as shown, under the control of register bit MUXOP[1:0]. See `Output Formats' description in Device Description section for further details. 8+6-bit A 13 14 15 16 17 18 19 20 OP[0] OP[1] OP[2] OP[3] OP[4] OP[5] OP[6] OP[7] Digital output Digital output Digital output Digital output Digital output Digital output Digital output Digital output d6 d7 d8 d9 d10 d11 d12 d13 B F F d0 d1 d2 d3 d4 d5 A F d7 d8 d9 d10 d11 d12 d13 7+7-bit B F d0 d1 d2 d3 d4 d5 d6 d10 d11 d12 d13 d6 d7 d8 d9 d2 d3 d4 d5 F F d0 d1 A 4+4+4+2-bit B C D Alternatively, pin OP[7]/SDO may be used to output register read-back data when OEB = 0 and SEN has been pulsed high. See Serial Interface description in Device Description section for further details. WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 2 Advanced Information PIN 21 22 23 24 25 26 NAME AVDD AGND1 VRB VRT VRX VRLC/VBIAS TYPE Supply Supply Analogue output Analogue output Analogue output Analogue I/O DESCRIPTION WM8190 Analogue supply (5V). This must be operated at the same potential as DVDD1. Analogue ground (0V). Lower reference voltage. This pin must be connected to AGND via a decoupling capacitor. Upper reference voltage. This pin must be connected to AGND via a decoupling capacitor. Input return bias voltage. This pin must be connected to AGND via a decoupling capacitor. Selectable analogue output voltage for RLC or single-ended bias reference. This pin would typically be connected to AGND via a decoupling capacitor. VRLC can be externally driven if programmed Hi-Z. Blue channel input video. Green channel input video. 27 28 BINP GINP Analogue input Analogue input ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. As per JEDEC specifications A112-A and A113-B, this product requires specific storage conditions prior to surface mount assembly. It is anticipated as having a Moisture Sensitivity Level of 2 and as such will be supplied in vacuum-sealed moisture barrier bags. CONDITION Analogue supply voltage: AVDD Digital supply voltages: DVDD1 - 2 Digital ground: DGND Analogue grounds: AGND1 - 2 Digital inputs, digital outputs and digital I/O pins Analogue inputs (RINP, GINP, BINP) Other pins Operating temperature range: TA Storage temperature Lead temperature (soldering, 10 sec) Lead temperature (soldering, 2 mins) Notes: 1. GND denotes the voltage of any ground pin. MIN GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V GND - 0.3V 0C -65C MAX GND + 7V GND + 7V GND + 0.3V GND + 0.3V DVDD2 + 0.3V AVDD + 0.3V AVDD + 0.3V +70C +150C +260C +183C 2. AGND1, AGND2 and DGND pins are intended to be operated at the same potential. Differential voltages between these pins will degrade performance. RECOMMENDED OPERATING CONDITIONS CONDITION Operating temperature range Analogue supply voltage Digital core supply voltage Digital I/O supply voltage 5V I/O 3.3V I/O SYMBOL TA AVDD DVDD1 DVDD2 DVDD2 MIN 0 4.75 4.75 4.75 2.97 5.0 5.0 5.0 3.3 TYP MAX 70 5.25 5.25 5.25 3.63 UNITS C V V V V WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 3 WM8190 ELECTRICAL CHARACTERISTICS Advanced Information Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 12MHz unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Overall System Specification (including 14-bit ADC, PGA, Offset and CDS functions) NO MISSING CODES GUARANTEED Full-scale input voltage range (see Note 1) Input signal limits (see Note 2) Full-scale transition error Zero-scale transition error Differential non-linearity Integral non-linearity Channel to channel gain matching References Upper reference voltage Lower reference voltage Input return bias voltage Diff. reference voltage (VRT-VRB) Output resistance VRT, VRB, VRX VRLC/Reset-Level Clamp (RLC) RLC switching impedance VRLC short-circuit current VRLC output resistance VRLC Hi-Z leakage current RLCDAC resolution RLCDAC step size, RLCDAC = 0 RLCDAC step size, RLCDAC = 1 RLCDAC output voltage at code 0(hex), RLCDACRNG = 0 RLCDAC output voltage at code 0(hex), RLCDACRNG = 1 RLCDAC output voltage at code F(hex) RLCDACRNG, = 0 RLCDAC output voltage at code F(hex), RLCDACRNG = 1 VRLC deviation Offset DAC, Monotonicity Guaranteed Resolution Differential non-linearity Integral non-linearity Step size Output voltage Notes: 1. 2. Code 00(hex) Code FF(hex) DNL INL 8 0.1 0.25 2.04 -260 +260 0.5 1 bits LSB LSB mV/step mV mV VRLCSTEP VRLCSTEP VRLCBOT VRLCBOT VRLCTOP VRLCTOP -50 VRLC = 0 to AVDD 4 0.24 0.16 0.40 0.25 4.20 2.85 +50 50 5 2 1 mA A bits V/step V/step V V V V mV VRT VRB VRX VRTB 2.85 1.35 0.65 1.5 1 V V V V DNL INL VIN Gain = 0dB; PGA[7:0] = 4B(hex) Gain = 0dB; PGA[7:0] = 4B(hex) Max Gain Min Gain 0 20 20 0.65 4 1 0.4 4.08 AVDD Vp-p Vp-p V mV mV LSB LSB % Full-scale input voltage denotes the maximum amplitude of the input signal at the specified gain. Input signal limits are the limits within which the full-scale input voltage signal must lie. WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 4 Advanced Information WM8190 Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 12MHz unless otherwise stated. PARAMETER Programmable Gain Amplifier Resolution Gain Max gain, each channel Min gain, each channel Gain error, each channel DIGITAL SPECIFICATIONS Digital Inputs High level input voltage Low level input voltage High level input current Low level input current Input capacitance Digital Outputs High level output voltage Low level output voltage High impedance output current Digital IO Pins Applied high level input voltage Applied low level input voltage High level output voltage Low level output voltage Low level input current High level input current Input capacitance High impedance output current Supply Currents Total supply current - active Total analogue supply current - active Digital core supply current, DVDD1 - active Digital I/O supply current, DVDD2 - active Supply current - full power down mode IAVDD 50 47 2 1 100 mA mA mA mA A VIH VIL VOH VOL IIL IIH CI IOZ 5 1 IOH = 1mA IOL = 1mA DVDD2 - 0.5 0.5 1 1 0.8 DVDD2 0.2 DVDD2 V V V V A A pF A VOH VOL IOZ IOH = 1mA IOL = 1mA DVDD2 - 0.5 0.5 1 V V A VIH VIL IIH IIL CI 5 0.8 DVDD2 0.2 DVDD2 1 1 V V A A pF GMAX GMIN 8 208 283 - PGA[7 : 0] SYMBOL TEST CONDITIONS MIN TYP MAX UNIT bits V/V V/V V/V % 7.4 0.74 1 WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 5 WM8190 INPUT VIDEO SAMPLING tP E R MCLK tV S M P S U VSMP INPUT tV S U VIDEO tV H tR S U tR H tV S M P H tM C L K H tM C L K L Advanced Information Figure 1 Input Video Timing Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 12MHz unless otherwise stated PARAMETER MCLK period MCLK high period MCLK low period VSMP set-up time VSMP hold time Video level set-up time Video level hold time Reset level set-up time Reset level hold time Notes: 1. 2. SYMBOL tPER tMCLKH tMCLKL tVSMPSU tVSMPH tVSU tVH tRSU tRH TEST CONDITIONS MIN 83.3 37.5 37.5 10 5 15 5 15 5 TYP MAX UNITS ns ns ns ns ns ns ns ns ns tVSU and tRSU denote the set-up time required after the input video signal has settled. Parameters are measured at 50% of the rising/falling edge. OUTPUT DATA TIMING MCLK tPD OP[7:0] Figure 2 Output Data Timing WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 6 Advanced Information WM8190 OEB t PZE OP[7:0] Hi-Z t PEZ Hi-Z Figure 3 Output Data Enable Timing Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 12MHz unless otherwise stated PARAMETER Output propagation delay Output enable time Output disable time SYMBOL tPD tPZE tPEZ TEST CONDITIONS IOH = 1mA, IOL = 1mA MIN TYP MAX 75 50 25 UNITS ns ns ns SERIAL INTERFACE t SPER SCK t SSU SDI t SCE SEN tSERD ADC DATA SDO MSB REGISTER DATA LSB tS C R D t SCRDZ ADC DATA tS E W t SEC t SH t SCKL t S C K H Figure 4 Serial Interface Timing Test Conditions AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70C, MCLK = 12MHz unless otherwise stated PARAMETER SCK period SCK high SCK low SDI set-up time SDI hold time SCK to SEN set-up time SEN to SCK set-up time SEN pulse width SEN low to SDO = Register data SCK low to SDO = Register data SCK low to SDO = ADC data SYMBOL tSPER tSCKH tSCKL tSSU tSH tSCE tSEC tSEW tSERD tSCRD tSCRDZ TEST CONDITIONS MIN 83.3 37.5 37.5 10 10 20 20 50 35 35 25 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns Note: Parameters are measured at 50% of the rising/falling edge WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 7 WM8190 TYPICAL OVERALL SYSTEM PERFORMANCE DNL VS CODES 2 Advanced Information 1.5 1 0.5 DNL (LSB) 0 -0.5 -1 -1.5 -2 0 1024 2048 3072 4096 5120 6144 7168 8192 9216 10240 11264 12288 13312 14336 15360 Output Data Code Figure 5 DNL Vs Output Data Codes INL vs CODES 16 14 12 10 8 6 4 INL (LSB) 2 0 -2 -4 -6 -8 -10 -12 -14 -16 0 1024 2048 3072 4096 5120 6144 7168 8192 9216 10240 11264 12288 13312 14336 15360 Output Data Code Figure 6 INL Vs Output Data Codes WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 8 Advanced Information WM8190 DEVICE DESCRIPTION INTRODUCTION A block diagram of the device showing the signal path is presented on Page 1. The WM8190 samples up to three inputs (RINP, GINP and BINP) simultaneously. The device then processes the sampled video signal with respect to the video reset level or an internally/externally generated reference level using either one or three processing channels. Each processing channel consists of an Input Sampling block with optional Reset Level Clamping (RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and an 8-bit Programmable Gain Amplifier (PGA). The ADC then converts each resulting analogue signal to a 14-bit digital word. The digital output from the ADC is presented on an 8-bit wide bi-directional bus, with optional 8+6-bit, 7+7-bit or 4+4+4+2-bit multiplexed formats. On-chip control registers determine the configuration of the device, including the offsets and gains applied to each channel. These registers are programmable via a serial interface. INPUT SAMPLING The WM8190 can sample and process one to three inputs through one or three processing channels as follows: Colour Pixel-by-Pixel: The three inputs (RINP, GINP and BINP) are simultaneously sampled for each pixel and a separate channel processes each input. The signals are then multiplexed into the ADC, which converts all three inputs within the pixel period. Monochrome: A single chosen input (RINP, GINP, or BINP) is sampled, processed by the corresponding channel, and converted by the ADC. The choice of input and channel can be changed via the control interface, e.g. on a line-by-line basis if required. Colour Line-by-Line: A single chosen input (RINP, GINP, or BINP) is sampled and multiplexed into the red channel for processing before being converted by the ADC. The input selected can be switched in turn (RINP GINP BINP RINP...) together with the PGA and Offset DAC control registers by pulsing the RLC/ACYC pin. This is known as auto-cycling. Alternatively, other sampling sequences can be generated via the control registers. This mode causes the blue and green channels to be powered down. Refer to the Line-by-Line Operation section for more details. RESET LEVEL CLAMPING (RLC) To ensure that the signal applied to the WM8190 lies within its input range (0V to AVDD) the CCD output signal is usually level shifted by coupling through a capacitor, CIN. The RLC circuit clamps the WM8190 side of this capacitor to a suitable voltage during the CCD reset period. A typical input configuration is shown in Figure 7. A clamp pulse, CL, is generated from MCLK and VSMP by the Timing Control Block. When CL is active the voltage on the WM8190 side of CIN, at RINP, is forced to the VRLC/VBIAS voltage (VVRLC ) by switch 1. When the CL pulse turns off, the voltage at RINP initially remains at VVRLC but any subsequent variation in sensor voltage (from reset to video level) will couple through CIN to RINP. RLC is compatible with both CDS and non-CDS operating modes, as selected by switch 2. Refer to the CDS/non-CDS Processing section. WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 9 WM8190 RLC/ACYC MCLK VSMP Advanced Information TIMING CONTROL CL RS VS FROM CONTROL INTERFACE C IN S/H + RINP 1 RLC 2 + S/H CDS INPUT SAMPLING BLOCK FOR RED CHANNEL TO OFFSET DAC EXTERNAL VRLC VRLC/ VBIAS 4-BIT RLC DAC VRLCEXT CDS FROM CONTROL INTERFACE Figure 7 Reset Level Clamping and CDS Circuitry If auto-cycling is not required, RLC can be selected by pin RLC/ACYC. Figure 8 illustrates control of RLC for a typical CCD waveform, with CL applied during the reset period. The input signal applied to the RLC pin is sampled on the positive edge of MCLK that occurs during each VSMP pulse. The sampled level, high (or low) controls the presence (or absence) of the internal CL pulse on the next reset level. The position of CL can be adjusted by using control bits CDSREF[1:0] (Figure 9). If auto-cycling is required, pin RLC/ACYC is no longer available for this function and control bit RLCINT determines whether clamping is applied. MCLK VSMP RLC/ACYC 1 X Programmable Delay X 0 X X 0 CL (CDSREF = 01) INPUT VIDEO RGB RGB RLC on this Pixel RGB No RLC on this Pixel Figure 8 Relationship of RLC Pin, MCLK and VSMP to Internal Clamp Pulse, CL The VRLC/VBIAS pin can be driven internally by a 4-bit DAC (RLCDAC) by writing to control bits RLCV[3:0]. The RLCDAC range and step size may be increased by writing to control bit RLCDACRNG. Alternatively, the VRLC/VBIAS pin can be driven externally by writing to control bit VRLCEXT to disable the RLCDAC and then applying a d.c. voltage to the pin. CDS/NON-CDS PROCESSING For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel common mode noise. For CDS operation, the video level is processed with respect to the video reset level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must be set to 1 (default), this controls switch 2 (Figure 7) and causes the signal reference to come from the video reset level. The time at which the reset level is sampled, by clock Rs/CL, is adjustable by programming control bits CDSREF[1:0], as shown in Figure 9. WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 10 Advanced Information WM8190 MCLK VSMP VS R S /CL (CDSREF = 00) R S /CL (CDSREF = 01) R S /CL (CDSREF = 10) R S /CL (CDSREF = 11) Figure 9 Reset Sample and Clamp Timing For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described above. The VRLC/VBIAS pin is sampled by Rs at the same time as Vs samples the video level in this mode. OFFSET ADJUST AND PROGRAMMABLE GAIN The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset for each channel are independently programmable by writing to control bits DAC[7:0] and PGA[7:0]. In colour line-by-line mode the gain and offset coefficients for each colour can be multiplexed in order (Red Green Blue Red...) by pulsing the ACYC/RLC pin, or controlled via the FME, ACYCNRLC and INTM[1:0] bits. Refer to the Line-by-Line Operation section for more details. ADC INPUT BLACK LEVEL ADJUST The output from the PGA must be offset to match the full-scale range of the ADC. For negative-going input signals, a black level (zero differential) output from the PGA should be offset to the top of the ADC range. For positive going input signal the black level should be offset to the bottom of the ADC range. This is achieved by writing to control bits PGAFS[1:0]. OVERALL SIGNAL FLOW SUMMARY Figure 10 represents the processing of the video signal through the WM8190. INPUT SAMPLING OFFSET DAC PGA BLOCK BLOCK BLOCK ADC BLOCK OUTPUT INVERT BLOCK TO MULTIPLEXER FOR 8-BIT OUTPUT V1 V IN CDS = 1 V RESET CDS = 0 V VRLC RLCEXT=1 RLCEXT=0 Offset DAC V2 ++ V3 + - X analog x (16383/V FS ) +0 if PGAFS[1:0]=11 +16383 if PGAFS[1:0]=10 +8191 if PGAFS[1:0]=0x D1 digital D2 OP[13:0] D2 = D1 if INVOP = 0 D2 = 16383-D1 if INVOP = 1 PGA gain A = 208/(283-PGA[7:0]) 260mV*(DAC[7:0]-127.5)/127.5 V IN is RINP or GINP or BINP V R E S E T is V IN sampled during reset clamp V V R L C is voltage applied to VRLC pin CDS, RLCEXT,RLCV[3:0], DAC[7:0], PGA[7:0], PGAFS[1:0] and INVOP are set by programming internal control registers. CDS=1 for CDS, 0 for non-CDS RLC DAC V R L C S T E P*RLCV[3:0] + V R L C B O T Figure 10 Overall Signal Flow WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 11 WM8190 Advanced Information The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC, optionally set via the RLC DAC. The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the black level of the input signal towards 0V, producing V2. The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range, outputting voltage V3. The ADC BLOCK then converts the analogue signal, V3, to a 14-bit unsigned digital output, D1. The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D2. CALCULATING OUTPUT FOR ANY GIVEN INPUT The following equations describe the processing of the video and reset level signals through the WM8190. INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the input video. V1 = VIN - VRESET ................................................................... Eqn. 1 If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted instead. V1 = VIN - VVRLC ..................................................................... Eqn. 2 If RLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS. If RLCEXT = 0, VVRLC is the output from the internal RLC DAC. VVRLC = (VRLCSTEP RLCV[3:0]) + VRLCBOT ................................. Eqn. 3 VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC. OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST The resultant signal V1 is added to the Offset DAC output. V2 = V1 + {260mV (DAC[7:0]-127.5) } / 127.5 ..................... Eqn. 4 PGA NODE: GAIN ADJUST The signal is then multiplied by the PGA gain, V3 = V2 208/(283- PGA[7:0]) ............................................... Eqn. 5 ADC BLOCK: ANALOGUE-DIGITAL CONVERSION The analogue signal is then converted to a 14-bit unsigned number, with input range configured by PGAFS[1:0]. D1[13:0] = INT{ (V3 /VFS) 16383} + 8191 D1[13:0] = INT{ (V3 /VFS) 16383} PGAFS[1:0] = 00 or 01 ...... Eqn. 6 PGAFS[1:0] = 11 ............... Eqn. 7 D1[13:0] = INT{ (V3 /VFS) 16383} + 16383 PGAFS[1:0] = 10 ............... Eqn. 8 where the ADC full-scale range, VFS = 3V OUTPUT INVERT BLOCK: POLARITY ADJUST The polarity of the digital output may be inverted by control bit INVOP. D2[13:0] = D1[13:0] D2[13:0] = 16383 - D1[13:0] (INVOP = 0) ....................... Eqn. 9 (INVOP = 1) ....................... Eqn. 10 WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 12 Advanced Information WM8190 The digital data output from the ADC is available to the user in 8/7/4-bit wide multiplexed formats by setting control bits MUXOP[1:0]. Latency of valid output data with respect to VSMP is programmable by writing to control bits DEL[1:0]. The latency for each mode is shown in the Operating Mode Timing Diagrams section. Figure 11 shows the output data formats for Modes 1 - 2 and 4 - 6. Figure 12 shows the output data formats for Mode 3. Table 1 summarises the output data obtained for each format. OUTPUT FORMATS MCLK MCLK 8+6 AND 7+7-BIT OUTPUT A B 8+6 AND 7+7-BIT OUTPUT A B 4+4+4+2-BIT OUTPUT A B C D 4+4+4+2-BIT OUTPUT ABABCD Figure 11 Output Data Formats (Modes 1 - 2, 4 - 6) OUTPUT FORMAT 8+6-bit multiplexed 7+7-bit 4+4+4+2-bit (nibble) MUXOP[1:0] 0X 10 11 OUTPUT PINS OP[7:0] OP[7:0] OP[7:4] Figure 12 Output Data Formats (Mode 3) OUTPUT A = d13, d12, d11, d10, d9, d8, d7, d6, d5 B = d4, d3, d2, d1, d0, CC, OVRNG A = d13, d12, d11, d10, d9, d8, d7, CC B = d6, d5, d4, d3, d2, d1, d0, OVRNG A = d13, d12, d11, d10 B = d9, d8, d7, d6 C = d5, d4, d3, d2 D = d1, d0, CC, OVRNG Table 1 Details of Output Data Shown in Figure 11 and Figure 12. FLAGS The following flags are output during multiplexed modes: CC can be used in colour modes 1 and 5 to identify the green channel output, from which the blue and red data can be identified. INPUT RINP GINP BINP CC 0 1 0 Table 2 Input Sampled Flags CC[1:0] OVRNG indicates that the current output data was produced by an input signal that exceeded the input range limit of the device. 1 = out of range, 0 = within range. WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 13 WM8190 CONTROL INTERFACE Advanced Information The internal control registers are programmable via the serial digital control interface. The register contents can be read back via the serial interface on pin OP[7]/SDO. SERIAL INTERFACE: REGISTER WRITE Figure 13 shows register writing in serial mode. Three pins, SCK, SDI and SEN are used. A six-bit address (a5, 0, a3, a2, a1, a0) is clocked in through SDI, MSB first, followed by an eight-bit data word (b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Each bit is latched on the rising edge of SCK. When the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the appropriate internal register. Note all valid registers have address bit a4 equal to 0 in write mode. SCK SDI a5 0 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 Address SEN Data Word Figure 13 Serial Interface Register Write SERIAL INTERFACE: REGISTER READ-BACK Figure 14 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. Writing address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of corresponding register (a5, 0, a3, a2, a1, a0) to be output MSB first on pin SDO (on the falling edge of SCK). Note that pin SDO is shared with an output pin, OP[7], therefore OEB should always be held low when register read-back data is expected on this pin. The next word may be read in to SDI while the previous word is still being output on SDO. SCK SDI a5 1 a3 a2 a1 a0 x x x x x x x x Address SEN SDO/ OP[7] OEB Data Word d7 d6 d5 d4 d3 d2 d1 d0 Output Data Word Figure 14 Serial Interface Register Read-back TIMING REQUIREMENTS To use this device a master clock (MCLK) of up to 12MHz and a per-pixel synchronisation clock (VSMP) of up to 6MHz are required. These clocks drive a timing control block, which produces internal signals to control the sampling of the video signal. MCLK to VSMP ratios and maximum sample rates for the various modes are shown in Table 5. WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 14 Advanced Information WM8190 PROGRAMMABLE VSMP DETECT CIRCUIT The VSMP input is used to determine the sampling point and frequency of the WM8190. Under normal operation a pulse of 1 MCLK period should be applied to VSMP at the desired sampling frequency (as shown in the Operating Mode Timing Diagrams) and the input sample will be taken on the first rising MCLK edge after VSMP has gone low. However, in certain applications such a signal may not be readily available. The programmable VSMP detect circuit in the WM8190 allows the sampling point to be derived from any signal of the correct frequency, such as a CCD shift register clock, when applied to the VSMP pin. When enabled, by setting the VSMPDET control bit, the circuit detects either a rising or falling edge (determined by POSNNEG control bit) on the VSMP input pin and generates an internal VSMP pulse. This pulse can optionally be delayed by a number of MCLK periods, specified by the VDEL[2:0] bits. Figure 15 shows the internal VSMP pulses that can be generated by this circuit for a typical clock input signal. The internal VSMP pulse is then applied to the timing control block in place of the normal VSMP pulse provided from the input pin. The sampling point then occurs on the first rising MCLK edge after this internal VSMP pulse, as shown in the Operating Mode Timing Diagrams. MCLK INPUT PINS VSMP POSNNEG = 1 (VDEL = 000) INTVSMP (VDEL = 001) INTVSMP (VDEL = 010) INTVSMP (VDEL = 011) INTVSMP (VDEL = 100) INTVSMP (VDEL = 101) INTVSMP (VDEL = 110) INTVSMP (VDEL = 111) INTVSMP POSNNEG = 0 (VDEL = 000) INTVSMP (VDEL = 001) INTVSMP (VDEL = 010) INTVSMP (VDEL = 011) INTVSMP (VDEL = 100) INTVSMP (VDEL = 101) INTVSMP (VDEL = 110) INTVSMP (VDEL = 111) INTVSMP Figure 15 Internal VSMP Pulses Generated by Programmable VSMP Detect Circuit REFERENCES The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin VRLC/VBIAS POWER SUPPLY The WM8190 can run from a 5V single supply or from split 5V (core) and 3.3V (digital interface) supplies. POWER MANAGEMENT Power management for the device is performed via the Control Interface. The device can be powered on or off completely by the EN bit. Alternatively, when control bit SELPD is high, only blocks selected by further control bits (SELDIS[3:0]) are powered down. This allows the user to optimise power dissipation in certain modes, or to define an intermediate standby mode to allow a quicker recovery into a fully active state. In Line-by-line operation, the green and blue channel PGAs are automatically powered down. All the internal registers maintain their previously programmed value in power down modes and the Control Interface inputs remain active. Table 3 summarises the power down control bit functions. WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 15 WM8190 EN 0 1 X SELDPD 0 0 1 Device completely powers down. Device completely powers up. Advanced Information Blocks with respective SELDIS[3:0] bit high are disabled. Table 3 Power Down Control LINE-BY-LINE OPERATION Certain linear sensors (e.g. Contact Image Sensors) give colour output on a line-by-line basis. i.e. a full line of red pixels followed by a line of green pixels followed by a line of blue pixels. In order to accommodate this type of signal the WM8190 can be set into Monochrome mode, with the input channel switched by writing to control bits CHAN[1:0] between every line. Alternatively, the WM8190 can be placed into colour line-by-line mode by setting the LINEBYLINE control bit. When this bit is set the green and blue processing channels are powered down and the device is forced internally to only operate in MONO mode (because only one colour is sampled at a time) through the red channel. Figure 16 shows the signal path when operating in colour line-by-line mode. VRLC/VBIAS VSMP MCLK CL RS V S TIMING CONTROL R G B 8 WM8190 OFFSET DAC + PGA 8 OFFSET MUX RINP RLC INPUT MUX CDS R G B + I/P SIGNAL POLARITY ADJUST 14BIT ADC DATA I/O PORT OP[7:0] GINP RLC PGA MUX BINP RLC CONFIGURABLE SERIAL CONTROL INTERFACE RLC DAC 4 SEN SCK SDI RLC/ACYC Figure 16 Signal Path When in Line-by-Line Mode In this mode the input multiplexer and (optionally) the PGA/Offset register multiplexers can be autocycled by the application of pulses to the RLC/ACYC input pin by setting the ACYCNRLC register bit. The multiplexers change on the first MCLK rising edge after RLC/ACYC is taken high. Alternatively, all three multiplexers can be controlled via the serial interface by writing to register bits INTM[1:0] to select the desired colour. It is also possible for the input multiplexer to be controlled separately from the PGA and Offset multiplexers. Table 4 describes all the multiplexer selection modes that are possible. FME 0 0 1 ACYCNRLC 0 1 0 NAME Internal, no force mux Auto-cycling, no force mux Internal, force mux Auto-cycling, force mux DESCRIPTION Input mux, offset and gain registers determined by internal register bits INTM1, INTM0. Input mux, offset and gain registers auto-cycled, RINP GINP BINP RINP... on RLC/ACYC pulse. Input mux selected from internal register bits FM1, FM0; Offset and gain registers selected from internal register bits INTM1, INTM0. Input mux selected from internal register bits FM1, FM0; Offset and gain registers auto-cycled, RINP GINP BINP RINP... on RLC/ACYC pulse. 1 1 Table 4 Colour Selection Description in Line-by-Line Mode WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 16 Advanced Information WM8190 OPERATING MODES Table 5 summarises the most commonly used modes, the clock waveforms required and the register contents required for CDS and non-CDS operation. MODE DESCRIPTION CDS AVAILABLE MAX SAMPLE RATE 2MSPS SENSOR INTERFACE DESCRIPTION The 3 input channels are sampled in parallel. The signal is then gain and offset adjusted before being multiplexed into a single data stream and converted by the ADC, giving an output data rate of 6MSPS max. As mode 1 except: Only one input channel at a time is continuously sampled. Identical to mode 2 TIMING REQUIREMENTS MCLK max = 12MHz MCLK: VSMP ratio is 6:1 REGISTER CONTENTS WITH CDS SetReg1: 03(hex) REGISTER CONTENTS WITHOUT CDS SetReg1: 01(hex) 1 Colour Pixel-by-Pixel Yes 2 Monochrome/ Colour Line-by-Line Yes 2MSPS MCLK max = 12MHz MCLK: VSMP ratio is 6:1 MCLK max = 12MHz MCLK: VSMP ratio is 3:1 MCLK max = 12MHz MCLK: VSMP ratio is 2:1 MCLK max = 12MHz MCLK: VSMP ratio is 2n:1, n 4 MCLK max = 12MHz MCLK: VSMP ratio is 2n:1, n 4 SetReg1: 07(hex) SetReg1: 05(hex) 3 Fast Monochrome/ Colour Line-by-Line Yes 4MSPS Identical to mode 2 plus SetReg3: bits 5:4 must be set to 0(hex) CDS not possible Identical to mode 2 4 Maximum speed Monochrome/ Colour Line-by-Line Slow Colour Pixel-by-Pixel No 6MSPS Identical to mode 2 SetReg1: 45(hex) 5 Yes 1.5MSPS Identical to mode 1 Identical to mode 1 Identical to mode 1 6 Slow Monochrome/ Colour Line-by-Line Yes 1.5MSPS Identical to mode 2 Identical to mode 2 Identical to mode 2 Table 5 WM8190 Operating Modes Notes: 1. 2. In Monochrome mode, SetReg3 bits 7:6 determine which input is to be sampled. For Colour Line-by-Line, set control bit LINEBYLINE. For input selection, refer to Table 4, Colour Selection Description in Line-by-Line Mode. WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 17 WM8190 OPERATING MODE TIMING DIAGRAMS Advanced Information The following diagrams show 8+6/7+7 multiplexed output data and MCLK, VSMP and input video requirements for operation of the most commonly used modes as shown in Table 5. The diagrams are identical for both CDS and non-CDS operation. Outputs from RINP, GINP and BINP are shown as R, G and B respectively. X denotes invalid data. 16.5 MCLK PERIODS MCLK VSMP INPUT VIDEO OP[7:0] (DEL = 00) OP[7:0] (DEL = 01) OP[7:0] (DEL = 10) OP[7:0] (DEL = 11) RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GA GB BA BB RA RB RA RB GA GB BA BB RA RB GA GB BA BB RA RB GB GA BA BB RA RB GA GB BA BB RA RB GA GB BA BB Figure 17 Mode 1 Operation 16.5 MCLK PERIODS MCLK VSMP INPUT VIDEO OP[7:0] (DEL = 00) OP[7:0] (DEL = 01) OP[7:0] (DEL = 10) OP[7:0] (DEL = 11) RA RB X X X X RA RB X X X X RA RB X X X X RA RB X X X X RA RB X X RA RB X X X X RA RB X X X X RA RB X X X X RA RB X X X X X X X X RA RB X X X X RA RB X X X X RA RB X X X X RA RB X X RA RB X X X X RA RB X X X X RA RB X X X X RA RB X X X X RA RB Figure 18 Mode 2 Operation WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 18 Advanced Information WM8190 23.5 MCLK PERIODS MCLK VSMP INPUT VIDEO OP[7:0] (DEL = 00) OP[7:0] (DEL = 01) OP[7:0] (DEL = 10) OP[7:0] (DEL = 11) RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB Figure 19 Mode 3 Operation 16.5 MCLK PERIODS MCLK VSMP INPUT VIDEO OP[7:0] (DEL = 00) OP[7:0] (DEL = 01) OP[7:0] (DEL = 10) OP[7:0] (DEL = 11) RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB RA RB Figure 20 Mode 4 Operation WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 19 WM8190 16.5 MCLK PERIODS Advanced Information MCLK VSMP INPUT VIDEO OP[7:0] (DEL = 00) OP[7:0] (DEL = 01) OP[7:0] (DEL = 10) OP[7:0] (DEL = 11) X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB BA BB X X RA RB GA GB BA BB Figure 21 Mode 5 Operation (MCLK:VSMP Ratio = 8:1) 16.5 MCLK PERIODS MCLK VSMP INPUT VIDEO OP[7:0] (DEL = 00) OP[7:0] (DEL = 01) OP[7:0] (DEL = 10) OP[7:0] (DEL = 11) X X RA RB X X X X X X RA RB X X X X X X RA RB X X X X X X X X X X RA RB X X X X X X RA RB X X X X X X RA RB X X X X X X X X X X RA RB X X X X X X RA RB X X X X X X RA RB X X RA RB X X X X X X RA RB X X X X X X RA RB X X X X X X RA RB Figure 22 Mode 6 Operation (MCLK:VSMP Ratio = 8:1) WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 20 Advanced Information WM8190 DEVICE CONFIGURATION REGISTER MAP The following table describes the location of each control bit used to determine the operation of the WM8190. The register map is programmed by writing the required codes to the appropriate addresses via the serial interface. ADDRESS Table 6 Register Map REGISTER MAP DESCRIPTION The following table describes the function of each of the control bits shown in Table 7. REGISTER Setup Register 1 BIT NO 0 1 2 3 5:4 BIT NAME(S) EN CDS MONO SELPD PGAFS[1:0] DEFAULT 1 1 0 0 00 DESCRIPTION Global power down: 0 = complete power down, 1 = fully active. Select correlated double sampling mode: 0 = single ended mode, 1 = CDS mode. Mono/colour select: 0 = colour, 1 = monochrome operation. Selective power down: 0 = no individual control, 1 = individual blocks can be disabled (controlled by SELDIS[3:0]). Offsets PGA output to optimise the ADC range for different polarity sensor output signals. Zero differential PGA input signal gives: 00 = Zero output (use for bipolar video) 01 = Zero output 6 MODE4 0 10 = Full-scale positive output (use for negative going video) 11 = Full-scale negative output (use for positive going video) Required when operating in MODE4: 0 = other modes, 1 = MODE4. WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 21 WM8190 REGISTER Setup Register 2 BIT NO 1:0 BIT NAME(S) MUXOP[1:0] DEFAULT 00 DESCRIPTION Determines the output data format. 00 = 8-bit multiplexed (8+6 bits) 01 = 8-bit multiplexed (8+6 bits) 2 INVOP 0 Advanced Information 10 = 7-bit multiplexed mode (7+7 bits) 11 = 4-bit multiplexed mode (4+4+4+2 bits) Digitally inverts the polarity of output data. 0 = negative going video gives negative going output, 1 = negative-going video gives positive going output data. When set powers down the RLCDAC, changing its output to Hi-Z, allowing VRLC/VBIAS to be externally driven. Sets the output range of the RLCDAC. 0 = RLCDAC ranges from 0 to AVDD (approximately), 1 = RLCDAC ranges from 0 to VRT (approximately). Sets the output latency in ADC clock periods. 1 ADC clock period = 2 MCLK periods except in Mode 3 where 1 ADC clock period = 3 MCLK periods. 00 = Minimum latency 01 = Delay by one ADC clock period 10 = Delay by two ADC clock periods 11 = Delay by three ADC clock periods 3 5 VRLCEXT RLCDACRNG 0 1 7:6 DEL[1:0] 00 Setup Register 3 3:0 RLCV[3:0] 1111 Controls RLCDAC driving VRLC pin to define single ended signal reference voltage or Reset Level Clamp voltage. See Electrical Characteristics section for ranges. CDS mode reset timing adjust. 00 = Advance 1 MCLK period 01 = Normal 10 = Retard 1 MCLK period 11 = Retard 2 MCLK periods 10 = Blue channel select 11 = Reserved 5:4 CDSREF[1:0] 01 7:6 CHAN[1:0] 00 Monochrome mode channel select. 00 = Red channel select 01 = Green channel select Software Reset Auto-cycle Reset Any write to Software Reset causes all cells to be reset. Any write to Auto-cycle Reset causes the auto-cycle counter to reset to RINP. WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 22 Advanced Information REGISTER Setup Register 4 BIT NO 0 BIT NAME(S) LINEBYLINE DEFAULT 0 DESCRIPTION WM8190 Selects line by line operation 0 = normal operation, 1 = line by line operation. When line by line operation is selected MONO is forced to 1 and CHAN[1:0] to 00 internally, ensuring that the correct internal timing signals are produced. Green and Blue PGAs are also disabled to save power. When LINEBYLINE = 0 this bit has no effect. When LINEBYLINE = 1 this bit determines the function of the RLC/ACYC input pin and the input multiplexer and offset/gain register controls. 0 = RLC/ACYC pin enabled for Reset Level Clamp. Internal selection of input and gain/offset multiplexers, 1 = Auto-cycling enabled by pulsing the RLC/ACYC input pin. See Table 4, Colour Selection Description in Line-by-Line Mode for colour selection mode details. When auto-cycling is enabled, the RLC/ACYC pin cannot be used for reset level clamping. The RLCINT bit may be used instead. When LINEBYLINE = 0 this bit has no effect. When LINEBYLINE = 1 this bit controls the input force mux mode: 0 = No force mux, 1 = Force mux mode. Forces the input mux to be selected by FM[1:0] separately from gain and offset multiplexers. See Table 4 for details. When LINEBYLINE = 1 and ACYCNRLC = 1 this bit is used to determine whether Reset Level Clamping is used. 0 = RLC disabled, 1 = RLC enabled. Colour selection bits used in internal modes. 00 = Red, 01 = Green, 10 = Blue and 11 = Reserved. See Table 4 for details. Colour selection bits used in input force mux modes. 00 = Red, 01 = Green, 10 = Blue and 11 = Reserved. See Table 4 for details. 0 = Normal operation, signal on VSMP input pin is applied directly to Timing Control block. 1 = Programmable VSMP detect circuit is enabled. An internal synchronisation pulse is generated from signal applied to VSMP input pin and is applied to Timing Control block. When VSMPDET = 0 these bits have no effect. When VSMPDET = 1 these bits set a programmable delay from the detected edge of the signal applied to the VSMP pin. The internally generated pulse is delayed by VDEL MCLK periods from the detected edge. See Figure 15, Internal VSMP Pulses Generated for details. When VSMPDET = 0 this bit has no effect. When VSMPDET = 1 this bit controls whether positive or negative edges are detected: 0 = Negative edge on VSMP pin is detected and used to generate internal timing pulse. 1 = Positive edge on VSMP pin is detected and used to generate internal timing pulse. See Figure 15 for further details. Selective power disable register - activated when SELPD = 1. Each bit disables respective cell when 1, enabled when 0. SELDIS[0] = Red CDS, PGA SELDIS[1] = Green CDS, PGA SELDIS[2] = Blue CDS, PGA SELDIS[3] = ADC 1 ACYCNRLC 0 2 FME 0 3 RLCINT 0 5:4 INTM[1:0] 00 7:6 FM[1:0] 00 Setup Register 5 0 VSMPDET 0 3:1 VDEL[2:0] 000 4 POSNNEG 0 Setup Register 6 3:0 SELDIS[3:0] 0000 Table 7 Register Control Bits WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 23 WM8190 RECOMMENDED EXTERNAL COMPONENTS DVDD 3 10 C1 C2 AVDD 21 C3 AGND2 DGND AGND AGND 1 VRT RINP VRX GINP VRB BINP 24 25 23 C6 C7 C8 C4 C5 AVDD AGND1 22 2 DVDD1 DVDD2 DGND 8 Advanced Information Video Inputs 28 27 26 C9 VRLC/VBIAS AGND WM8190 AGND OP[7]/SDO 7 MCLK VSMP RLC/ACYC OP[6] OP[5] OP[4] OP[3] 12 11 SCK SDI SEN OP[2] OP[1] OP[0] 20 19 18 17 16 15 14 13 DVDD + C10 + C11 AVDD + C12 Timing Signals 5 6 Output Data Bus DGND AGND Interface Controls 9 4 OEB N O T E S : 1. C1-9 should be fitted as close to WM8190 as possible. 2. AGND and DGND should be connected as close to WM8190 as possible. 3. DVDD should be connected as close to WM8190 as possible. Figure 23 External Components Diagram COMPONENT REFERENCE C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 SUGGESTED VALUE 100nF 100nF 100nF 10nF 1F 100nF 100nF 100nF 100nF 10F 10F 10F DESCRIPTION De-coupling for DVDD1. De-coupling for DVDD2. De-coupling for AVDD. High frequency de-coupling between VRT and VRB. Low frequency de-coupling between VRT and VRB (non-polarised). De-coupling for VRB. De-coupling for VRX. De-coupling for VRT. De-coupling for VRLC. Reservoir capacitor for DVDD. Reservoir capacitor for DVDD. Reservoir capacitor for AVDD. Table 8 External Components Descriptions WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 24 Advanced Information WM8190 PACKAGE DIMENSIONS D: 28 PIN SOICW 7.5mm (0.3") Wide Body, 1.27mm Lead Pitch DM016.B e B 28 15 ZONE A E H L ZONE B h x 45 o 1 14 D C A1 -CSEATING PLANE A 0.10 (0.004) Symbols A A1 B C D e E h H L REF: Dimensions (mm) MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 17.70 18.10 1.27 BSC 7.40 7.60 0.25 0.75 10.00 10.65 0.40 1.27 o o 8 0 Dimensions (Inches) MIN MAX 0.0926 0.1043 0.0040 0.0118 0.0130 0.0200 0.0091 0.0125 0.6969 0.7125 0.0500 BSC 0.2914 0.2992 0.0100 0.0290 0.3940 0.4190 0.0160 0.0500 o o 0 8 JEDEC.95, MS-013 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS (INCHES). B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM (0.010IN). D. MEETS JEDEC.95 MS-013, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. E. PIN ONE INDICATORS WILL BE LOCATED IN EITHER ZONE A OR ZONE B. WOLFSON MICROELECTRONICS LTD AI Rev 3.0 August 1999 25 |
Price & Availability of WM8190
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |