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| VT83205 3.3V Low Phase Noise VCXO (Voltage-Controlled Crystal Oscillator) and PLL Clock Synthesizer Applications *= *= Telecom switching Set-top boxes *= *= HDTV MPEG Video clock source General Description The Vaishali VT83205 is a single-chip, integrated VCXO and Phase Locked Loop (PLL) clock synthesizer. The device uses the VCXO and an analog Phase-Locked Loop (PLL) to accept a 10 MHz to 14.318 MHz, 30pF (pull range of 200 ppm) crystal input, in order to produce either one or two output clocks. A 0 to 3V control signal is used to fine tune the output clock frequency in the 100ppm range. Select inputs SO:S2 are used for frequency and output selection. Features *= *= *= *= 3.3V supply operation Packaged in 16-pin SOIC & QSOP packages. Replaces separate VCXO and multiplier Uses inexpensive pullable crystal *= *= *= On-chip VCXO with 200 ppm pull range (100 ppm) 5V-tolerant control inputs Zero ppm synthesis error in both clocks Figure 1. Functional Block Diagram VDD1 VDD2 VIN X2 Load Cap Control Output Buffer osc Low Phase Noise PLL Output Buffer X1 S2:S0 OE CLK2 CLK1 10-14 MHz Pullable Crystal Load Caps 2001-03-08 Vaishali Semiconductor Page 1 www.vaishali.com 1300 White Oaks Road, Ste. 200 Campbell MDST-0001-01 CA 95008 Ph. 408.377.6060 Fax 408.377.6063 VT83205 Figure 2. Pin Configuration VT83205 Pinout X1 VDD1 VDD1 VIN GND GND S2 OE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X2 NC S1 GND CLK2 VDD2 S0 CLK1 Table 1. Pin Description Name X1 VDD1 VIN GND S2 OE CLK1 SO VDD2 CLK2 S1 NC X2 1 2,3 4 5,6,13 7 8 9 10 11 12 14 15 16 Pin # Type XI P I P I I O I P O I XO Core VDD. Connect to 3.3V Description Crystal connection. Connect to a pullable crystal of 10-14.318 MHz Voltage input to VCXO. Zero to 3V signal controls the frequency of the VCXO. Connect to ground. Select input #2. Selects outputs per Table 2 Active HIGH Output enable . Outputs in Hi-Z state when LOW Clock output #1 per Table 2. Select input #0. Selects output per Table 2 Output VDD. Connect to 3.3V Clock output #2 per Table 2 Select input #1. Selects outputs per Table 2 There is no internal connection to this pin. Crystal connection. Connect to a pullable crystal of 10 MHz - 14.318 MHz. Legend: I = Input O = Output P = Power supply connection XI, XO = Crystal connections. Table 2. Pullable Crystal Specifications Parameter Correlation (load) capacitance C0/C1 ESR Operating Temperature Initial Accuracy Temperature + Aging Stability 2001-03-08 Vaishali Semiconductor Page 2 www.vaishali.com 1300 White Oaks Road, Ste 200 Campbell Value 30 pF 240 max 35 max 0C to +70C 20 ppm 50 ppm MDST-0001-01 CA 95008 Ph. 408.377.6060 Fax 408.377.6063 VT83205 Table 3 Clock Selection Table (OE = High) S2 0 0 0 0 0 0 1 1 1 1 1 1 Note: 1. S1 0 0 0 1 1 1 0 0 0 1 1 1 S0 0 M (1) CLK1 REF/4 OFF OFF OFF OFF OFF Test OFF OFF OFF OFF OFF CLK2 REF/2 X 0.666 X 2.6666 X4 X 1.5 X 1.3333 Test X4 X2 X3 X5 X6 1 0 M (1) 1 0 M (1) 1 0 M (1) 1 SO has three valid states: 0 = VIN 0.5V 1 = VIN VDD - 0.5 M = 0.5V < VIN < VDD - 0.5V Table 4 Absolute Maximum Ratings Parameter Supply voltage, VDD Inputs and Clock Outputs Soldering Temperature Storage temperature Conditions Referenced to GND Referenced to GND Max of 10 seconds Min -0.5 Typ Max 5 VDD+0.5 260 Units V V C C -65 150 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 5 Operating Conditions Parameter Operating Voltage, VDD Input High Voltage, VIH, X1 pin only Input Low Voltage, VIL, X1 pin only Input High Voltage, VIH, binary inputs Input Low Voltage, VIL, binary inputs Input High Voltage, VIH, trinary input Input Low Voltage, VIL, trinary input Operating Temperature VCXO control voltage, VIN S2, S1, OE S2, S1, OE S0 S0 0 0 VDD-0.5 0.5 70 3 2 0.8 Conditions Min 3.15 2.5 Typ 3.3 Max 3.45 Units V V 0.4 V V V V V C V 2001-03-08 Vaishali Semiconductor Page 3 www.vaishali.com 1300 White Oaks Road, Ste 200 Campbell MDST-0001-01 CA 95008 Ph. 408.377.6060 Fax 408.377.6063 VT83205 Table 6. DC Electrical Characteristics TA = 0C to +70C, VDD = 3.15 V to 3.45 V Parameter Output High Voltage, VOH Output Low Voltage, VOL Operating Supply Current, IDD Short Circuit Current Input Capacitance Note: 1. Typical values are at VDD = 3.3V and 25C Condition IOH=-25mA IOL=25mA No Load Each output S2:0, OE Min 2.4 Typ (1) Max 0.4 Units V V mA mA pF 38 85 7 Table 7. AC Electrical Characteristics TA = 0C to +70C, VDD = 3.15 V to 3.45 V Symbol Fosc Tr tf tod tpZL, tpZH tpLZ, tpHZ tjit (pk-pk) Parameter Input Crystal Frequency Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle Enable Time. OE to CLK Disable Time. OE to CLK Maximum Absolute Jitter (Peak to Peak) Phase Noise, relative to carrier Output pullability Condition 0.8 to 2.0V 2.0 to 0.8V At VDD/2 CL = 50pf CL = 50pf Min 10 Typ Max 14.318 1.5 1.5 Units MHz ns ns % ns ns ps dBc/Hz ppm 40 5 4 100 60 6.5 5.5 10 KHz offset 0V Note: 1. Typical values are at VDD = 3.3V and 25C Figure 3. External Crystal Connection Block Diagram 10-14MHz Pullable Crystal X2 X2 XTAL OSC XTAL OSC X1 X1 PLL PLL CLOCK CLOCK GEN Clk 1 Clk 2 20pF 33pF (CX2) CX2 20pF 33pF CX1 CX1 External Crystal External Load Capacitors GEN OE OE Crystal Ordering Information Part Number VT83205Q VT83205QX VT83205S1 VT83205S1X VT83205/D Marking VT83205Q VT83205Q VT83205S1 VT83205S1 Shipping/Packaging Tubes Tape & Reel Tubes Tape & Reel Die No. of Pins 16 16 16 16 Package QSOP QSOP SOIC SOIC Temperature 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 2001-03-08 Vaishali Semiconductor Page 4 www.vaishali.com 1300 White Oaks Road, Ste 200 Campbell MDST-0001-01 CA 95008 Ph. 408.377.6060 Fax 408.377.6063 |
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