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VV5404 & VV6404
(R)
Mono and Colour Digital Video CMOS Image Sensors
DESCRIPTION
VV5404 and VV6404 are highly integrated CMOS VLSI sensors which enables high standards of performance and image quality at a very cost-effective price point. The 356 x 292 monochrome device offers one of the simplest routes currently available to design-in of imaging applications, while the colour device is ideal for low cost PC camera applications. Both devices incorporate a comprehensive range of on-board controls eliminating the need for additional support chips. Onchip A/D conversion provides 8 bit digital output and the device set up is fully automatic via the built-in automatic black level calibration algorithm. Exposure and gain settings are programmable and operation is controlled via a serial interface. This sensors offer variable frame rates of up to 30 frames per second and a 4 wire digital video bus. The digital interface also provides a tri-stateable data qualification clock and frame synchronisation signal. Hand-held products, in applications such as PDAs, bar code scanning or automatic meter reading, will benefit from the low power requirements and from the inbuilt sleep and power down modes. The price and performance standards introduced with the VV5404 and VV6404 enable use of an imaging solution where previously it may not have been practicable on cost grounds.
FEATURES
* * * * * * * * * * * CIF Format mono or colour pixel array Up to 30 frames per second operation On-chip 8 bit analogue to digital converter Low power consumption Up to 356 x 292 pixel image size Automatic exposure and gain control Serial interface control Programmable exposure and gain values Automatic black level calibration 4-wire digital video bus Evaluation kit available
APPLICATIONS
* * * PC Cameras Biometrics Inspection Systems
SPECIFICATIONS
Pixel resolution Array size Pixel size Min. illumination Exposure control Gain control Signal/Noise ratio 356 x 292 (CIF) 4.272mm x 3.212mm 12.0 m x 11.0 m 0.1 lux Automatic (to 25000:1) Automatic (to +20dB) 46dB 5.0v DC +/- 5% <75mA 0oC - 40oC
(for extended temp. info please contact STMicroelectronics)
BLOCK DIAGRAM
C LKI C LK O S IN
BLACK CALIBRATION
IMAGE FORMAT
EXPOSURE REGISTERS
SERIAL INTERFACE
Supply voltage
SD A SC L
Supply current Operating temperature (ambient) Package type
VERTICAL SHIFT REGISTER
PHOTO DIODE ARRAY
OUTPUT FORMAT
D[3:0] QCK FS T OEB
48LCC
8-bit ADC SAMPLE & HOLD ANALOG VOLTAGE REFS. HORIZONTAL SHIFT REGISTER GAIN STAGE
Important:
1. A colour co-processor is required to convert the VV6404 sensor's video data stream of raw colourised pixel data into either a CIF or QCIF format RGB or YUV colour image. VV5404 and VV6404 do NOT have any form of automatic exposure control. This must be performed externally.
2.
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Table of Contents
1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Image Read-out Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Frame Rate Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. Exposure Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4. Digital Video Interface Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 General description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 Embedded control data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4.2.1 The combined escape and sync character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2.2 The command word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2.3 Supplementary Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.3 Video timing reference and status/configuration data. . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3.1 Blank lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3.2 Black line timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3.3 Valid video line timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3.4 Start of frame line timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3.5 End of frame line timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.4 Detection of sensor using data bus state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.5 Resetting the Sensor Via the Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 Power-up, Low-power and Sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.6.1 Power-Up/Down (Figure 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.6.2 Low-Power Mode (Figure 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.6.3 Sleep Mode (Figure 11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.6.4 Application of the system clock during sensor low-power modes . . . . . . . . . . . . . . . 22 4.7 Qualification of Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.7.1 Using the External Clock signal applied to CKI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.7.2 Data Qualification Clock, QCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4.7.3 Frame Start Signal, FST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5. Serial Control Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 Serial Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 5.3 Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4 Message Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 5.5 The Programmers Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.5.1 DeviceH [000_00002] and DeviceL [000_ 00012] . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.5.2 Status0 [000_00102] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 5.5.3 Line_count_H [000_00112] & Line_count_L [000_01002]. . . . . . . . . . . . . . . . . . . . . 31 5.5.4 Setup0 [001_00002] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 5.5.5 Setup1 [001_00012] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 5.5.6 Setup2 [001_00102] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 5.5.7 Setup4 [001_01002] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 5.5.8 Setup5 [001_01012] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 5.5.9 Exposure Control Registers [010_00002] - [010_10012]. . . . . . . . . . . . . . . . . . . . . . 35 5.5.10 ADC Setup Register AS0 [111_01112] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.6 Types of messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.6.1 Single location, single data write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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5.6.2 Single location, single data read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 5.6.3 No data write followed by same location read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.6.4 Same location multiple data write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.6.5 Same location multiple data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.6.6 Multiple location write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.6.7 Multiple location read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 5.7 Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 6. Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.8 Synchronising 2 or More Cameras . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 7. Detailed specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 7.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 7.2 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8. Physical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 8.1 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.2 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 8.3 48LCC Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 8.4 VV6404 Sensor Support Circuit Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.5 Sensor Support Circuit Component List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 9. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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1. Introduction VV5404 and VV6404 are CIF format CMOS image sensors capable of outputing digital pixel data at frame rates, of upto 30 frames per second. The VV5404 is a monochrome part, while the VV6404 has a colour filter applied over the sensor array. Important: The VV6404 sensor's video data stream only contains raw colourised pixel data. A colour co-processor is required to generate for example either a CIF or a QCIF format YUV colour image. The 356 x 292 pixel sensors have an on-chip 8-bit analogue to digital converter (Figure 1). The sensors offer very flexible digital interface, the main components of which are listed below: 1. A tri-stateable 4-wire data bus (D[3:0]) for sending both video data and embedded timing references. 2. A data qualification clock, QCK, which can be programmable via the serial interface to behave in a number of different ways (Tri-stateable). 3. A frame start signal, FST (Tri-stateable). 4. A 2-wire serial interface (SDA,SCL) for controlling and setting up the device. 5. The ability to synchronise the operation of multiple cameras - synchronisation input, SIN. An 8-bit pixel value is transmitted across the 4 wire tri-stateable databus as series pair of 4-bit nibbles, most significant nibble first. Along within the pixel data, codes representing the start and end frames and the start and end of lines are embedded within the video data stream to allow the video processor to synchronise with video data the camera module is generating. Section 4. defines the format for the output video datastream.
CLKI CLKO SIN
BLACK CALIBRATION
IMAGE FORMAT
EXPOSURE REGISTERS
SERIAL INTERFACE
SDA SCL
VERTICAL SHIFT REGISTER
PHOTO DIODE ARRAY
OUTPUT FORMAT
D[3:0] QCK FST OEB
8-bit ADC SAMPLE & HOLD ANALOG VOLTAGE REFS. HORIZONTAL SHIFT REGISTER GAIN STAGE
Figure 1 : Block Diagram of VV5404 and VV6404 Image Sensors
To complement the embedded control sequences a data qualification clock, QCK, and a frame start signal are also available. QCK can be set-up to either be: 1. Disabled 2. Free-running. 3. Qualify only the control sequences and the pixel data. 4. Qualify the pixel data only There is also the choice of two different QCK frequencies, where one is twice the frequency of the other.
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1. Fast QCK: the falling edge of the clock qualifies the nibble data irrespective of whether it is the most or the least significant nibble. 2. Slow QCK: the rising edge of the clock qualifies the most significant nibbles while the falling edge of the clock qualifies the least significant nibbles. The FST can be enabled/disabled via the serial interface. OEB tri-states all 4 databus lines, D[3:0], the qualification clock, QCK and the frame start signal, FST. There are 3 main ways of interfacing to the VV5404 or VV6404 sensor based on the above signals: 1. The processor capturing the data (or colour co-processor for VV6404) supplies the sensor clock, CKI, and uses the embedded control sequences to synchronise with the frame and line level timings. Thus the processor and sensor are running off derivatives of the same fundamental clock (4 fsc - 14.31818 MHz). To allow the receiver to determine the best sampling position of the video data, during its power-up sequence the sensor outputs a 101010... sequence on each of its databus lines for the video processor to lock on to. 2. The video processor uses a free-running QCK supplied by the sensor to sample the incoming video data stream. The embedded control sequences are used to synchronise the frame and line level timings. A crystal is used to generate the clock for the sensor. 3. The video processor uses FST and the data only mode for QCK to synchronise to the incoming video data. Primarily intended for interfacing to frame grabbers. The 2-wire serial interface provides complete control over how the sensor is setup and run. Exposure and gain values are programmed via this interface. Section 5. defines the communications protocol and the register map of all the locations which can be accessed via the serial interface.
D[3:0] Sensor Colour Co-processor (processor)
CLKI SDA SCL D[3:0]
Sensor
QCK FST SDA SCL
Colour Co-processor (processor)
Figure 2 : Interfacing Options
Using the first two interface options outlined above it is possible to control the sensor and receive video data via a 9wire cable between the sensor and the video processor/colour-processor. 1. A 4-wire data bus (D[3:0]) for sending both video data and embedded timing references. 2. A 2-wire serial interface (SDA,SCL). 3. The clock for the sensor or QCK from the sensor. 4. VCC and GND power lines. The various image read-out and frame rate options are detailed in Sections 2 and 3 respectively.
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2.
Operating Modes
2.1 Image Read-out Options The output image format is CIF (352 x 288 pixel array). To provide the colour co-processor with the extra information it needs for interpolation at the edges of the VV6404 pixel array, an optional border 2 pixels deep on all 4 sides of the array can be enabled (Figure 4). The resulting image size of 356 x 292 pixels is the default power up state for this camera module. The border option is programmable via the serial interface.
Border
Disabled Enabled
Image size (column x row)
352 x 288 356 x 292 Default
Table 1 : Image Format Selection.
Even Columns (0, 2, 4,...) Even Rows (0, 2, 4,...) Odd Rows (1, 3, 5,...) Odd Columns (1, 3, 5,...)
Green
Red
Blue
Green
Figure 3 : Bayer Colourisation Pattern. (VV6404 only)
Image read-out is either non-interlaced raster scan, or `shuffled' non-interlaced raster scan. The shuffled raster scan order differs from a conventional raster in that the pixels of individual rows are re-ordered, with the odd pixels within a row read-out first, followed by the even pixels. This `shuffled' read-out within a line, is useful in the VV6404 device as it groups pixels of the same colour (according to the Bayer pattern - Figure 3) together, reducing cross talk between the colour channels. NOTE: This option is on by default in both VV5404 and VV6404 sensors and is controllable via the serial interface. 2.2 Frame Rate Options Two options: 30 fps or 25 fps (Assuming a 7.15909 MHz input clock and the default clock divider setting). The number of video lines in for each frame rate is the same (304), the slower frame rate is implemented by extending the line period from 393 pixel periods to 471 pixel periods. 30 fps is the default option, the frame rate is programmable via the serial interface.
Frame Rate (fps)
25 30
Frame Timing (Pixels x Lines)
471 x 304 393 x 304 default
Table 2 : Frame Rate Selection
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0 0 1 2 3
Green Blue Green Blue
1
Red Green Red Green
2
Green Blue Green Blue
3
Red
Border Rows and Columns
Green Red
0, 1, 2, 3,...
Green
... 352, 353, 354, 355 352 Pixels
288 Pixels
292 Pixels
0, 1, 2, 3,... ... 288, 289, 290, 291
CD5404-6404F-A
Green
Red Green Red Green
Green Blue Green Blue
Red Green Red Green
288 289 290 291 VV5404 & VV6404
356 Pixels Pixel Array
Blue Green Blue
352
353
354
355
Figure 4 : VV6404 Colourised Image Format
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3. Exposure Control The exposure time for a pixel and the gain of the input amplifier to the 8-bit ADC are programmable via the serial interface. The explanation below assumes that the gain and exposure values are updated together as part of a 5 byte serial interface auto-increment sequence. The exposure is divided into 2 components - coarse and fine. The coarse exposure value sets the number of lines a pixel exposes for, while the fine exposure sets the number of additional pixel clock cycles a pixel integrates for. The sum of the two gives the overall exposure time for the pixel array. 30 fps mode: Exposure Time = (Clock Divisor) x (Coarse x 393 + Fine) x (CKI clock period)/ 25 fps mode: Exposure Time = (Clock Divisor) x (Coarse x 471 + Fine) x (CKI clock period)
30 fps mode Value
Coarse Fine
25 fps mode Min.
0 0
Units Min.
Video Lines Pixel Clocks 0 0
Max.
302 356
Max.
302 434
Table 3 : Coarse and Fine Exposure Ranges.
If an exposure value is loaded outwith the valid ranges listed in the above table the value is clipped to lie within the above ranges.
Gain Code, G[2:0]
0 0 0 1 0 0 1 1 0 1 1 1
Amplifier Gain
1 2 4 8
Table 4 : Main Gain Steps.
Exposure and gain values are re-timed within the sensor to ensure that a new set of values is only applied to the sensor array at the start of each frame. Bit 0 of the Status Register is set high when a new exposure value is written via the serial interface but has not yet been applied to the sensor array. There is a 1 frame latency between a new exposure value being applied to the sensor array and the results of the new exposure value being read-out. The same latency does not exist for the gain value. To ensure that the new exposure and gain values are aligned up correctly the sensor delays the application of the new gain value by one frame relative to the application of the new exposure value. To eliminate the possibility of the sensor array seeing only part of the new exposure and gain setting, if the serial interface communications extends over a frame boundary, the internal re-timing of exposure and gain data is disabled while writing data to any location in the Exposure page of the serial interface register map. Thus if the 5 bytes of exposure and gain data is sent as an auto-increment sequence, it is not possible for the sensor to consume only part of the new exposure and gain data.
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4.
Digital Video Interface Format
4.1 General description The video interface consists of a unidirectional, tri-stateable 4-wire databus. The nibble transmission is synchronised to the rising edge of the system clock (Figure 13). Read-out Order Form of encoding Correspondence between video signal levels and quantisation levels: Progressive Scan (Non-interlaced) Uniformly quantised, PCM, 8 bits per sample Internally valid pixel data is clipped to ensure that 00 H and FFH values do not occur when pixel data is being output on the data bus. This gives 254 possible values for each pixel (1 - 254). The video black level corresponds to code 16.
Table 5 : Video encoding parameters
Digital video data is 8 bits per sample, transmitted as serial pairs of parallel 4-bit nibbles (most significant nibble first) on 4 wires. Multiplexed with the sampled pixel data is control information including both video timing references and sensor status/configuration data. Video timing reference information takes the form of field start characters, line start characters, end of line characters and a line counter. Where hexadecimal values are used, they are indicated by a subscript H, such as FFH; other values are decimal. 4.2 Embedded control data To distinguish the control data from the sampled video data all control data is encapsulated in embedded control sequences. These are a minimum of 6 words long and includes a combined escape/sync character, 1 control word (the `command byte') and 2 words of supplementary data. To minimise the susceptibility of the embedded control data to random bit errors redundant coding techniques have been used to allow single bit errors in the embedded control words to be corrected. However, more serious corruption of control words or the corruption of escape/sync characters cannot be tolerated without loss of sync to the data stream. To ensure that a loss of sync is detected a simple set of rules has been devised. The four exceptions to the rules are outlined below: 1. Data containing a command words that has two bit errors. 2. Data containing two `end of line' codes that are not separated by a `start of line' code. 3. Data preceding an `end of frame' code before a start of frame' code has been received. 4. Data containing line that do not have sequential line numbers (excluding the `end of frame' line). If the video processor detects one of these violations then it should abandon the current frame of video.
4.2.1 The combined escape and sync character
Each embedded control sequence begins with a combined escape and sync character that is made up of three words. The first two of these are FFH FFH- constituting two words that are illegal in normal data. The next word is 00H guaranteeing a clear signal transition that allows a video processor to determine the position of the word boundaries in the serial stream of nibbles. Combined escape and sync characters are always followed by a command word making up the four word minimum embedded control sequence. 4.2.2 The command word
The word that follows the combined escape/sync characters defines the type of embedded control data. Three of the 8 bits are used to carry the control information, four are `parity bits' that allow the video processor to detect and correct a certain level of errors in the transmission of the command words, the remaining bit is always set to 1 to ensure that the command word is never has the value 00H. The coding scheme used allows the correction of single bit errors (in the 8-bit sequence) and the detection of 2 bit errors. The three data bits of the command word are interpreted as shown in Figure 5.
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Line Code
End of Line Blank Line (BL) Black line (BK) Visible Line (VL) Start of Frame (SOF) End of Frame (EOF)
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Nibble XH 1 C2 C1 C0
10002 (8H) 10012 (9H) 10102 (AH) 10112 (BH) 11002 (CH) 11012 (DH) 11102 (EH) 11112 (FH)
Nibble YH P3 P2 P1 P0
00002 (0H) 11012 (DH) 10112 (BH) 01102 (6H) 01112 (7H) 10102 (AH) 11002 (CH) 00012 (1H) Supplementary Data (i) Line Number (L11 MSB) Bit 7 6 5 4 3 2 1 0
0 L11 L10 L9 L8 L7 L6 P Nibble D3 Nibble D2
0 L5 L4 L3 L2 L1 L0 P Nibble D1 Nibble D0
Reserved Reserved 7 Bit 6 5 4 3 2 1
Odd word parity or (ii) If Line Code = End of Line then 1 1 1 1 1 1 1 1
0 Command (Line Code)
1 C2 C1 C0 P3 P2 P1 P0 Nibble XH Nibble YH
Nibble D3 = FH Nibble D2 = FH 1 1 1 1 1 1 1 1
Nibble D1 = FH Nibble D0= FH
4-wire nibble output mode
FH FH FH FH 0H 0H XH YH D3 D2 D1 D0
Escape/Sync Sequence
VV5404 & VV6404
Figure 5 : Embedded Control Sequence
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Frame Format (Border rows and columns enabled - Default) :
Blanking Line
303
Black Lines
Blanking Lines
Image Data
Frame Period (304 Lines) Line Number Line Code
CD5404-6404F-A
303
0
1
2
3
4
9
10
11
12
13
298
299
300
301
302
Start of Frame
0 1 SOF BK
Start of Frame
Start of Image (SOF)
BL SOF BK BK
7 Blank Lines (BL)
BL BL BL VL VL
292 Visible Lines (VL)
VL VL VL VL VL
End of Image (EOF)
VL EOF BL
2 Black Lines (BK)
Frame Format (Border rows and columns disabled)) :
End of Frame
Black Lines
Blanking Lines
Image Data
Blanking Lines
Frame Period (304 Lines) Line Number Line Code
303 0 1 2 3 4 9 10 11 12 13 298 299 300 301 302 303 0 1
Start of Image (SOF)
BL SOF BK BK BL
9 Blank Lines (BL)
BL BL BL BL
288 Visible Lines (VL) End of Image (EOF)
VL VL VL VL EOF BL BL BL SOF BK
2 Black Lines (BK)
Figure 6 : Frame Formats
Start of Frame
Start of Frame
End of Frame
VV5404 & VV6404
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Line Format
Line Period (393 Pixel Periods - 30 fps, 471 Pixel Periods - 25 fps) End of Active Video (EAV) Video Data Escape/Sync Sequence Null Line Code Characters SAV
Start of Active Video (SAV) Escape/Sync Sequence Line Code Line Number
Pixel Number (Shuffled Pixel Data)
1
178 Odd Pixels
3 355
178 Even Pixels
0 352 354
Pixel Number (Unshuffled Pixel Data)
CD5404-6404F-A 0 1
356 Pixels
177 178 354 355
4-wire Nibble Output Mode, D[3:0]
FH 0H 0H XH YH D3 D2 D1 D0 PM PL PM PL PM PL PM PL PM PL PM PL FH FH FH FH 0H 0H 8H 0H FH FH
(i) (ii) (iii) (iv) (v)
Blanking Line (BL) Black Line (BK) Visible Line (VL) Start of Frame (SOF) End of Frame (EOF)
P = Blanking Level (07H) P = Valid Black Pixel Data P = Valid Pixel Data P = Sensor Status Data P = Blanking Level (07H)
PM = Pixel Value - Most Significant Nibble, PL = Pixel Value - Least Significant Nibble, P = 8-bit Pixel Value VV5404 & VV6404
Figure 7 : Line Data Format.
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VV5404 & VV6404
Parity Checks Comment P3
1 1 1 1 0 0 0 1
P2
1 1 1 0 1 0 1 0
P1
1 1 0 1 1 1 0 0
P0
1 0 1 1 1 0 0 0 Code word un-corrupted P0 corrupted, line code OK P1 corrupted, line code OK P2 corrupted, line code OK P3 corrupted, line code OK C0 corrupted, invert sense of C0 C1 corrupted, invert sense of C1 C2 corrupted, invert sense of C2 2-bit error in code word.
All other codes
Table 6 : Detection of 1-bit and 2-bit errors in the Command Word
The even parity bits are based on the following relationships: 1. An even number of ones in the 4-bit sequence (C2, C1, C0 and P0). 2. An even number of ones in the 3-bit sequence (C2, C1, P1). 3. An even number of ones in the 3-bit sequence (C2, C0, P2). 4. An even number of ones in the 3-bit sequence (C1, C0, P3). Table 6 shows how the parity bits maybe used to detect and correct 1-bit errors and detect 2-bit errors. 4.2.3 Supplementary Data
The last 2 bytes of the embedded control sequence contains supplementary data. This normally contains the current line number except if the line code is the end of line, the 2 bytes are padded out using null characters (FFH). The 12 bit line number is packaged up by splitting it into two 6-bit values. Each 6-bit values is then converted into an 8-bit value by adding a zero to the start and an odd word parity bit at the end. 4.3 Video timing reference and status/configuration data The video sequence is made up of lines of data. Each field of data is constructed of the following data lines: 1. A start of frame line 2. 2 of `black lines' (used for black level calibration) 3. 7 (9) of blank lines 4. 292 (288) active video lines 5. An end of frame line 6. 1 (3) blank lines The numbers given in () are for when the border rows and columns are not output on the databus. Each line of data starts with an embedded control sequence that identifies the line type (as outlined in Table 3). The control sequence is then followed by two bytes that, except in the case of the end-of-frame line, contain a coded line number. The line number sequences starts with the start-of-frame line at 00H and increments one per line up until the end-of-frame line. Each line is terminated with an end-of-line embedded control sequence. The line start embedded sequences must be used to recognise data lines as a number of null bytes may be inserted between data lines.
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VV5404 & VV6404
4.3.1 Blank lines
In addition to padding between data lines, actual blank data lines may appear in the positions indicated above. These lines begin with start-of-blank-line embedded control sequences and are constructed identically to active video lines except that they will contain only blank bytes (07H). 4.3.2 Black line timing
The black lines (which are used for black level calibration) are identical in structure to valid video lines except that they begin with a start-of-black line sequence and contain either information from the sensor `black lines' or blank bytes (07H). 4.3.3 Valid video line timing
All valid video data is contained on active video lines. The pixel data appears as a continuous stream of bytes within the active lines. The pixel data may be separated from the line header and end-of-line control sequence by a number of `blank' bytes (07H), e.g. when the border lines and pixels are disabled 07H is output in place of pixels 0, 1, 354 and 355. 4.3.4 Start of frame line timing
The start of frame line which begins each video field contains no video data but instead contains the contents of all the serial interface registers. This information follows the start-of-line header immediately and is terminated by an end-of-line control sequence. To ensure that no escape/sync characters appear in the sensor status/configuration information the code 07H is output after each serial interface value. Thus it takes 256 pixel clock periods (512 system clocks) to output all 128 of the serial interface registers. The remainder of the 356 pixel periods of the video portion of the line is padded out using 07H values. The first two pixel locations are also padded with 07H characters (Figure 8) If a serial interface register location is unused then 07H is output. The read-out order of the registers is independent of whether the pixel read-out order is shuffled or un-shuffled. 4.3.5 End of frame line timing
The end of frame line which begins each video field contains no video data. Its sole purpose is to indicate the end of a frame. 4.4 Detection of sensor using data bus state The video processor device must have internal pull-down terminations on the data bus. On power-up a sensor will pull all data lines high for a guaranteed period. This scheme allows the presence of a sensor on the interface to be detected by the video processor on power-up, and the connection of a sensor to an already power-up interface (a `hot' connection). The absence of a sensor is detected by the video processor seeing more than 32 consecutive nibbles of 0H on the data bus. On detecting the absence of a sensor, CKI, should be disabled (held low). The presence of a sensor is detected by the video processor seeing more than 32 consecutive nibbles of FH on the data bus. On detecting the presence of a sensor, CKI, should be enabled. 4.5 Resetting the Sensor Via the Serial Interface Bit 2 of setup register 0 allows the VV6404 sensor to be reset to its power-on state via the 2-wire serial interface. Setting this "Soft Reset" bit causes all of the serial interface registers including the "Soft Reset" bit to be reset to their default values. This "Soft Reset" leaves the sensor in low-power mode and thus an "Exit Low-Power Mode" command (Section 4.6.2) must be issued via the serial interface before the sensor will start to generate video data (Figure 9). 4.6 Power-up, Low-power and Sleep modes To clarify the state of the interface on power-up and in the case of a `hot' connection of the interface cable the powerup state of the bus is defined below.
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Start of Active Video (SAV)
Serial Interface Register Values Padding Characters
End of Active Video (EAV)
Start of Frame Line Code Output Databus, D[3:0]
FH 0H
CD5404-6404F-A
CH 7H 0H 1H 0H 1H 0H 7H 0H 7H 1H 9H 0H 7H 4H 0H 0H 7H
0H 7H 0H 7H
FH
0H
8H 0H
FH
Line Number 0
DeviceH DeviceL (Register 0) (Register 1)
Figure 8 : Status Line Data Format.
VV5404 & VV6404
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SR2 SR1 SR0
SR5 SR4 SR3
SR7
SR8
SR6
D[3:0]
FH
9H,6H,9H,6H...
FH
One frame of 9H & 6H data.
Start of Frame Line for the 1st frame of valid video data.
Valid Video data.
CLKI SDA SCL
CD5404-6404F-A
setup0[0] setup0[2] Frame Number
SR0-SR1 SR2 SR3-SR4 SR5-SR6 SR7-SR8 N 0 1 2 3 4 5
"Soft-Reset" Command. At the end of the command the sensor is reset and enters low-power mode. The sensor enters low-power mode. "Exit Low Power Mode" Command. Powers-up analogue circuits and initiates the VM6404 sensor's 4-frame start-up sequence 1 Frame of alternating 9H & 6H data on D[3:0] for the video processor to determine the best sampling phase for the nibble data (D[3:0]). 4 Frames after the "Exit Low-Power mode" command, the sensor starts outputing valid video data.
VV5404 & VV6404
Figure 9 : Resetting the VV6404 Sensor via the Serial Interface.
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VV5404 & VV6404
PU0 PU1 PU2 PU3 PU4-PU5
System Power Up or Sensor Hot Plugged Sensor Internal-on Reset Triggers, the sensor enters low power mode and D[3:0] is set to FH. Video Processor released from reset. Video Processor enables the sensor clock, CLKI. At least 16 CLKI clock periods after CLKI has been enabled the VP sends a "Soft-Reset" command to the sensor via the serial interface. This ensures that if a sensor is present then it is in low-power mode. On detecting 32 consecutive FH values on D[3:0], the Video Processor sets the no_camera low. If present, upload the sensor defect map from E2PROM into the Video Processor Video Processor disables the sensor clock, CLKI. Video Processor generates the VP_Ready interrupt. The host software services the VP_Ready interrupt. Host issues command to remove sensor from low-power mode. VP enables the sensor clock, CLKI. At least 16 CLKI clock periods after CLKI has been enabled the VP sends the "Exit LowPower Mode" command to the sensor via the serial interface. This initiates the sensors 4 frame start sequence. One frame of alternating 9H & 6H data on D[3:0] for the video processor to determine the best sampling phase for the nibble data (D[3:0]). 4 Frames after the "Exit Low-Power Mode" serial comms, the sensor starts outputing valid video data.
PU6 PU7-PU8 PU9 PU10 PU11 PU12 PU13-PU4
PU15-PU16 PU17-PU18
Table 7 : System Power-Up or Hot-plugging Device Behaviour
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4.6.1 Power-Up/Down (Figure 12)
On power-up all of the databus lines will go high Immediately (FH), to indicate that the device is "present" and the device enters it low-power mode (Section 4.6.2). When the Video Processor is reset the following sequence should be executed to ensure that the VM6404 starts to generate video data: 1. After the Video Processor has been released from reset, the sensor clock, CLKI, should be enabled immediately 2. After waiting for at least 16 CLKI clock cycles, a "Soft Reset" command should be issued to the sensor. This is necessary to ensure that the sensor is brought into a known state. If the sensor is not present then the serial interface communications by Video Processor will not be acknowledged. 3. Poll for 32 consecutive FH values on the data bus, if this condition is satisfied then the sensor is present. The Video processor should set the camera_present flag. 4. Determine if the serial CMOS E2PROM containing the defectivity map for the sensor is present and down-load the values. 5. Disable the sensor clock CKI. 6. The Video Processor should generate the VP_Ready interrupt. 7. Once the host software serviced the VP_Ready interrupt, then the sensor and video processor is ready to generate video data. 8. To enable video data, the host software, sets the low-power mode bit low. The video processor must enable CLKI at least 16 CLKI clock cycles before issuing the "Exit Low-Power Mode" command via the serial interface. After the "Exit Low-Power Mode" command has been sent the sensor will output for one frame, a continuous stream of alternating 9H and 6H values on D[3:0]. By locking onto the resulting 0101/1010 patterns appearing on the data bus lines the video processor can determine the best sampling position for the nibble data. After the last 9H 6H pair has been output the databus returns to FH until the start of fifth frame after CKI has been enabled when the first active frame output. After the video processor has determined the correct sampling position for the data, it should then wait for the next start of frame line (SOF). If the video processor detects 32 consecutive 0H values on the data bus, then the sensor has been removed. The sensor clock, CKI, should be held low. 4.6.2 Low-Power Mode (Figure 10)
Under the control of the serial interface the sensor analogue circuitry can be powered down and then be powered up. When the low-power bit is set via the serial interface, all the databus lines will go high at the end of the end of frame line of the current frame. At this point the analogue circuits in the sensor will power down. The system clock must remain active for the duration of low power mode. Only the analogue circuits are powered down, the values of the serial interface registers e.g. exposure and gain are preserved. The internal frame timing is reset to the start of a video frame on exiting low-power mode. In a similar manner to the previous section, the first frame after the serial comms contains a continuous stream of alternating 9H and 6H to allow the video processor to re-confirm its sampling position. Then three frames latter the first start of frame line is generated. 4.6.3 Sleep Mode (Figure 11)
Sleep mode is similar to the low-power mode, except that analogue circuitry remains powered. When the sleep command is received via the serial interface the pixel array will be put into reset and the data lines all will go high at the end of the current frame. Again the system clock must remain active for the duration of sleep mode. When sleep mode is disabled, the CMOS sensor's frame timing is reset to the start of a frame. During the first frame after exiting from sleep mode the databus will remain high, while the exposure value propagates through the pixel array. At the start of the second frame the first start of field line will be generated.
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LP7
LP8
LP1 LP0
LP2
LP5 LP4 LP3
LP6
D[3:0]
FH
9H,6H,9H,6H...
FH
One frame of 9H & 6H data.
Start of Frame Line for the 1st frame of valid video data.
Valid Video data.
CLKI SDA SCL
CD5404-6404F-A
setup0[0] Frame Number
N 0 1 2 3 4 5
LP0-LP1 LP2 LP3-LP4 LP5-LP6 LP7-LP8
"Enter Low Power Mode" Command. At end of current frame, D[3:0] is set to FH and the VM6404 sensor's analogue circuitry is powered down. "Exit Low Power Mode" Command. Powers-up analogue circuits and initiates the VM6404 sensor's 4-frame start-up sequence 1 Frame of alternating 9H & 6H data on D[3:0] for the video processor to determine the best sampling phase for the nibble data (D[3:0]). 4 Frames after the "Exit low Power Mode" command, the sensor starts outputing valid video data.
VV5404 & VV6404
Figure 10 : Entering and Exiting Low Power Mode.
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SL1 SL0
SL2
SL5 SL4 SL3
SL6
SL7
D[3:0]
FH
Start of Frame Line for the 1st frame of valid video data.
Valid Video data.
CLKI SDA SCL
CD5404-6404F-A
setup0[1] Frame Number
N 0 1 2 3 4 5
SL0-SL1 SL2 SL3-SL4 SL6-SL7
"Enter Sleep Mode" Command. At end of current frame, D[3:0] is set to FH. "Exit Sleep Mode" Command. Powers-up analogue circuits and initiates the VM6404 sensor's 1-frame sleep start-up sequence 1 Frame after the "Exit Sleep Mode" command, the sensor starts outputing valid video data.
VV5404 & VV6404
Figure 11 : Entering and Exiting Sleep Mode.
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PU0
PU1
PU7 PU6 PU5 PU4 PU3 PU2
PU10 PU9 PU8
PU11
PU15 PU14 PU13 PU12
PU16
PU17
5V
2.8V
PU18
Regulated Sensor Power
One frame of 9H & 6H data. Start of Frame Line for the 1st frame of valid video data.
9H,6H,9H,6H... FH
0V
D[3:0] CLKI SDA SCL setup0[0] setup0[2] Frame Number Colour Video Processor VP dev_reset VP_Ready Camera_Present
FH
CD5404-6404F-A
0
1
2
3
4
VV5404 & VV6404
Figure 12 : System Power-Up or Hot-plugging Device Behaviour
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VV5404 & VV6404
4.6.4
Application of the system clock during sensor low-power modes
For successfully entry and exit into and out of low power and `sleep' modes the system clock, CLKI, must remain active for the duration of these modes. 4.7 Qualification of Output Data There are two distinct ways for qualifying the data nibbles appearing of the output data bus
4.7.1 Using the External Clock signal applied to CKI
The data on the output data bus, changes on the rising edge of CKI. The delay between the video processor supplying a rising clock edge and the data on the databus becoming valid, depends on the length of the cable between the sensor and the video processor. To allow the video processor to find the best sampling position for the data nibbles, via the serial interface the databus can be forced to output continuously 9H, 6H, 9H, 6H,... 4.7.2 Data Qualification Clock, QCK
VV6404 provides a data qualification clock for the output bus. There are two frequencies for the qualification clock: one runs at the nibble rate and the other at the pixel read-out rate. The falling edge of the fast QCK qualifies every nibble irrespective of whether it is most or least significant nibble. For the slow QCK, the rising edge qualifies the most significant nibbles in the output data stream and the falling edge qualifies the least significant nibbles in the output data stream. There are 4 modes of operation of QCK. 1. Disabled (Always low - (Default) 2. Free running - qualifies the whole of the output data stream. 3. Embedded control sequences, status data and pixel data. 4. Pixel Data Only. The operating mode for QCK is set via the serial interface. The QCK output is tristated when OEB is high.In one of the modes available via the serial interface the slow version of QCK will appear on the QCK pin while the fast version of the same signal will appear on the FST pin. In the case where the border rows and columns are disabled, there is simply no qualification pulse at that point in time i.e. when pixels 0,1, 354 and 355 are normally output. The QCK pin can also be configured to output the state of a serial interface register bit. This feature allows the sensor to control external devices, e.g. stepper motors, shutter mechanisms. The configuration details for QCK can be found in sections 5.5.7 and 5.5.8 of this document.
4.7.3
Frame Start Signal, FST
There are 3 modes of operation for the FST pin programmable via the serial interface: 1. Disabled (Always Low- Default). 2. Frame start signal. The FST signal occurs once frame, is high for 356 pixel periods (712 system clock periods) and qualifies the data in the start of frame line. The FST is tristated when OEB is high. The FST pin can also be configured to output the state of a serial interface register bit. This feature allows the sensor to control external devices, e.g. stepper motors, shutter mechanisms. The configuration details for FST can be found in sections 5.5.7 and 5.5.8 of this document.
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Line Format Start of Active Video (SAV) 4-wire Nibble Output Mode - D[3:0]
FH D1 D0 PM PL PM
Video Data
End of Active Video (EAV)
Pixel Data
PL PM PL PM PL FH FH FH
Crystal Clock or external clock applied to CKI
Slow Qualification Clock, QCK (i) Free running
CD5404-6404F-A
(ii) Control sequences and Pixel Data (iii) Pixel Data only
Fast Qualification Clock, QCK (i) Free running (ii) Control sequences and Pixel Data (iii) Pixel Data only
VV5404 & VV6404
PM = Pixel Value - Most Significant Nibble, PL = Pixel Value - Least Significant Nibble, P = 8-bit Pixel Value
Figure 13 : Qualification of Output Data (Border Rows and Columns Enabled).
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Frame Format (Border rows and columns enabled - Default) :
Blanking Line
303
Black Lines
Blanking Lines
Image Data
Frame Period (304 Lines) Line Number Line Code
CD5404-6404F-A
303
0
1
2
3
4
9
10
11
12
13
298
299
300
301
302
Start of Frame
0 1 SOF BK
Start of Frame
Start of Image (SOF)
BL SOF BK BK
7 Blank Lines (BL)
BL BL BL VL VL
292 Visible Lines (VL)
VL VL VL VL VL
End of Image (EOF)
VL EOF BL
2 Black Lines (BK) FST
QCK (i) Free Running
(ii) Control plus Data
(iii) Data Only
End of Frame
VV5404 & VV6404
Figure 14 : Frame Level Timings for FST and QCK (Border Rows and Columns Enabled).
24/54
Frame Format (Border rows and columns disabled) :
Black Lines
Blanking Lines
Image Data
Blanking Lines
Frame Period (304 Lines) Line Number Line Code
CD5404-6404F-A
303
0
1
2
3
4
9
10
11
12
13
298
299
300
301
302
303
Start of Frame
0 1 BL SOF BK
Start of Frame
Start of Image (SOF)
BL SOF BK BK BL
9 Blank Lines (BL)
BL BL BL BL
288 Visible Lines (VL) End of Image (EOF)
VL VL VL VL EOF BL BL
2 Black Lines (BK) FST
QCK (i) Free Running
(ii) Control plus Data
(iii) Data Only
End of Frame
VV5404 & VV6404
Figure 15 : Frame Level Timings for FST and QCK (Border Rows and Columns Disabled).
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VV5404 & VV6404
Frame Format (Border rows and columns enabled in example): Blanking Line Blanking Line Black Lines Blanking Lines Start of Frame Start of Frame End of Frame End of Frame Image Data Black Lines
Line Number
302 303 0 1 2 3 9
Frame Period (304 Lines)
10 11 300 301 302 303 0 1 2
FST
Start of Frame Line Format: Line Period (393 Pixel Periods - 30 fps, 471 Pixel Periods - 25 fps) 37 (115) Pixels EAV 33 (111) Pixels SAV 4 Pixels 356 Pixels Status Information EAV
FST (i) Frame start pulse - qualifies status line information.
Figure 16 : FST Pin Waveforms.
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5.
Serial Control Bus
5.1 General Description Writing configuration information to the video sensor and reading both sensor status and configuration information back from the sensor is performed via the 2-wire serial interface. Communication using the serial bus centres around a number of registers internal to the video sensor. These registers store sensor status, set-up, exposure and system information. Most of the registers are read/write allowing the receiving equipment to change their contents. Others (such as the chip id) are read only. The main features of the serial interface include: * Variable length read/write messages. * Indexed addressing of information source or destination within the sensor. * Automatic update of the index after a read of write message. * Message abort with negative acknowledge from the master. * Byte oriented messages. The contents of all internal registers accessible via the serial control bus are encapsulated in each start-of-field line see Section 4.3.4. 5.2 Serial Communication Protocol The video processor must perform the role of a communications master and the camera acts as either a slave receiver or transmitter.The communication from host to camera takes the form of 8-bit data with a maximum serial clock video processor frequency of up to 100 kHz. Since the serial clock is generated by the host it determines the data transfer rate. The bus address for the sensor in VV6404 is 20H and for the serial E2PROM containing the defect map it is A0H. Data transfer protocol on the bus is shown below.
Start condition
SDA
Acknowledge
MSB
SCL S
LSB 2 3 4 5 6 7 8
P
1
A Stop condition
Address or data byte
Figure 17 : Serial Interface Data Transfer Protocol
5.3 Data Format Information is packed in 8-bit packets (bytes) always followed by an acknowledge bit. The internal data is produced by sampling sda at a rising edge of scl. The external data must be stable during the high period of scl. The exceptions to this are start (S) or stop (P) conditions when sda falls or rises respectively, while scl is high. A message contains at least two bytes preceded by a start condition and followed by either a stop or repeated start, (Sr), followed by another message. The first byte contains the device address byte which includes the data direction read, (r), ~write, (~w), bit. The device address of VV6404 is fixed as 0010_000_[lsb]2. The lsb of the address byte indicates the direction of the message. If the lsb is set high then the master will read data from the slave and if the lsb is reset low then the master will write data to the slave. After the r,~w bit is sampled, the data direction cannot be changed, until the next address byte with a new r,~w bit is received. The byte following the address byte contains the address of the first data byte (also referred to as the index). The serial interface can address up to 128, byte registers. If the msb of the second byte is set the automatic increment feature of the address index is selected.
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Sensor acknowledges valid address S address[7:1] address [0] A
0010000
R
Acknowledge from slave A
DATA[7:0]
INC
INDEX[6:0]
A
/W bit
Auto increment Index bit
DATA[7:0]
A
P
Figure 18 : Serial Interface Data Format
5.4 Message Interpretation All serial interface communications with the sensor must begin with a start condition. If the start condition is followed by a valid address byte then further communications can take place. The sensor will acknowledge the receipt of a valid address by driving the sda wire low. The state of the read/~write bit (lsb of the address byte) is stored and the next byte of data, sampled from sda, can be interpreted. During a write sequence the second byte received is an address index and is used to point to one of the internal registers. The msbit of the following byte is the index auto increment flag. If this flag is set then the serial interface will automatically increment the index address by one location after each slave acknowledge. The master can therefore send data bytes continuously to the slave until the slave fails to provide an acknowledge or the master terminates the write communication with a stop condition or sends a repeated start, (Sr). If the auto increment feature is used the master does not have to send indexes to accompany the data bytes. As data is received by the slave it is written bit by bit to a serial/parallel register. After each data byte has been received by the slave, an acknowledge is generated, the data is then stored in the internal register addressed by the current index. During a read message, the current index is read out in the byte following the device address byte. The next byte read from the slave device are the contents of the register addressed by the current index. The contents of this register are then parallel loaded into the serial/parallel register and clocked out of the device by scl. At the end of each byte, in both read and write message sequences, an acknowledge is issued by the receiving device. Although VV5404 and VV6404 is always considered to be a slave device, it acts as a transmitter when the bus master requests a read from the sensor. At the end of a sequence of incremental reads or writes, the terminal index value in the register will be one greater the last location read from or written to. A subsequent read will use this index to begin retrieving data from the internal registers. A message can only be terminated by the bus master, either by issuing a stop condition, a repeated start condition or by a negative acknowledge after reading a complete byte during a read operation.
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5.5 The Programmers Model There may be up to 128, 8-bit registers within the camera, accessible by the user via the serial interface. They are grouped according to function with each group occupying a 16-byte page of the location address space. There may be up to eight such groups, although this scheme is purely a conceptual feature and not related to the actual hardware implementation, The primary categories are given below: * Status Registers (Read Only). * Setup registers with bit significant functions. * Exposure parameters that influence output image brightness. * System functions and analogue test bit significant registers. Any internal register that can be written to can also be read from. There are a number of read only registers that contain device status information, (e.g. design revision details). Names that end with H or L denote the most or least significant part of the internal register. Note that unused locations in the H byte are packed with zeroes. STMicroelectronics sensors that include a 2-wire serial interface are designed with a common address space. If a register parameter is unused in a design, but has been allocated an address in the generic design model, the location is referred to as reserved. If the user attempts to read from any of these reserved locations a default byte will be read back. In VV6404 this data is the LSByte of the device status word, address 000_0000. A write instruction to a reserved (but unused) location is illegal and would not be successful as the device would not allocate an internal register to the data word contained in the instruction.
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A detailed description of each register follows. The address indexes are shown as binary numbers in brackets [].
Index
000_0000 000_0001 000_0010 Status 000_0011 000_0100 000_0101 000_011x 000_1xxx 001_0000 001_0001 001_0010 Setup 001_0011 001_0100 001_0101 001_011x 001_1xxx 010_0000 010_0001 010_0010 Exposure 010_0011 010_0100 010_0101 010_0110 010_0111 010_1xxx 111_0000 111_0001 111_0010 111_0011 111_0100 System 111_0101 111_0110 111_0111 111_1000 111_1001 111_101x 111_11xx
Name
deviceH deviceL status0 line_countH line_countL Unused Unused Unused setup0 setup1 setup2 Reserved setup4 setup5 Unused Unused fineH fineL coarseH coarseL gain clk_div Unused Unused Unused Reserved Reserved Reserved Unused Reserved Reserved cr as0 Reserved Unused Unused Unused
Length
8 8 8 8 8
R/W
RO RO RO RO RO
Default
0001 10012 0100 00002 0000 10002
Comments
Chip identification number including revision indicator Current line counter MSB value Current line counter LSB value
8 8 8
R/W R/W R/W
0001 00012 1100 00012 31 Contains pixel counter reset value used by external sync. FST and QCK mode selects FST and QCK mapping mode.
8 8
R/W R/W
0 0
8 8 8 8 3 2
R/W R/W R/W R/W R/W R/W
0 302 0 0
Fine exposure. Coarse exposure ADC Pre-amp gain Setting Clock division
8 8
R/W R/W
0000 00002 0100 01002
Control Register ADC Setup Register
Table 8 : Serial Interface Address Map.
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5.5.1 DeviceH [000_00002] and DeviceL [000_ 00012]
These registers provide read only information that identifies the sensor type that has been coded as a 12bit number and a 4bit mask set revision identifier. The device identification number for VV6404 is 404 i.e. 0001 1001 01002. The initial mask revision identifier is 0 i.e. 00002.
Bits
7:0
Function
Device type identifier
Default
0001 10012
Comment
Most significant 8 bits of the 12 bit code identifying the chip type.
Table 9 : DeviceH [000_00002] Bits
7:4 3:0
Function
Device type identifier Mask set revision identifier
Default
01002 00002
Comment
Least significant 4 bits of the 12 bit code identifying the chip type.
Table 10 : DeviceL [000_00012]
5.5.2 Status0 [000_00102]
Bit
0 1 2 3
Function
Exposure value update pending Gain value update pending Clock divisor update pending Black cal fail flag
Default
0 0 0 0
Comment
Exposure sent but not yet consumed by the exposure controller Gain value sent but not yet consumed by the exposure controller Clock divisor sent but not yet consumed by the exposure controller If the black calibration has failed this flag will be raised. It will stay active until the last line of the next successful black calibration. The flag will toggle state on alternate frames
4 7:5
Odd/even frame Unused
1 000
Table 11 : Status0 [000_00102]
5.5.3 Line_count_H [000_00112] & Line_count_L [000_01002]
Register Index
000_00112 000_01002
Bits
7:0 7:0
Function
Current line count MSB Current line count LSB
Default
-
Comment
Displays current line count
Table 12 : Current Line Counter Value.
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5.5.4
Setup0 [001_00002]
Bit
0
Function
Low Power Mode: Off/On Sleep Mode: Off/On Soft Reset Off/On Frame Rate select: 25 fps or 30 fps Tri-state output data bus Outputs Enabled/Tristate unused
Default
1
Comment
Powers down the sensor array. The output databus goes to FH. On power-up the sensor enters low power mode. Puts the sensor array into reset. The output databus goes to FH. Setting this bit resets the sensor to its power-up defaults. This bit is also reset.
1 2 3 4 7:5
0 0 1 0
On power up the data output pads D[3:0] are enabled by default.
Table 13 : Setup0 [001_0000 2]
5.5.5
Setup1 [001_00012]
Bit
1:0
Function
Black calibration mode selection
Default
10
Comment
Black calibration trigger selection. Default setting bases decision on result of monitor test. See table below Allow manual change to clock division to be applied immediately Allow manual change to gain to be applied immediately If enabled this bit will also enable the line immediately following the end of frame line These extra pixels/rows are used in colour processing It is strongly recommended to use shuffled read-out.
2 3 4 5 6 7
reserved Enable immediate clock division update. Off/On Enable immediate gain update. Off/On Enable additional black lines (lines 3-9) Off/On Border rows and columns: Masked or Output Pixel read-out order: Unshuffled or Shuffled 0 0 0 1 1
Table 14 : Setup1 [001_0001 2]
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Black Cal Mode[1]
0 0 1 1
Black Cal Mode[0]
0 1 0 1
Comment
No black calibration Always trigger black calibration Black calibration triggered by a failed monitor test Trigger black calibration only if the gain setting changes
Table 15 : Black Calibration Mode
If the gain change trigger option has been selected then care should be taken when writing the new gain value if the immediate gain update option has been selected. It is strongly advised that the user should not write a new gain value between line 0 (the status line) and line 9 (the last black calibration line). If the gain values are written in a timed manner then no restriction applies.
5.5.6
Setup2 [001_00102]
Bit
5:0 7:6
Function
Pixel counter reset value Unused
Default
31
Comment
NOTE: For proper synchronisation this register should be written with the value 30.
Table 16 : Setup2[001_00102]
5.5.7 Setup4 [001_01002]
Bit
1:0 3:2 5:4 7:6 QCK modes Reserved FST modes
Function
FST/QCK pin modes
Default
0 0 0 0
Comment
Selection of FST, QCK pin data When to output QCK reserved for LST modes in other sensors
Table 17 : Setup4[001_01002]
FST/QCK pin mode[1:0]
0 0 1 1 0 1 0 1
FST pin
FST FST Fast QCK Invert of Fast QCK
QCK pin
Slow QCK Fast QCK Slow QCK Fast QCK
Table 18 : FST/QCK Pin Selection
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QCK mode[1:0]
0 0 1 1 0 1 0 1 Off Free Running
QCK state
Valid during data and control period of line (see note) Valid only during data period of line
Table 19 : QCK Modes
Note: Not currently verified. Contact STMicroelectronics for further information if this mode is to be used.
FST mode[1:0]
0 0 1 1 0 1 0 1 Off
FST state
On - qualifies the status line Reserved Unallocated
Table 20 : FST Modes
The option to enable the qclk during the data and control period of the line must not be selected if monochrome (shuffled or unshuffled) video has been selected.
5.5.8
Setup5 [001_01012]
It is important to note that although the output buffer driver strengths can be selected by writing to this register the programmed values cannot be read back by the serial interface.
Bit
0
Function
Map serial interface register bits values on to the QCK and FST pins Off/On Serial Interface Bit for QCK pin Serial Interface Bit for FST pin Output driver strength select Output driver strength select Unused
Default
0
Comment
1 2 3 4 7:5
0 0 1 0 0 Default setting selects 4mA driver Default setting selects 4mA drivers
Table 21 : Setup4[001_01012] Mapping Enable
0 1
FST pin
FST su5[2]
QCK pin
QCK su5[1]
Table 22 : FST/QCK Pin Selection
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oeb_composite
0 0 0 0 1
su5[4]
0 0 1 1 x
su5[3]
0 1 0 1 x
Comments
Drive strength = 2mA Default drive strength = 4mA Drive strength = 6mA unallocated Outputs are not being driven therefore driver strength is irrelevant
Table 23 : Output driver strength selection
5.5.9 Exposure Control Registers [010_00002] - [010_10012]
There is a set of programmable registers which controls the sensitivity of the sensor. The registers are as follows: 1. Fine exposure. 2. Coarse exposure time. 3. Gain. 4. Clock division. The gain parameter does not affect the integration period rather it amplifies the video signal at the output stage of the sensor core. Note: The external exposure (coarse, fine, clock division or gain) values do not take effect immediately. Data from the serial interface is read by the exposure algorithm at the start of a video frame. If the user reads an exposure value via the serial interface then the value reported will be the data as yet unconsumed by the exposure algorithm, because the serial interface logic locally stores all the data written to the sensor. Between writing the exposure data and the point at which the data is consumed by the exposure logic, bit 0 of the status register is set. The gain value is updated a frame later than the coarse, fine and clock division parameters, since the gain is applied directly at the video output stage and does not require the long set up time of the coarse and fine exposure and the clock division. To eliminate the possibility of the sensor array seeing only part of the new exposure and gain setting, if the serial interface communications extends over a frame boundary, the internal re-timing of exposure and gain data is disabled while writing data to any location in the Exposure page of the serial interface register map. Thus if the 5 bytes of exposure and gain data is sent as an auto-increment sequence, it is not possible for the sensor to consume only part of the new exposure and gain data. The range of some parameter values is limited and any value programmed out-with this range will be clipped to the maximum allowed.
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Register Index
010_00002 010_00012 010_00102 010_00112 010_01002
Bits
7:0 7:0 7:0 7:0 2:0
Function
Fine MSB exposure value Fine LSB exposure value Coarse MSB exposure value Coarse LSB exposure value Gain value
Default
0 302 0
Comment
Maximum mode dependent: 360 (30fps) / 438 (25 fps) Maximum: 302 000: Gain = 1 001: Gain = 2 011: Gain = 4 111: Gain = 8 00: Pixel clock = CLKI clock/2 01: Pixel clock = CLKI clock/4 10: Pixel clock = CLKI clock/8 11: Pixel clock = CLKI clock/16
010_01012
1:0
Clock divisor value
0
Table 24 : Exposure, Clock Rate and Gain Registers
Bit
0 1 2 5:3 7:6
Function
Standby Off/On Power Down - ADC Off/On Power Down - ADC Top Reference Off/On Reserved Unused
Default
0 0 0
Comment
Powers down ALL analogue circuitry
Table 25 : Control Register CR [111_01102]
Notes: 1. The enable signal enabling the external ADC functionality is the logical OR of CR0[0] bit and the invert of the ADCVDD pin. 2. The low-power select signal for the analogue circuitry is the logical OR of PD0[0] and Setup0[0].
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5.5.10 ADC Setup Register AS0 [111_01112]
Bit
1:0
Function
ADC Clock Fine Delay Setting 0 ns / 4 ns / 8 ns / 16 ns
Default
00
Comment
00: Clock Delay = 0 ns (Default) 01: Clock Delay = 4 ns 10: Clock Delay = 8 ns 11: Clock Delay = 16 ns 00: Phase Delay = 0 01: Phase Delay = 90 (Default) 10: Phase Delay = 180 11: Phase Delay = 270 00: Clock Delay = 0 ns (Default) 01: Clock Delay = 4 ns 10: Clock Delay = 8 ns 11: Clock Delay = 16 ns
3:2
ADC Clock Phase Delay Setting 0 / 90 / 180 / 270
01
5:4
PCK Clock Fine Delay Setting 0 ns / 4 ns / 8 ns / 16 ns
00
7:6
Reserved
1
Table 26 : ADC Setup Register AS0 [111_01112]
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5.6 Types of messages This section gives guidelines on the basic operations to read data from and write data to the serial interface. The serial interface supports variable length messages. A message may contain no data bytes, one data byte or many data bytes. This data can be written to or read from common or different locations within the sensor. The range of instructions available are detailed below. * Write no data byte, only sets the index for a subsequent read message. * Single location multiple data write or read for monitoring (real time control) * Multiple location, multiple data read or write for fast information transfers. Examples of these operations are given below. A full description of the internal registers is given in the previous section. For all examples the slave address used is 3210 for writing and 3310 for reading. The write address includes the read/write bit (the lsb) set to zero while this bit is set in the read address.
5.6.1 Single location, single data write.
When a random value is written to the sensor, the message will look like this:
Start S
Device address
Ack A0
Index 3210 A
Data 8510
Stop A P
3210
Figure 19 : Single location, single write.
In this example, the fineH exposure register (index = 3210) is set to 8510. The r/w bit is set to zero for writing and the inc bit (msbit of the index byte) is set to zero to disable automatic increment of the index after writing the value. The address index is preserved and may be used by a subsequent read. The write message is terminated with a stop condition from the master. 5.6.2 Single location, single data read.
A read message always contains the index used to get the first byte.
Start S
Device address
Ack A0
Index 3210 A
Data 8510
Stop A P
3310
Figure 20 : Single location, single read.
This example assumes that a write message has already taken place and the residual index value is 3210. A value of 8510 is read from the fineH exposure register. Note that the read message is terminated with a negative acknowledge (A) from the master: it is not guaranteed that the master will be able to issue a stop condition at any other time during a read message. This is because if the data sent by the slave is all zeros, the sda line cannot rise, which is part of the stop condition. 5.6.3 No data write followed by same location read.
When a location is to be read, but the value of the stored index is not known, a write message with no data byte must be written first, specifying the index. The read message then completes the message sequence. To avoid relinquishing the serial to bus to another master a repeated start condition is asserted between the write and read messages. In this example, the gain value (index = 3610) is read as 1510:
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No data write S 3210 A0 3610 A Sr 3310
Read index and data A0 3610 A 1510 A P
Figure 21 : No data write followed by same location read.
As mentioned in the previous example, the read message is terminated with a negative acknowledge (A) from the master. 5.6.4 Same location multiple data write.
It may be desirable to write a succession of data to a common location. This is useful when the status of a bit,(e.g. requesting a new black calibration), must be toggled. The message sequence indexes setup1 register. If bit 1 is toggled low, high low this will initiate a fresh black calibration. This is achieved by writing three consecutive data bytes to the sensor. There is no requirement to re-send the register index before each data byte.
Write setup1 S 3210 A0 1710 A 010 Turn off ABC A
Toggle "Force Black Cal.". 210 A 010 AP
Figure 22 : Same location multiple data write.
5.6.5 Same location multiple data read
When an exposure related value (fineH, fineL, coarseH, coarse L, gain or clk_div) is written, it takes effect on the output at the beginning of the next video frame, (remember that the application of the gain value is a frame later than the other exposure parameters). To signal the consumption of the written value, a flag is set when any of the exposure or gain registers are written and is reset at the start of the next frame. This flag appears in status0 register and may be monitored by the bus master. To speed up reading from this location, the sensor will repeatedly transmit the current value of the register, as long as the master acknowledges each byte read. In the next example, a fineH exposure value of 0 is written, the status register is addressed (no data byte) and then constantly read until the master terminates the read message.
Write fineL with zero S 3210 A0 3310 A 0 A Sr
Address the status0 reg. 3210 A 010 A
Read continuously... Sr 3310 A0 010 A 1 A 1 A 1 A
...until flag reset 1 A 0 AP
Figure 23 : Same location multiple data read.
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5.6.6
Multiple location write
If the automatic increment bit is set, (msb of the index byte), then it is possible to write data bytes to consecutive adjacent internal registers without having to send explicit indexes prior to sending each data byte. An auto-increment write to the black calibration DAC registers with their default values is shown in the following example. .
Incremental write S 3210 A1 11310 A 12816 A 12816 AP
Figure 24 : Multiple location write.
5.6.7 Multiple location read
In the same manner, multiple locations can be read with a single read message. In this example the index is written first, to ensure the exposure related registers are addressed and then all six are read
No data write S 3210 A1 3210 A Sr 3310
Incremental read A1 3210 A
fineH
A
Incremental read
fineL
A
coarseH A
coarseL A
gain
A
clk_div
AP
Figure 25 : Multiple location read.
Note that a stop condition is not required after the negative acknowledge from the master.
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5.7
Serial Interface Timing
stop
start
start
stop
SDA
...
tbuf
tlow tr
tf
thd;sta
SCL
...
thd;sta
thd;dat
thigh
tsu;dat
tsu;sta
tsu;sto
all values referred to the minimum input level (high) = 3.5V, and maximum input level (low) = 1.5V
Figure 26 : Serial Interface Timing Characteristics
Parameter
SCL clock frequency Bus free time between a stop and a start Hold time for a repeated start LOW period of SCL HIGH period of SCL Set-up time for a repeated start Data hold time Data Set-up time Rise time of SCL, SDA Fall time of SCL, SDA Set-up time for a stop Capacitive load of each bus line (SCL, SDA)
Symbol
fscl tbuf thd;sta tlow thigh tsu;sta thd;dat tsu;dat tr tf tsu;sto Cb
Min.
0 2 80 320 160 80 0 0 80 -
Max.
100 300 (note1) 300 (note1) 200
Unit
kHz us us us us us us ns ns ns us pF
Table 27 : Serial Interface Timing Characteristics
NOTE 1: With 200pF capacitive load. It is recommended that pull-up resistors of 2.2k - 4.7k are fitted to both SDA and SCL lines.
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6. Clock Signal VV5404 and VV6404 generate a system clock when a quartz crystal or ceramic resonator circuit is connected to the CLKI and CLKO pins. The device can also be driven directly from an external clock source driving CLK. If CLKI is generated for the video sensor by the receiving device it must be active during serial interface communications for at least 16 clock cycles before the serial communications start bit and for at least 16 cycles after the serial communications stop bit. The synchronisation input, SIN, synchronises the clock divider logic in addition to the main clock generation and the video timing control block. .
C1
31
CLKI
VV5/6404
Clock Source
31
CLKI
VV5/6404
X1
R1
CLKO
CLOCK DIVISION
CMOS Driver CLK
CLKO
CLOCK DIVISION
CLK
C2
R2
32 C1 = C2 = 47 pF X1 = 14.31818 MHz
32
R1 = 1 M R2 = 510
Figure 27 : Camera Clock Sources
For greater flexibility the input frequency can be divided by 2, 4, 8 or 16 to select the pixel clock frequency. The clock divisor serial register selects the input clock frequency divisor. The clock signal must be a square wave with a 50% (+/- 10%) mark:space ratio. Table 28 specifies the maximum and minimum pixel clock frequencies for the module. Table 29 and Table 29 specify the relationship between the input clock, CLKI, and the pixel clock frequency for the different settings of the sensor's internal clock divider.
MHz
Minimum Pixel Rate Maximum Pixel Rate 0.44744 3.57954
Table 28 : Maximum and Minimum Pixel Rates
This translates into a maximum input clock frequency of 7.15909 MHz if a clock divisor of 2 is used (the default - Table 29). Thus if a 14.31818 MHz crystal is used, only the 4, 8 and 16 clock divisors should be used (Table 29).
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CLKI (MHz)
7.15909 7.15909 7.15909 7.15909
Clock Div Reg Divisor bit 1
0 0 1 1
bit 0
0 1 0 1 2 4 8 16
Pixel Frequency (MHz)
3.57954 1.78977 0.89489 0.44744
Frame rate (fps) Comments 30 fps
30.0 15.0 7.50 3.75
25 fps
25.0 12.5 6.25 3.125 Default
Table 29 : Clock Divisors for an externally generated clock signal. CLKI (MHz)
14.31818 14.31818 14.31818 14.31818
Clock Div Reg Divisor bit 1
0 0 1 1
bit 0
0 1 0 1 2 4 8 16
Pixel Frequency (MHz)
7.15909 3.57954 1.78977 0.89489
Frame rate (fps) Comments 30 fps 25 fps
Not Valid 30.0 15.0 7.50 25.0 12.5 6.25
Table 30 : Clock Divisors for a 14.31818 MHz Crystal
6.8 Synchronising 2 or More Cameras
A rising edge on the SIN pin re-synchronises the sensor's internal video timing logic and clock generators to 5 pixels before the end of the start of frame control sequence in line 0 (assuming the Setup2 register has been programmed correctly with the value 30). By supplying an external timing signal to SIN, with a period equal to 2 frames (see Figure 28), 2 or more cameras can be synchronised together. For proper synchronisation, the pixel counter register Setup2 must be written with 30, which will cause SIN to reset the video timing to 5 pixel periods before the end of the start of frame control sequence. SIN is sampled internally by the system clock, CKI. If all cameras are supplied with the same clock signal then the reset generated by SIN will synchronise all the cameras to the same point in time. However, if the cameras being synchronised are running at the same frequency but each camera has its own crystal, then there could be upto one system clock period of skew between the cameras. This skew will vary over time due to the slight mis-matches between frequencies of the different crystals. .
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Frame Format:
1st Frame End of Frame Blanking Lines Blanking Lines End of Frame Blanking Lines Start of Frame Blanking Lines Start of Frame Visible Lines Black Lines Black Lines
2nd Frame End of Frame Blanking Lines Start of Frame Visible Lines EAV EAV
FST: (ii) Off (ii) On (iii) Sync input at SIN (if external synchronisation required))
Start of Frame Line Format: Line Period (393 Pixel Periods - 30 fps, 471 Pixel Periods - 25 fps) 37 (115) Pixels EAV 33 (111) Pixels SAV 4 Pixels 356 Pixels
Status Information
Synchronisation input (at SIN pin) from the master (e.g. video processor).
1 Pixel Period Output of Slave 2 - Pixel Counter Reset Value = 30. EAV SAV
Status Information
Figure 28 : Synchronisation Waveforms
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7. 7.1
Detailed specifications General
Image Format Pixel Size Array Format Exposure control Sensor signal / Noise ratio Minimum illumination Supply Voltage Package type Operating Temp. range Serial interface frequency range Supply Voltage Supply Current Package type
356 x 292 pixels (CIF) 12.0 x 11.0m CIF 25000:1 (performed by co-processor) 46dB 0.1 lux 5.0v DC +/-5% 48LCC 0oC - 40oC* 0-100kHz 5.0 V DC +/- 5% < 75 mA 48BGA
Table 31 : VV5407/6407 Specifications
* Contact STMicroelectronics for information regarding increased temperature range
7.2
DC characteristics
Parameter
VIL VIH VOL VOH TJ Junction Temp Internal Pullup resistor Internal Pulldown resistor
Min.
-0.5v 0.7 x VDD
Max.
0.3 x VDD VDD + 0.5v 0.4V
Notes
Guaranteed input low voltage Guaranteed input high voltage At max IOL for pad type IOH = 100A At max IOH for pad type
2.4v
VDD - 0.5v 100 deg C 150k 150k
0 deg C 35k 35k
Table 32 : VV5407/6407 DC Characteristics
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8. 8.1
Physical Pinout Diagram
(DNC)
(DNC)
(DNC)
(DNC)
(DNC)
(DNC)
(DNC)
VDD2
(DNC)
30 CLKI CLKO QCK D[0] D[1] VDD3 VSS3 D[2] D[3] FST SDA SCL 31 32 33 34 35 36 37 38 39 40 41 42 43 DVDD
29
28
27
26
25
24
23
22
21
20
19 18 17 16 15 14 (DNC) OEB/SCI RESETB SIN ADCVDD TopRef/ADCTop HOLDPIX ADCBot ADCVSS (*) VVSS (DNC) VVDD
VV5/6404 48 pin LCC
VDD1 13 12 11 10 9 8 7 6 AVDD
VSS2
44 DVSS/Dsub
45 VBLOOM
46 VBLTW
47 VBG
48 AGND (*)
1 AVCC
2 VCM / VREF2V5
3 VRT
4 VCDS
5 AVSS
Figure 29 : Pinout
(DNC) - Do not connect these pins (*) - Paddle connections
VSS1
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8.2
Signal Names
Pin
Name
Type
Description POWER SUPPLIES
1 48 43 44 6 5 7 9 14 10 19 30 36 20 29 37
AVCC AGND DVDD DVSS/Dsub AVDD AVSS VVDD VVSS ADCVDD ADCVSS VDD1 VDD2 VDD3 VSS1 VSS2 VSS3
PWR GND PWR GND PWR GND PWR GND PWR GND PWR PWR PWR GND GND GND
Core analogue power and reference supplies. Core analogue ground and reference supplies. Core digital power. Core digital ground. Output stage power. Output stage ground. Analogue output buffer power. Analogue output buffer ground. ADC power. ADC ground. Digital padring & logic power. Digital padring & logic power. Digital padring & logic power. Digital padring & logic ground. Digital padring & logic ground. Digital padring & logic ground.
ANALOGUE SIGNALS
45 46 47 2 3 4 8 11 12 13 VBLOOM VBLTW VBG VCM/ VREF2V5 VRT VCDSH AVO ADCbot HoldPix TopRef OA OA OA OA IA IA OA IA IA OA Analogue Test output Bottom voltage reference for ADC Not for Customer use Internally generally top voltage reference for ADC Anti-blooming pixel reset voltage Bitline test white level reference Internally generated bandgap reference voltage 1.22V Common-mode input for OSA and Internally generated 2.5 V reference voltage. Pixel reset voltage
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Pin
Name
Type
Description DIGITAL CONTROL SIGNALS
18 15 16
SCE SIN RESETB
ID ID ID
Test Pin Frame timing reset (soft reset). System Reset. Active Low.
SERIAL INTERFACE
42 41 SCL SDA ID BI Serial bus clock (input only). Serial bus data (bidirectional, open drain).
DIGITAL VIDEO INTERFACE
39 38 35 34 33 40 17 D[3] D[2] D[1] D[0]] QCK FST OEB ODT Tristateable 4-wire output data bus. D[3] is the most significant bit.
ODT ODT ID
Tristateable data qualification clock. Tristateable Frame start signal. Digital output (tristate) enable.
SYSTEM CLOCKS
31 32 CLKI CLKO ID OD Oscillator input. Oscillator output.
Key A OA BI BI BI Analogue Input Analogue Output Bidirectional Bidirectional with internal pull-up Bidirectional with internal pull-down D ID ID OD ODT Digital Input Digital input with internal pull-up Digital input with internal pull-down Digital Output Tristateable Digital Output
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8.3
48LCC Mechanical Dimensions
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8.4
VV6404 Sensor Support Circuit Schematic Diagram DVDD/AVDD +5v DC
C1 C2 C3
0v
C4
AGND DGND
19 30 36 1 VDD1 VDD2 VDD3
43 6 DVDD AVCC AVDD
7 14 ADCVDD VVDD
20 29 37 44 5 48 9 10
VSS1 VSS2 VSS3 DVSS AVSS AGND VVSS
IC1 (48 pin LCC)
D[3] D[2] D[1] D[0]
C4
39 38 35 34 45
ADCVSS D[3] D[2] D[1] D[0] VBLOOM Holdpix ADCtop/TopRef VBLTW VBG 33 QCK FST VCM / VREF2V5 OEB VRT RESETB SIN 17 16 15 40 C14 C16
VV5/6404
11 ADCbot C13 12 13 C15
46
C5 47 C6
2
3 AVDD R1 R2 TP1 C10 C8 C9 C7 R3 4
CLKO
VCDSH CLKI
SDA
31
32 41 42
SCL DVDD R4 R5
CLKI SDA SCL
C11
C12
8.5
Sensor Support Circuit Component List
CD5404-6404F-A
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VV5404 & VV6404
Component
IC1 C1 C2-C3, C4-C6, C7-C8 C9-C10 C11-C12 C13-C14 C15 C16
Part No. / Provisional Value
VV6404A 10.0 F 0.1 F 10.0 F 220pF(*) 0.1 F 4.7 F 10.0 F TDB
Rating / Notes
VVL camera chip (48 pin LCC) 6V tant.
6V tant. For 3m cable length
6V tant 6V tant
R1-R2 R3 R4-R5
Voltage divider such that TP1 = 3.2v 33 2k2() For 3m cable length
Table 33 : PCB Component List
Notes: 1. Use surface mount components throughout. 2. All ceramic capacitors are type COG. 3. Keep nodes Supply and Ground pins low impedance and independent. 4. Keep circuit components close to chip pins (especially de-coupling capacitors). 5. EMC precautions will be required on D[3:0] if driving a longer cable.
CD5404-6404F-A
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VV5404 & VV6404
9.
Ordering Information
Part Number
VV5404C001
Description
CIF resolution monochrome Digital CMOS Image Sensor, 48 pin LCC package CIF resolution Colour Digital CMOS Image Sensor, 48 pin LCC package CIF resolution Colour Digital CMOS Image Sensor, 48 pin LCC package
Defect specification
zero defects
VV6404C001 VV6404C001-B2
zero defects up to 36 defects for use when pixel defect correction is implemented N/A N/A
STV5404E-001 STV6404E-001
Evaluation Kit for VV5404 sensor Evaluation Kit for VV6404 sensor
CD5404-6404F-A
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VV5404 & VV6404
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CD5404-6404F-A
VV5404 & VV6404
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result fr om its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - All Rights Reserved .
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(R)
VLSI VISION LIMITED
A company of the ST Microelectronics Group
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