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TH50VSF3582/3583AASB
TENTATIVE TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS
SRAM AND FLASH MEMORY MIXED MULTI-CHIP PACKAGE DESCRIPTION
The TH50VSF3582/3583AASB is a mixed multi-chip package containing a 8,388,608-bit Full CMOS SRAM and a 33,554,432-bit flash memory. The CIOS and CIOF inputs can be used to select the optimal memory configuration. The power supply. FLASH MEMORY a Simultaneous Read/Write operation so that data can be read during a Write or Erase operation. The TH50VSF3582/3583AASB can range from 2.67 V to 3.3 V. The TH50VSF3582/3583AASB is available in a 69-pin BGA package, making it suitable for a variety of design applications.
FEATURES
* * * Power supply voltage VCCs = 2.67 V~3.3 V VCCf = 2.67 V~3.3 V Data retention supply voltage VCCs = 1.5 V~3.3 V Current consumption Operating: 45 mA maximum (CMOS level) Standby: 10 A maximum (SRAM CMOS level) Standby: 10 A maximum (FLASH) Block erase architecture for flash memory 8 x 8 Kbytes 63 x 64 Kbytes Organization
CIOF VCC VCC VSS CIOS VCC VSS VSS Flash Memory 2,097,152 words of 16 bits 2,097,152 words of 16 bits 4,194,304 words of 8 bits SRAM 524,288 words of 16 bits 1,048,576 words of 8 bits 1,048,576 words of 8 bits
* *
* *
* * *
PIN ASSIGNMENT (TOP VIEW)
*
Case: CIOF = VCC, CIOS = VCC (x16, x16)
1 2 3 4 5 6 7 8 9 10
Function mode control for flash memory Compatible with JEDEC-standard commands Flash memory functions Simultaneous Read/Write operations Auto-Program Auto Chip Erase, Auto Block Erase Auto Multiple-Block Erase Program Suspend/Resume Block-Erase Suspend/Resume Data Polling/Toggle Bit function Block Protection/Boot Block Protection Automatic Sleep, Hidden ROM Area Supports Common Flash Memory Interface (CFI) Byte/Word Mode Erase and Program cycle for flash memory 105 cycles (typical) Boot block architecture for flash memory TH50VSF3582AASB: Top boot block TH50VSF3583AASB: Bottom boot block Package P-FBGA69-1209-0.80A3: 0.31 g (typ.)
PIN NAMES
A0~A21 A12S A12F SA DQ0~DQ15 CEF OE
Address Inputs A12 Input for SRAM A12 Input for Flash Memory A18 Input for SRAM Data Inputs/Outputs Chip Enable Input for Flash Memory Output Enable Input Write Enable Input Data Byte Control Input Ready/Busy Output Hardware Reset Input Write Protect/Program Acceleration Input Word Enable Input for SRAM Word Enable Input for Flash Memory Power Supply for SRAM Power Supply for Flash Memory Ground Not Connected Don't Use
000707EBA2
A B C D E F G H J K L M
NC NC NC A3 A2 NC NC A1 A0 CEF CE1S A7 A6 A5 A4 VSS OE DQ0 DQ8 NC NC
NC NC
CE1S , CE2S Chip Enable Inputs for SRAM
LB
UB A18 A17 DQ1 DQ9 DQ10 DQ2
WP/ACC RESET
WE
CE2S A20
A8 A19 A9 A10 DQ6
A11 A12 A13 A14 DU A15 NC NC A16 NC NC
WE LB , UB RY/BY
RESET WP/ACC CIOS CIOF VCCs VCCf NC NC VSS NC DU
RY/BY
DQ3 VCCf DQ11
DQ4
DQ13 DQ15 CIOF DQ7 DQ14 VSS
VCCs DQ12 CIOS DQ5
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk.
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PIN ASSIGNMENT (TOP VIEW)
*
Case: CIOF = VCC, CIOS = VSS (x16, x8)
1 2 3 4 5 6 7 8 9 10
A B C D E F G H J K L M
NC NC NC A3 A2 NC NC A1 A0 CEF CE1S A7 A6 A5 A4 VSS OE DQ0 DQ8 NC NC DU DU A18 A17 DQ1 DQ9 DQ10 DQ2 DQ3 VCCf DQ11 DQ4 WP/ACC RESET
NC NC
WE
CE2S A20
A8 A19 A9 A10 DQ6
A11 A12 A13 A14 SA A15 NC NC A16 NC NC
RY/BY
DQ13 DQ15 CIOF DQ7 DQ14 NC NC VSS
VCCs DQ12 CIOS DQ5
*
Case: CIOF = VSS, CIOS = VSS (x8, x8)
1 2 3 4 5 6 7 8 9 10
A B C D E F G H J K L M
NC NC NC A3 A2 NC NC A1 A0 CEF CE1S A7 A6 A5 A4 VSS OE DQ0 DU NC NC DU DU A19 A18 DQ1 DU DU DQ2 DQ3 VCCf DU DQ4 VCCs CIOS WP/ACC RESET
NC NC
WE
CE2S A21
A8 A20 A9 A10 DQ6 DU DU DQ5
A11 A13 A14 A15 A12S A12F DQ7 DU NC NC A16 NC NC A17 CIOF VSS NC NC
RY/BY
Note: A12F and A12S should be wired and used as A12 pin.
000707EBA2
* The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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TH50VSF3582/3583AASB
BLOCK DIAGRAM
VCCf A0~A21 A0~A21
WP/ACC RESET CEF
VSS
32-Mbit Flash Memory
DQ0~DQ15 (DQ0~DQ7)
RY/BY CIOF VCCs A0~A18 VSS DQ0~DQ15
SA WE OE CE1S CE2S UB LB CIOS
8-Mbit SRAM Memory DQ0~DQ15 (DQ0~DQ7)
MODE SELECTION
OPERATION MODE Flash Read
CEF CE1S
CE2S X L H H H X L H H H X L X X X X X L
OE
WE H H H H H L L L L L H H H X X X X X
RESET
UB
LB X X L L H X X L L H X X X H X X X X
WP/ACC
DQ0~DQ7 DOUT DOUT DOUT DOUT Hi-Z DIN DIN DIN DIN Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z S S F F
DQ8~DQ15 DOUT DOUT DOUT Hi-Z DOUT DIN DIN DIN Hi-Z DIN Hi-Z Hi-Z Hi-Z Hi-Z S S F F
L L H
H X L L L H X L L L H X X X X X H X
L L L L L H H X X X H H H X X X X X
H H H H H H H H H H X X X X H L X X
X X L H L X X L H L X X X H X X X X
X X X X X X X X X X X X X X X X X X
SRAM Read
H H
Flash Write
L L H
SRAM Write
H H
Flash Output Disable
X X
SRAM Output Disable Flash Standby Flash Hardware Reset / Standby SRAM Standby
H H H X X X
Notes: L = VIL; H = VIH; X = VIH or VIL F: Depends on flash memory operation mode. S: Depends on SRAM operation mode. When CIOS = VCC and CIOF = VCC, Word Mode is selected for both SRAM and flash memory. Does not apply when CEF = CE1S = VIL and CE2S = VIH at the same time.
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ID CODE TABLE
TYPE Manufacturer Code TH50VSF3582AASB Device Code TH50VSF3583AASB Verify Block Protect Note: * = VIH or VIL L = VIL H = VIH (1) DQ8~DQ15 are Hi-Z in Byte mode (2) BA: Block address (3) 0001H: Protected block 0000H: Unprotected block * BA
(2)
A20~A12 * *
A6 L L L L
A1 L L L H
A0 L H H L
CODE (HEX) 0098H 009AH 009CH Data
(3)
(1)
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COMMAND SEQUENCES
BUS COMMAND SEQUENCE WRITE CYCLES REQ'D Read/Reset Read/Reset Word Byte Word ID Read Byte Word Byte Program Suspend Program Resume Auto Chip Erase Auto Block Erase Word Byte Word Byte 1 1 4 Word 3 Byte Fast Program Set Fast Program Fast Program Reset Hidden ROM Mode Entry Hidden ROM Program Hidden ROM Erase Hidden ROM Mode Exit Word Byte Word Byte Word Byte Word Byte Word 2 Byte 4 6 4 Word Byte 2 2 3 AAAH 555H AAAH XXXH XXXH 555H AAAH 555H AAAH 555H AAAH 555H AAAH BK BK
(3)
FIRST BUS WRITE CYCLE Addr. XXXH 555H AAAH 555H Data F0H AAH
SECOND BUS WRITE CYCLE Addr. Data
THIRD BUS WRITE CYCLE Addr. Data
FOURTH BUS WRITE CYCLE Addr. Data
FIFTH BUS WRITE CYCLE Addr. Data
SIXTH BUS WRITE CYCLE Addr. Data
1 3
2AAH 555H 2AAH
55H
555H AAAH BK
(3)
F0H
RA
(1)
RD
(2)
+ + 90H IA
(4)
3 AAAH 555H AAAH 1 1 6 BK BK
(3) (3)
AAH 555H 2AAH 555H B0H 30H AAH 2AAH 555H AAH B0H 30H 60H BPA
(9)
55H
555H BK
(3)
ID
(5)
AAAH 55H 555H AAAH A0H PA
(6)
Auto-Program
4
AAH
PD
(7)
555H AAAH
55H
555H AAAH
80H
555H AAAH
AAH
2AAH 555H
55H
555H AAAH
10H
6
555H AAAH BK BK
(3) (3)
2AAH 555H
55H
555H AAAH
80H
555H AAAH
AAH
2AAH 555H
55H
BA
(8)
30H
Block Erase Suspend Block Erase Resume Block Protect
XXXH 555H
60H
XXXH BK + 555H
(3) (3)
40H
BPA
(9)
BPD
(10)
Verify Block Protect
2AAH AAH 555H 2AAH 555H A0H 90H AAH PA
(6)
55H
BK
+
90H
BPA
(9)
BPD
(10)
AAAH 55H PD F0H
(7)
3
AAH
555H AAAH
20H
XXXH 2AAH 555H
(13)
55H
555H AAAH
88H
(6) (7)
AAH
2AAH 555H
55H
555H AAAH
A0H
PA
PD
AAH
2AAH 555H
55H
555H AAAH
80H
555H AAAH
AAH
2AAH 555H
55H
BA
(8)
30H
AAH
2AAH 555H
55H
555H AAAH
90H
XXXH
00H
+ + 98H CA
(11)
Query Command
55H
(3)
CD
(12)
AAH
Note: The system should generate the following address patterns: Word Mode: 555H or 2AAH to addresses A10~A0 Byte Mode: AAAH or 555H to addresses A10~A0, A12F DQ8~DQ15 are ignored in Word mode.
* Byte mode when VIL is inputted to CIOF, and addresses are A21~A0 * Write mode when VIH is inputted to CIOF, and addresses are A20~A0 * Valid addresses are A10~A0 when a command is entered. (6) PA: Program Address (1) RA: Read Address (2) RD: Read Data (7) PD: Program Data (3) BK: Bank Address = A20~A15 (8) BA: Block Address = A20~A12 (4) IA: Bank Address and ID Read Address (A6, A1, A0) (9) BPA: Block Address and ID Read Address (A6, A1, A0) Bank Address = A20~A15 Block Address = A20~A12 Manufacturer Code = (0, 0, 0) ID Read Address = (0, 1, 0) Device Code = (0, 0, 1) (10) BPD: Verify Data (5) ID: ID Data (11) CA: CFI Address 0098H - Manufacturer Code (12) CD: CFI Data 009AH - Device Code (TH50VSF3582AASB) (13) F0H: 00H is valid too 009CH - Device Code (TH50VSF3583AASB) 0001H - Protected Block
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BLOCK ERASE ADDRESS TABLES
TH50VSF3582AASB (top boot block)
BLOCK ADDRESS BANK # BLOCK # ADDRESS RANGE BANK ADDRESS A20 A19 A18 A17 A16 A15 A14 A13 A12 BA0 BA1 BA2 BA3 BK0 BA4 BA5 BA6 BA7 BA8 BA9 BA10 BA11 BK1 BA12 BA13 BA14 BA15 BA16 BA17 BA18 BA19 BK2 BA20 BA21 BA22 BA23 BA24 BA25 BA26 BA27 BK3 BA28 BA29 BA30 BA31 L L L L H H H H H H H H H H H H L L H H L H L H * * * * * * * * * * * * 1C0000H~1CFFFFH 1D0000H~1DFFFFH 1E0000H~1EFFFFH 1F0000H~1FFFFFH 0E0000H~0E7FFFH 0E8000H~0EFFFFH 0F0000H~0F7FFFH 0F8000H~0FFFFFH L L L L L L L L H H H H H H H H L L L L H H H H H H H H L L L L L L H H L L H H L H L H L H L H * * * * * * * * * * * * * * * * * * * * * * * * 140000H~14FFFFH 150000H~15FFFFH 160000H~16FFFFH 170000H~17FFFFH 180000H~18FFFFH 190000H~19FFFFH 1A0000H~1AFFFFH 1B0000H~1BFFFFH 0A0000H~0A7FFFH 0A8000H~0AFFFFH 0B0000H~0B7FFFH 0B8000H~0BFFFFH 0C0000H~0C7FFFH 0C8000H~0CFFFFH 0D0000H~0D7FFFH 0D8000H~0DFFFFH L L L L L L L L L L L L H H H H H H H H L L L L H H H H L L L L L L H H L L H H L H L H L H L H * * * * * * * * * * * * * * * * * * * * * * * * 0C0000H~0CFFFFH 0D0000H~0DFFFFH 0E0000H~0EFFFFH 0F0000H~0FFFFFH 100000H~10FFFFH 110000H~11FFFFH 120000H~12FFFFH 130000H~13FFFFH 060000H~067FFFH 068000H~06FFFFH 070000H~077FFFH 078000H~07FFFFH 080000H~087FFFH 088000H~08FFFFH 090000H~097FFFH 098000H~09FFFFH L L L L L L L L L L L L L L L L L L L L H H H H H H H H L L L L L L H H L L H H L H L H L H L H * * * * * * * * * * * * * * * * * * * * * * * * 040000H~04FFFFH 050000H~05FFFFH 060000H~06FFFFH 070000H~07FFFFH 080000H~08FFFFH 090000H~09FFFFH 0A0000H~0AFFFFH 0B0000H~0BFFFFH 020000H~027FFFH 028000H~02FFFFH 030000H~037FFFH 038000H~03FFFFH 040000H~047FFFH 048000H~04FFFFH 050000H~057FFFH 058000H~05FFFFH L L L L L L L L L L L L L L L L L L H H L H L H * * * * * * * * * * * * BYTE MODE 000000H~00FFFFH 010000H~01FFFFH 020000H~02FFFFH 030000H~03FFFFH WORD MODE 000000H~007FFFH 008000H~00FFFFH 010000H~017FFFH 018000H~01FFFFH
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BLOCK ADDRESS BANK # BLOCK # ADDRESS RANGE BANK ADDRESS A20 A19 A18 A17 A16 A15 A14 A13 A12 BA32 BA33 BA34 BA35 BK4 BA36 BA37 BA38 BA39 BA40 BA41 BA42 BA43 BK5 BA44 BA45 BA46 BA47 BA48 BA49 BA50 BA51 BK6 BA52 BA53 BA54 BA55 BA56 BA57 BA58 BK7 BA59 BA60 BA61 BA62 H H H H H H H H H H H H H H H H H H H H H H L L L L H H H H H H H H H H H L L L L H H H L L H H L L H H L L H L H L H L H L H L H L * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 340000H~34FFFFH 350000H~35FFFFH 360000H~36FFFFH 370000H~37FFFFH 380000H~38FFFFH 390000H~39FFFFH 3A0000H~3AFFFFH 3B0000H~3BFFFFH 3C0000H~3CFFFFH 3D0000H~3DFFFFH 3E0000H~3EFFFFH 1A0000H~1A7FFFH 1A8000H~1AFFFFH 1B0000H~1B7FFFH 1B8000H~1BFFFFH 1C0000H~1C7FFFH 1C8000H~1CFFFFH 1D0000H~1D7FFFH 1D8000H~1DFFFFH 1E0000H~1E7FFFH 1E8000H~1EFFFFH 1F0000H~1F7FFFH H H H H H H H H L L L L H H H H H H H H L L L L H H H H L L L L L L H H L L H H L H L H L H L H * * * * * * * * * * * * * * * * * * * * * * * * 2C0000H~2CFFFFH 2D0000H~2DFFFFH 2E0000H~2EFFFFH 2F0000H~2FFFFFH 300000H~30FFFFH 310000H~31FFFFH 320000H~32FFFFH 330000H~33FFFFH 160000H~167FFFH 168000H~16FFFFH 170000H~177FFFH 178000H~17FFFFH 180000H~187FFFH 188000H~18FFFFH 190000H~197FFFH 198000H~19FFFFH H H H H H H H H L L L L L L L L L L L L H H H H H H H H L L L L L L H H L L H H L H L H L H L H * * * * * * * * * * * * * * * * * * * * * * * * 240000H~24FFFFH 250000H~25FFFFH 260000H~26FFFFH 270000H~27FFFFH 280000H~28FFFFH 290000H~29FFFFH 2A0000H~2AFFFFH 2B0000H~2BFFFFH 120000H~127FFFH 128000H~12FFFFH 130000H~137FFFH 138000H~13FFFFH 140000H~147FFFH 148000H~14FFFFH 150000H~157FFFH 158000H~15FFFFH H H H H L L L L L L L L L L L L L L H H L H L H * * * * * * * * * * * * BYTE MODE 200000H~20FFFFH 210000H~21FFFFH 220000H~22FFFFH 230000H~23FFFFH WORD MODE 100000H~107FFFH 108000H~10FFFFH 110000H~117FFFH 118000H~11FFFFH
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BLOCK ADDRESS BANK # BLOCK # ADDRESS RANGE BANK ADDRESS A20 A19 A18 A17 A16 A15 A14 A13 A12 BA63 BA64 BA65 BA66 BK8 BA67 BA68 BA69 BA70 H H H H H H H H H H H H H H H H H H H H H H H H H H H H L L H H L H L H 3F8000H~3F9FFFH 3FA000H~3FBFFFH 3FC000H~3FDFFFH 3FE000H~3FFFFFH 1FC000H~1FCFFFH 1FD000H~1FDFFFH 1FE000H~1FEFFFH 1FF000H~1FFFFFH H H H H H H H H H H H H H H H H H H H H H H H H L L L L L L H H L H L H BYTE MODE 3F0000H~3F1FFFH 3F2000H~3F3FFFH 3F4000H~3F5FFFH 3F6000H~3F7FFFH WORD MODE 1F8000H~1F8FFFH 1F9000H~1F9FFFH 1FA000H~1FAFFFH 1FB000H~1FBFFFH
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TH50VSF3583AASB (bottom boot block)
BLOCK ADDRESS BANK # BLOCK # ADDRESS RANGE BANK ADDRESS A20 A19 A18 A17 A16 A15 A14 A13 A12 BA0 BA1 BA2 BA3 BK0 BA4 BA5 BA6 BA7 BA8 BA9 BA10 BK1 BA11 BA12 BA13 BA14 BA15 BA16 BA17 BA18 BK2 BA19 BA20 BA21 BA22 BA23 BA24 BA25 BA26 BK3 BA27 BA28 BA29 BA30 L L L L H H H H L L L L H H H H L L H H L H L H * * * * * * * * * * * * 140000H~14FFFFH 150000H~15FFFFH 160000H~16FFFFH 170000H~17FFFFH 0A0000H~0A7FFFH 0A8000H~0AFFFFH 0B0000H~0B7FFFH 0B8000H~0BFFFFH L L L L L L L L L L L L H H H H H H H H L L L L H H H H L L L L L L H H L L H H L H L H L H L H * * * * * * * * * * * * * * * * * * * * * * * * 0C0000H~0CFFFFH 0D0000H~0DFFFFH 0E0000H~0EFFFFH 0F0000H~0FFFFFH 100000H~10FFFFH 110000H~11FFFFH 120000H~12FFFFH 130000H~13FFFFH 060000H~067FFFH 068000H~06FFFFH 070000H~077FFFH 078000H~07FFFFH 080000H~087FFFH 088000H~08FFFFH 090000H~097FFFH 098000H~09FFFFH L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L H H H H L L L L L L L H H H H L L L L L L L L L H H L L H H L L H H L L L L H L H L H L H L H L H H H H H * * * * * * * * * * * L L H H * * * * * * * * * * * L H L H * * * * * * * * * * * 008000H~009FFFH 00A000H~00BFFFH 00C000H~00DFFFH 00E000H~00FFFFH 010000H~01FFFFH 020000H~02FFFFH 030000H~03FFFFH 040000H~04FFFFH 050000H~05FFFFH 060000H~06FFFFH 070000H~07FFFFH 080000H~08FFFFH 090000H~09FFFFH 0A0000H~0AFFFFH 0B0000H~0BFFFFH 004000H~004FFFH 005000H~005FFFH 006000H~006FFFH 007000H~007FFFH 008000H~00FFFFH 010000H~017FFFH 018000H~01FFFFH 020000H~027FFFH 028000H~02FFFFH 030000H~037FFFH 038000H~03FFFFH 040000H~047FFFH 048000H~04FFFFH 050000H~057FFFH 058000H~05FFFFH L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L H H L H L H BYTE MODE 000000H~001FFFH 002000H~003FFFH 004000H~005FFFH 006000H~007FFFH WORD MODE 000000H~000FFFH 001000H~001FFFH 002000H~002FFFH 003000H~003FFFH
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BLOCK ADDRESS BANK # BLOCK # ADDRESS RANGE BANK ADDRESS A20 A19 A18 A17 A16 A15 A14 A13 A12 BA31 BA32 BA33 BA34 BK4 BA35 BA36 BA37 BA38 BA39 BA40 BA41 BA42 BK5 BA43 BA44 BA45 BA46 BA47 BA48 BA49 BA50 BK6 BA51 BA52 BA53 BA54 BA55 BA56 BA57 BA58 BK7 BA59 BA60 BA61 BA62 H H H H H H H H L L L L H H H H L L H H L H L H * * * * * * * * * * * * 340000H~34FFFFH 350000H~35FFFFH 360000H~36FFFFH 370000H~37FFFFH 1A0000H~1A7FFFH 1A8000H~1AFFFFH 1B0000H~1B7FFFH 1B8000H~1BFFFFH H H H H H H H H L L L L H H H H H H H H L L L L H H H H L L L L L L H H L L H H L H L H L H L H * * * * * * * * * * * * * * * * * * * * * * * * 2C0000H~2CFFFFH 2D0000H~2DFFFFH 2E0000H~2EFFFFH 2F0000H~2FFFFFH 300000H~30FFFFH 310000H~31FFFFH 320000H~32FFFFH 330000H~33FFFFH 160000H~167FFFH 168000H~16FFFFH 170000H~177FFFH 178000H~17FFFFH 180000H~187FFFH 188000H~18FFFFH 190000H~197FFFH 198000H~19FFFFH H H H H H H H H L L L L L L L L L L L L H H H H H H H H L L L L L L H H L L H H L H L H L H L H * * * * * * * * * * * * * * * * * * * * * * * * 240000H~24FFFFH 250000H~25FFFFH 260000H~26FFFFH 270000H~27FFFFH 280000H~28FFFFH 290000H~29FFFFH 2A0000H~2AFFFFH 2B0000H~2BFFFFH 120000H~127FFFH 128000H~12FFFFH 130000H~137FFFH 138000H~13FFFFH 140000H~147FFFH 148000H~14FFFFH 150000H~157FFFH 158000H~15FFFFH L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L L L L L H H L L H H L H L H L H L H * * * * * * * * * * * * * * * * * * * * * * * * 1C0000H~1CFFFFH 1D0000H~1DFFFFH 1E0000H~1EFFFFH 1F0000H~1FFFFFH 200000H~20FFFFH 210000H~21FFFFH 220000H~22FFFFH 230000H~23FFFFH 0E0000H~0E7FFFH 0E8000H~0EFFFFH 0F0000H~0F7FFFH 0F8000H~0FFFFFH 100000H~107FFFH 108000H~10FFFFH 110000H~117FFFH 118000H~11FFFFH L L L L H H H H H H H H L L L L L L H H L H L H * * * * * * * * * * * * BYTE MODE 180000H~18FFFFH 190000H~19FFFFH 1A0000H~1AFFFFH 1B0000H~1BFFFFH WORD MODE 0C0000H~0C7FFFH 0C8000H~0CFFFFH 0D0000H~0D7FFFH 0D8000H~0DFFFFH
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TH50VSF3582/3583AASB
BLOCK ADDRESS BANK # BLOCK # ADDRESS RANGE BANK ADDRESS A20 A19 A18 A17 A16 A15 A14 A13 A12 BA63 BA64 BA65 BA66 BK8 BA67 BA68 BA69 BA70 H H H H H H H H H H H H H H H H L L H H L H L H * * * * * * * * * * * * 3C0000H~3CFFFFH 3D0000H~3DFFFFH 3E0000H~3EFFFFH 3F0000H~3FFFFFH 1E0000H~1E7FFFH 1E8000H~1EFFFFH 1F0000H~1F7FFFH 1F8000H~1FFFFFH H H H H H H H H H H H H L L L L L L H H L H L H * * * * * * * * * * * * BYTE MODE 380000H~38FFFFH 390000H~39FFFFH 3A0000H~3AFFFFH 3B0000H~3BFFFFH WORD MODE 1C0000H~1C7FFFH 1C8000H~1CFFFFH 1D0000H~1D7FFFH 1D8000H~1DFFFFH
2001-06-08
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TH50VSF3582/3583AASB
BLOCK SIZE TABLE
TH50VSF3582AASB (top boot block)
BLOCK # BA0~BA7 BA8~BA15 BA16~BA23 BA24~BA31 BA32~BA39 BA40~BA47 BA48~BA55 BA56~BA62 BA63~BA70 BLOCK SIZE BYTE MODE 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 8 Kbytes WORD MODE 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords BANK # BK0 BK1 BK2 BK3 BK4 BK5 BK6 BK7 BK8 BANK SIZE BLOCK COUNT BYTE MODE 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 448 Kbytes 64 Kbytes WORD MODE 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 224 Kwords 32 Kwords 8 8 8 8 8 8 8 7 8
TH50VSF3583AASB (bottom boot block)
BLOCK # BA0~BA7 BA8~BA14 BA15~BA22 BA23~BA30 BA31~BA38 BA39~BA46 BA47~BA54 BA55~BA62 BA63~BA70 BLOCK SIZE BYTE MODE 8 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes WORD MODE 4 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords BANK # BK0 BK1 BK2 BK3 BK4 BK5 BK6 BK7 BK8 BANK SIZE BLOCK COUNT BYTE MODE 64 Kbytes 448 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes WORD MODE 32 Kwords 224 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 256 Kwords 8 7 8 8 8 8 8 8 8
2001-06-08
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TH50VSF3582/3583AASB
ABSOLUTE MAXIMUM RATINGS
SYMBOL VCC VIN VDQ Topr PD Tsolder IOSHORT NEW Tstg PARAMETER VCCs/VCCf Supply Voltage Input Voltage
(1)
RANGE -0.3~4.2 -0.3~4.2 -0.5~VCC + 0.5 ( 4.2) -30~85 0.6 260 100 100,000 -55~125
UNIT V V V C W C mA Cycle C
Input/Output Voltage Operating Temperature Power Dissipation Soldering Temperature (10 s) Output Short Circuit Current
(2)
Erase/Program Cycling Capability Storage Temperature
(1) -2.0 V for pulse width 20 ns (2) Output shorted for no more than one second. No more than one output shorted at a time
HARDWARE STATUS FLAGS
STATUS Auto Programming Read in Program Suspend
(1)
DQ7
DQ 7
DQ6 Toggle Data Toggle Toggle Toggle Toggle 1 Data Toggle Toggle Toggle Toggle Toggle
DQ5 0 Data 0 0 0 0 0 Data 0 0 1 1 1
DQ3 0 Data 0 0 1 1 0 Data 0 0 0 1 0
DQ2 1 Data Toggle 1 Toggle 1 Toggle Data Toggle 1 1 N/A N/A
RY/BY 0 Hi-Z 0 0 0 0 Hi-Z Hi-Z 0 0 0 0 0
Data Selected
(2) (3)
0 0 0 0 1 Data
DQ 7 DQ 7 DQ 7
Erase Hold Time In AutoErase In Progress Auto-Erase Selected
Non-Selected
Non-Selected Selected Read In Erase Suspend Programming Non-Selected Auto Programming Time Limit Exceeded Auto-Erase Programming in Erase Suspend Non-Selected Selected
0
DQ 7
Notes: DQ outputs cell data and RY/BY to high impedence when the operation has completed. DQ0 and DQ1 pins are reserved for futyre use. DQ0, DQ1 and DQ4 output 0. (1) Data output from an address to which Write is being performed are undefined. (2) Output when the block address selected for Auto Block Erase is specified and data is read from there. During Auto Chip Erase, all blocks are selected. (3) Output when a block address not selected for Auto Block Erase of same bank as selected block is specified and data is read from there.
2001-06-08
13/50
TH50VSF3582/3583AASB
RECOMMENDED DC OPERATING CONDITIONS (Ta = -30~85C)
SYMBOL VCCs/VCCf VIH VIL VDH VLKO VACC VID PARAMETER Power Supply Voltage Input High-Level Voltage Input Low-Level Voltage Data Retention Voltage for SRAM Flash Low-Lock Voltage High Voltage for WP/ACC High Voltage for RESET MIN 2.67 2.2 -0.3
(1)
TYP.
MAX 3.3 VCC + 0.3 VCC x 0.2 3.3 2.5 9.5 12.6
UNIT
1.5 2.3 8.5 11.4
V
(1) -2.0 V for pulse width 20 ns
CAPACITANCE (Ta = 25C, f = 1 MHz)
SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance CONDITION VIN = GND VOUT GND = MIN TYP. MAX 15 20 UNIT pF pF
Note: These parameters are sampled periodically and are not tested for every device.
2001-06-08
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TH50VSF3582/3583AASB
DC CHARACTERISTICS (Ta = -30~85C, VCCs/VCCf = 2.67 V~3.3 V)
SYMBOL IIL IILW ISOH ISOL IFOH1 IFOH2 IFOL ILO ICCO1 ICCO2 PARAMETER Input Leakage Current Input Leakage Current ( WP/ACC pin) SRAM Output High Current SRAM Output Low Current VIN = 0 V~VCC 0 V VIN VCC VOH = VCCs - 0.5 V VOL = 0.4 V CONDITION MIN -0.5 2.1 -0.4 -2.5 -100 4 tcycle = tRC tcycle = 1 MHz tcycle = tRC tcycle = 1 MHz Ta = 25C Ta = -30~85C Ta = 25C VCCs = 3.0 V Ta = -30~40C Ta = -30~85C IACC High Voltage Input Current for WP/ACC 8.5 V VACC 9.5 V TYP. 0.01 MAX UNIT 1 10 1 30 A A mA mA mA mA A mA A mA
Flash Output High Current (TTL) VOH = 2.4 V Flash Output High Current (CMOS) Flash Output Low Current Output Leakage Current Flash Average Read Current Flash Average Program/ Erase Current VOH = VCCf x 0.85 VOH = VCCf - 0.4 V VOL = 0.4 V VOUT = 0 V~VCC, OE = VIH
CEF = VIL, OE = VIH, IOUT = 0 mA, tcycle = tRC(min) CEF = VIL, OE = VIH, IOUT = 0 mA CE1S = VIL, CE2S = VIH, OE = VIH, IOUT = 0 mA CE1S = 0.2 V, OE = VCCs - 0.2 V, CE2S = VCCs - 0.2 V, IOUT = 0 mA
15 50
mA
ICCO3 SRAM Average Operating Current ICCO4 Flash Average Read-While-Program Current Flash Average Read-While- Erase Current Flash Average Program-WhileErase-Suspend Current Flash Standby Current Flash Standby Current (1) (Automatic Sleep Mode )
mA 10 45 mA 5 45 mA
ICCO5 ICCO6 ICCO7 ICCS1 ICCS2 ICCS3
VIN = VIH/VIL, IOUT = 0 mA, tcycle = tRC(min) VIN = VIH/VIL, IOUT = 0 mA, tcycle = tRC(min) VIN = VIH/VIL, IOUT = 0 mA
CEF = RESET = VCCf or RESET = VSS
45
mA
15 10 10 2 1 10 0.5 1 5 20
mA A A mA
VIH = VCCf or VIL = VSS
CE1S = VIH or CE2S = VIL
VCCs = 3.3 V SRAM Standby Current ICCS4
CE1S = VCCs - 0.2 V (2) or CE2S = 0.2 V
A
mA
(1) The device is going to Automatic Sleep Mode, when address remain steady during 150 ns. (2) In Standby Mode, with CE1S VCCs - 0.2 V, these limits are guaranteed when CE2S VCCs - 0.2 V or CE2S 0.2 V and CIOS VCCs - 0.2 V or CIOS 0.2 V.
2001-06-08
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TH50VSF3582/3583AASB
AC CHARACTERISTICS (SRAM) (Ta = -40~85C, VCCs = 2.7 V~3.6 V)
Read cycle
SYMBOL tRC tACC tCO1 tCO2 tOE tBA tCOE tOEE tBE tOD tODO tBD tOH tCCR Read Cycle Time Address Access Time Chip Enable ( CE1S ) Access Time Chip Enable (CE2S) Access Time Output Enable Access Time Data Byte Control Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Data Byte Control Low to Output Active Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Data Byte Control High to Output Hi-Z Output Data Hold Time CE Recovery Time PARAMETER MIN 70 5 0 0 10 0 MAX 70 70 70 35 35 30 30 30 ns UNIT
Write cycle
SYMBOL tWC tWP tCW tBW tAS tWR tODW tOEW tDS tDH Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Byte Control to End of Write Address Set-up Time Write Recovery Time WE Low to Output Hi-Z WE High to Output Active Data Set-up Time Data Hold Time PARAMETER MIN 70 50 60 50 0 0 0 30 0 MAX 30 ns UNIT
AC TEST CONDITIONS
PARAMETER Input Pulse Level Input Pulse Rise and Fall Time (10%~90%) Timing Measurement Reference Level (input) Timing Measurement Reference Level (output) Output Load VALUES 0.4 V, 2.4 V 5 ns VCCs x 0.5 VCCs x 0.5 CL (100 pF) + 1 TTL gate
2001-06-08
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TH50VSF3582/3583AASB
AC CHARACTERISTICS (FLASH MEMORY)
READ CYCLE
LOAD CAPACITANCE SYMBOL PARAMETER MIN tRC tACC tCE tOE tCEE tOEE tOEH tOH tDF1 tDF2 Read Cycle Time Address Access Time
CEF Access Time OE Access Time CEF to Output Low-Z OE to Output Low-Z OE Hold Time
30pF MAX 70 70 30 30 20 MIN 0 0 0 0
100pF MAX 80 80 80 35 25 25
UNIT
70 0 0 0 0
ns ns ns ns ns ns ns ns ns ns
Output Data Hold Time
CEF to Output Hi-Z OE to Output Hi-Z
BLOCK PROTECT
SYMBOL tVPS tCESP tVPH tPPLH VID Set-up Time
CEF Set-up Time OE Hold Time
PARAMETER
MIN 4 4 4 100
MAX
UNIT s s s s
WE Low-Level Hold Time
PROGRAM AND ERASE CHARACTERISTICS
SYMBOL Auto-Program Time (Byte Mode) tPPW Auto-Program Time (Word Mode) tPCEW tPBEW tEW *: typ. Auto Chip Erase Time Auto Block Erase Time Erase/Program Cycle 11* 50* 0.7* 10
5
PARAMETER
MIN 8*
MAX 300 300 710 10
UNIT s s s s Cycles
2001-06-08
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TH50VSF3582/3583AASB
COMMAND WRITE/PROGRAM/ERASE CYCLE
LOAD CAPACITANCE SYMBOL PARAMETER MIN tCMD tAS tAH tAHW tDS tDH tWELH tWEHH tCES tCEH tCELH tCEHH tWES tWEH tOES tOEHP tOEHT tBEH tVCS tBUSY tRP tREADY tRB tRH tCEBTS tSUSP tRESP tSUSE tRESE Command Write Cycle Time Address Set-up Time / BYTE Set-up Time Address Hold Time / BYTE Hold Time Address Hold Time from WE High level Data Set-up Time Data Hold Time WE Low-Level Hold Time WE High-Level Hold Time
CEF Set-up Time to WE Active
30pF MAX 90 20 1.5 1 15 1 MIN 80 0 40 20 40 0 40 20 0 0 40 20 0 0 0 90 20 50 500 500 0 50 5
100pF MAX 90 20 1.5 1 15 1
UNIT
70 0 40 20 40 0 ( WE Control) ( WE Control) ( WE Control) 40 20 0 0 40 20 0 0 0 90 20 50 500 500 0 50 5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s ns ns s ns ns ns s s s s
CEF Hold Time from WE High Level ( WE Control) CEF Low-Level Hold Time CEF High-Level Hold Time
( CEF Control) ( CEF Control) ( CEF Control)
WE Set-up time to CEF Active
WE Hold Time from CEF High Level ( CEF Control)
OE Set-up Time OE Hold Time (Toggle, Data Polling) OE High-Level Hold Time (Toggle)
Erase Hold Time VCCf Set-up Time Program/Erase Valid to RY/BY Delay
RESET Low-Level Hold Time RESET Low-Level to Read Mode
RY/BY Recovery Time
RESET Recovery Time CEF Set-up time BYTE Transition
Program Suspend Command to Suspend Mode Program Resume Command to Program Mode Erase Suspend Command to Suspend Mode Erase Resume Command to Erase Mode
2001-06-08
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TH50VSF3582/3583AASB
SIMULTANEOUS READ/WRITE OPERATION
The TH50VSF3582/3583AASB features a Simultaneous Read/Write operation. The Simultaneous Read/Write operation enables the device to simultaneously write data to or erase data from a bank while the device reads data from another bank. The TH50VSF3582/3583AASB has a total of nine banks: 0.5 Mbits x 1 bank, 3.5 Mbits x 1 bank, and 4 Mbits x 7 banks. Banks are switched using bank addresses (A20 to A15). For bank blocks and addresses, refer to the Block Address Table and Block Size Table. The Simultaneous Read/Write operation cannot perform multiple operations in a bank. The table below shows the operating modes in which simultaneous operation can be performed. Note that during Auto Program execution or Auto Block Erase operation, the Simultaneous Read/Write operation cannot read data from addresses which are not selected for operation in the same bank. Data from such addresses can be read using the Program Suspend or Erase Suspend function.
SIMULTANEOUS READ/WRITE OPERATION
ONE BANK STATUS Read mode ID Read mode
(1)
OTHER BANK STATUS
Auto Program mode Fast Program mode
(2)
Program Suspend mode Read mode Auto Block Erase mode Auto Multiple Block Erase mode Erase Suspend mode Program Suspend while Erase Suspend CFI mode (1) Command mode only is valid. (2) Includes when Acceleration mode is in use. (3) If the selected bank exists in all banks, simultaneous operation is not supported.
(3)
OPERATING MODES
In addition to Read, Write, and Erase modes, the TH50VSF3582/3583AASB features many functions including Block Protect and Data Polling. When using the device, reference the timing charts and flow charts together with the description below.
Read Mode
To read data from the memory cell array, set the device to Read mode. In Read mode, the device can perform high-speed random access as asynchronous ROM. The device is automatically set to Read mode immediately after power on or after completion of automatic operation. A software reset releases ID Read mode and the lock state when automatic operation ends abnormally, and sets to Read mode. A hardware reset terminates operation of the device and resets to Read mode. When reading the data without changing the address immediately after power on, either input a hardware reset or change CEF from H to L.
2001-06-08
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TH50VSF3582/3583AASB
ID Read Mode
ID Read mode is used to read the device maker code and device code. The mode is useful for EPROM programmers to automatically identify the device type. In this method, simultaneous operation can be performed. Inputting an ID Read command sets the specified bank to ID Read mode. Banks are specified by inputting the bank address (BK) in the third bus write cycle of the command cycle. To read an ID code, the bank address as well as the ID read address must be specified. From address BK + 00 the maker code is output; from address BK + 01 the device code is output. From other banks, data are output from the memory cells. Inputting a Reset command releases ID Read mode and returns the device to Read mode. Access time in ID Read mode is the same as that in Read mode. For the codes, see the ID Code Table.
Standby Mode
There are two methods of entering Standby mode. (1) Control using CEF and RESET When the device is in Read mode, input VDD 0.3 V to CEF and RESET . The device enters Standby mode and the current becomes standby current (ICCS1). However, if the device is in simultaneous operation, the device does not enter Standby mode but causes the operating current to flow. (2) Control using only RESET When the device is in Read mode, input VSS 0.3 V to RESET . The device enters Standby mode and the current becomes standby current (ICCS1). Even if the device is in simultaneous operation, this method can terminate the current operation and set the device to Standby mode. This is a hardware reset, described later. In standby mode, DQ is put in high-impedance state.
Auto Sleep Mode
Function which suppresses power dissipation during read. When address input does not change for 150 ns or longer, the device automatically enters Sleep mode and the current becomes standby current (ICCS1). However, if the device is in simultaneous operation, the device does not enter Standby mode but causes the operating current to flow. Because the output data are latched, data are output in Sleep mode. When the address is changed, Sleep mode is automatically released, outputting data from the changed address.
Output Disable Mode
Inputting VIH to OE disables output from the device, setting DQ to high-impedance.
2001-06-08
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TH50VSF3582/3583AASB
Command Write
The TH50VSF3582/3583AASB utilizes the JEDEC command control standard for a single power supply E2PROM. A Command is executed by inputting an address and data into the Command register. The Command is written by inputting a pulse to WE with CEF = VIL and OE = VIH ( WE control). The command can also be written by inputting a pulse to CEF with WE = VIL ( CEF control). The address is latched on the falling edge of either WE or CEF . The data is latched on the rising edge of either WE or CEF . DQ0 to DQ7 are valid for data input and DQ8 to DQ15 are ignored. To cancel input of the command sequence mid-way, use the Reset command. The device resets the Command register and enters Read mode. When an undefined command is input, the Command register is reset and the device enters Read mode.
Software Reset
Apply a software reset by inputting a Read/Reset command. Software reset returns the device from ID Read or CFI mode to Read mode, releases the lock state when automatic operation ends abnormally, or clears the Command register.
Hardware Reset
A hardware reset initializes the device and sets it to Read mode. When a pulse is input to RESET for tRP, the device ends the operation in progress and enters Read mode after tREADY. Note that if a hardware reset is applied during data overwrite such as a Write or Erase operation, data at that address or block become undefined. After a hardware reset the device enters Read mode when RESET = VIH and Standby mode when RESET = VIL. The DQ pins are High-Impedance when RESET = VIL. The Read operation sequence and input of any command are allowed after the device enters Read mode.
Comparison with Software Reset and Hardware Reset
ACTION Release ID Read or CFI mode Clear the Command resister Release the lock state when automatic operation ends abnormally Stop automatic operation in progress All stops of operation other than the above, and return to Read mode SOFTWARE RESET Valid Valid Valid Invalid Invalid HARDWARE RESET Valid Valid Valid Valid Valid
BYTE/WORD Mode
CIOF is used select Word mode (16 bits) or Byte mode (8 bits) for the TH50VSF3582/3583AASB. When VIH is input to CIOF, the device operates in Word mode. Read data or write commands using DQ0 to DQ15. When VIL is input to CIOF, read data or write commands using DQ0 to DQ7. A12F is used as the lowest address. DQ8 to DQ14 become high-impedance.
2001-06-08
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TH50VSF3582/3583AASB
Auto-Program Mode
The TH50VSF3582/3583AASB can be programmed in either byte or word units. The Auto Program mode is set using the Program command. The program address is latched on the falling edge of the WE signal and data is latched on the rising edge of the fourth bus cycle (with WE control). Auto programming starts on the rising edge of the WE signal in the fourth bus cycle. The Program and Program Verify commands are automatically executed by the chip. The device status during programming is determined from the Hardware Sequence flag. To read the Hardware Sequence flag, specify the address to which Write is being performed. During Auto Program execution, a command sequence for the bank on which execution is being performed cannot be received. To terminate execution, use a hardware reset. Note that when the operation is terminated, data cannot be correctly written. Programming of a protected block is ignored. The device enters Read mode 3 s after the rising edge of the WE signal in the fourth bus cycle. If an Auto Program operation fails, the device remains in programming state and does not automatically return to Read mode. The device status can be determined from the setting of the Hardware Sequence flag. Either a Reset command or a hardware reset is necessary to return the device to Read mode after a failure. If a programming operation fails, please do not try to use the block which contains the address to which data could not be programmed. The device allows the programming of memory cells from 1 to 0. The programming of Memory cells from 0 to 1 will fail. At this time, execution of Auto Program fails. This indicates that the failure is due to the usage rather than the device. A cell must be erased to turn it from 0 to 1.
Fast Program Mode
Fast Program is a function which enables execution of the command sequence for the Auto Program in two cycles. In this mode the first two cycles of the command sequence, which normally needs four cycles, are omitted. Write is performed in the remaining two cycles. To execute Fast Program, input the Fast Program set command. Write in this mode uses the Fast Program command but operation is the same at that for ordinary Auto Program. The status of the device can be checked using the hardware sequence flag and read operations can be performed as usual. To exit this mode, the Fast Program Reset command must be input. When the command is input, the device returns to Read mode.
Acceleration Mode
The TH50VSF3582/3583AASB features Acceleration mode for reducing write time. Applying VACC to WP or ACC automatically sets the device to Acceleration mode. In Acceleration mode, Block Protect mode changes to Temporary Block Unprotect mode. Write mode changes to Fast Program mode. Modes are switched by the WP/ACC signal; thus, there is no need for a Temporary Block Unprotect operation or for setting or resetting Fast Program mode. Operation of Write is the same as that in Auto Program mode. Releasing VACC to WP/ACC ends Acceleration mode.
2001-06-08
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TH50VSF3582/3583AASB
Program Suspend / Resume Mode
Program Suspend is used to enable Data Read by suspending Write operation. The device receives a Program Suspend command in Write mode (including Write performed during Erase Suspend) but ignores the command in other modes. At command input, the address of the bank on which Write is being performed must be specified. After command input, the device enters Program Suspend Read mode after tSUSP. During Program Suspend, Cell Data Read, ID Read and CFI Data Read can be performed. When Data Write is suspended, the address to which Write was being performed becomes undefined. ID Read and CFI Data Read are the same as usual. After completion of Program Suspend, to return to Write mode, input a Program Resume command. At command input, specify the address of the bank on which Write is being performed. When the ID Read and CFI Data Read functions are used, end the functions before inputting the Resume command. On receiving the Resume command, the device returns to Write mode and resumes output of a Hardware Sequence flag from the bank to which data are being written. Program Suspend can be run in Fast Program or Acceleration mode. However, note that when running Program Suspend in Acceleration mode, do not release VACC.
Auto Chip Erase Mode
The Auto Chip Erase mode is set using the Chip Erase command. The Auto Chip Erase operation starts on the rising edge of WE in the sixth bus cycle. All memory cells are automatically preprogrammed to 0, erased and verified as erased by the chip. The device status is determined from the Hardware Sequence flag. Command inputs are ignored during an Auto Chip Erase. The hardware reset allows interruption of an Auto Chip Erase operation. The Auto Chip Erase operation does not complete correctly when interrupted. Hence a further Erase operation is necessary. An attempt to erase a protected block is ignored. If all blocks are protected, the Auto Erase operation will not be executed and the device will enter Read mode 100 s after the rising edge of the WE signal in the sixth bus cycle. If an Auto Chip Erase operation fails, the device remains in, erasing state and does not return to Read mode. The device status is determined from the Hardware Sequence flag. Either a Reset command or a hardware reset is necessary to return the device to Read mode after a failure. In this case, the block in which a failure occurred cannot be detected. Either terminate device usage, or perform Block Erase for each block, specify the failed block, and stop using it. The host processor must take measures to prevent use of the failed block being used in the future.
2001-06-08
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TH50VSF3582/3583AASB
Auto Block / Multiple Block Erase Mode
The Auto Block and Multiple Block Erase modes are set using the Block Erase command. The block address is latched on the falling edge of the WE signal in the sixth bus cycle. The Block Erase starts as soon as the erase hold time (tBEH) has elapsed after the rising edge of the WE signal. To erase multiple blocks, repeat the 6th bus write cycles and input the block addresses and the Auto Block Erase command within the erase hold time (Auto Multiple Block Erase). If a command sequence other than Auto Block Erase or Erase Suspend command is input during the erase hold time, the device resets the Command register and enters Read mode. The erase hold time is valid every WE rising edge. Once operation starts, all the memory cells in the block selected in the device are automatically preprogrammed to data 0, erased, and Erase is verified. The device status can be determined from the setting of the Hardware Sequence flag. To read the Hardware Sequence flag, the addresses of blocks on which Auto Erase is being performed must be specified. When the selected blocks exit in all the banks, simultaneous operation cannot be performed. Commands (except Erase Suspend) are ignored during a Block/Multiple Block Erase operation. The operation can be aborted by a hardware reset. The Auto Erase operation does not complete correctly when aborted, therefore, a further Erase operation is necessary. An attempt to erase a protected block is ignored. If all the selected blocks are protected, the Auto Erase operation is not executed and the device returns to Read mode 100 s after the rising edge of the WE signal in the last bus cycle. If an Auto Erase operation fails, the device remains in erasing state and does not return to Read mode. The device status is determined from the Hardware Sequence flag. Either a Reset command or a Hardware reset is necessary to return the device to Read mode after a failure. If multiple blocks are selected, the block in which a failure occurred cannot be detected. Either terminate device usage, or perform Block Erase for each block, specify the failed block, and stop using it. The host processor must take measures to prevent use of the failed block being used in the future.
Erase Suspend / Resume Mode
Erase Suspend Mode suspends Auto Block Erase and reads data from or writes data to an unselected block. The Erase Suspend command is allowed during an auto block erase operation but is ignored in all other oreration modes. The Erase Suspend command is inhibited to input during the Erase Hold Time. When the command is input, the address of the bank on which Erase is being performed must be specified. In Erase Suspend Mode only a Read, Program or Resume command can be accepted. If an Erase Suspend command is input during an Auto Block Erase, the device will enter Erase Suspend Read Mode after tSUSE. The device status (Erase Suspend Read Mode) can be verified by checking the Hardware Sequence flag. If data is read consecutively from the block selected for Auto Block Erase, the DQ2 output will toggle and the DQ6 output will stop toggling and RY/ BY will be set to High-Impedance. Inputting a Write command during an Erase Suspend enables a Write to be performed to a block which has not been selected for the Auto Block Erase. Data is written in the usual manner. To resume the Auto Block Erase, input an Erase Resume command. On input of the command, the address of the bank on which the Write was being performed must be specified. On receiving an Erase Resume command, the device returns to the state it was in when the Erase Suspend command was input. If an Erase Suspend command is input during the Erase Hold Time, the device will return to the state it was in at the start of the Erase Hold Time. At this time more blocks can be specified for erasing. If an Erase Resume command is input during an Auto Block Erase, Erase resumes. At this time toggle output of DQ6 resumes and 0 is output on RY/ BY .
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TH50VSF3582/3583AASB
Block Protect
Block Protection is a function to disable write and erase in block units. Applying VID to RESET and inputting the Block Protect command performs block protection. The first cycle of the command sequence is the Setup command. In the second cycle, the Block Protect command is input, in which a block address and A1 = VIH and A0 = A6 = VIL are input. At this time, the device writes to the block protector circuit, Until write is complete, there must be a wait of tPPLH but the device need not be controlled during this time. In the third cycle, the Verify Block Protect command is input. This command verifies write to the block protector circuit. Read is performed in the fourth cycle. If the protection operation is complete, 01H is output. If other than 01H is output, write is not complete; thus, input the Block Protect command again. Canceling VID to RESET exits this mode.
Temporary Block Unprotection
The TC58VSF3580/3581AASB has a temporary block unprotection feature which disables block protection for all protected blocks. Unprotection is enabled by applying VID to the RESET pin. At this time, Write and Erase operations can be performed on all the blocks except the boot blocks protected by Boot Block Protect. The device returns to the previous condition after VID is removed from the RESET pin. That is, previously protected blocks are protected again.
Verify Block Protect
The Verify Block Protect command is used to ascertain whether a block is protected or unprotected. This mode is set by setting A0, A6 and the block address A19~A12 to VIL and setting A1 to VIH. This command should be input before a Read operation is performed. 0001H is output if the block is protected and 0000H is output if the block is unprotected. In Byte Mode DQ8 to DQ15 are in High-Impedance state. Block protection verification can also be carried out using a software command.
Boot Block Protection
Boot Block Protection temporarily protects some boot blocks using a method other than ordinary block protection. VID or a command sequence is not required. Protection is performed simply by inputting VIL to WP/ACC . The target blocks are two of the boot blocks. The Top Boot Block uses BA69/BA70; the Bottom Boot Block, BA0/BA1. Inputting VIH to WP/ACC releases the mode. At this time, the block is protected in ordinary block protection mode.
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TH50VSF3582/3583AASB
Hidden Rom Area
The TH50VSF3582/3583AASB features a 64-Kbyte Hidden ROM area apart from the memory cells. The area consists of one block. Data Read, Write, and Protect can be performed on the block. Because Protect cannot be released, once the block is protected, data in the block cannot be overwritten. The Hidden ROM area is located in the address space indicated in the Hidden ROM Area Address Table. Normally, memory cell data are accessed. To access the Hidden ROM area, input a Hidden ROM mode Entry command. At this time, the device enters Hidden ROM mode, allowing Read, Write, Erase, and Block Protect. Write and Erase operations are the same as Auto operations except that the device is in Hidden ROM mode. To protect the Hidden ROM area, use the Block Protect function. Operation of Block Protect here is the same as in normal Block Protect except that VIH rather than VID is input to RESET . Once the block is protected, protection cannot be released even using a Temporary Block Unprotect function. Use Block Protect carefully. Note that in Hidden ROM mode, simultaneous operation cannot be performed. Therefore, do not access areas other than the Hidden ROM area. To exit Hidden ROM mode, use the Hidden ROM Mode Exit command. The device returns to Read mode.
Hidden Rom Area Address Table
TYPE BOOT BLOCK ARCHITECTURE TOP BOOT BLOCK BOTTOM BOOT BLOCK BYTE MODE ADDRESS RANGE 3F0000H~3FFFFFH 000000H~00FFFFH SIZE 64 Kbytes 64 Kbytes WORD MODE ADDRESS RANGE 1F8000H~1FFFFFH 000000H~007FFFH SIZE 32 Kwords 32 Kwords
TH50VSF3582AASB TH50VSF3583AASB
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TH50VSF3582/3583AASB
Common Flash Memory Interface (CFI)
The TH50VSF3582/3583AASB conforms to the CFI. Information on device specifications and characteristics can be obtained via CFI. To read information from the device, input the Query command followed by the address. In Word mode, DQ8 to DQ15 all output 0s. To exit this mode, input the Reset command.
CFI Code Table
ADDRESS A6~A0 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH DATA DQ15~DQ0 0051H 0052H 0059H 0002H 0000H 0040H 0000H 0000H 0000H 0000H 0000H DESCRIPTION
Query Unique ASCII string "QRY"
Primary OEM Command Set 2: AMD/FJ standard type Address for Primary Extended Table Alternate OEM Command Set 0: none exists Address for Alternate OEM Extended Table VDD Min (write/erase) DQ7~DQ4: 1 V DQ3~DQ0: 100 mV VDD Max (write/erase) DQ7~DQ4: 1 V DQ3~DQ0: 100 mV VPP Min voltage VPP Max voltage Typical timeout per single byte/word write (2 s) Typical timeout for Min size buffer write (2 s) Typical timeout per individual block erase (2 ms) Typical timeout for full chip erase (2 ms) Max timeout for byte/word write (2 times typical) Max timeout for buffer write (2 times typical) Max timeout per individual block erase (2 times typical) Max timeout for full chip erase (2 times typical) Device Size (2 byte) Flash Device Interface description 2: x8/x16 Max number of byte in multi-byte write (2 )
N N N N N N N N N N
1BH
0027H
1CH
0036H
1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH
0000H 0000H 0004H 0000H 000AH 0000H 0005H 0000H 0004H 0000H 0016H 0002H 0000H 0000H 0000H
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TH50VSF3582/3583AASB
ADDRESS A6~A0 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 40H 41H 42H 43H 44H DATA DQ15~DQ0 0002H 0007H 0000H 0020H 0000H 003EH 0000H 0000H 0001H 0050H 0052H 0049H 0031H 0031H DESCRIPTION Number of Erase Block Region within device Erase Block Region 1 Information 0~15 bit: y = Block Number 16~31 bit: z = Block Size (z x 256 byte)
Erase Block Region 2 Information
Query Unique ASCII string "PRI"
Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock 0: Required 1: Not Required Erase Suspend 0: Not Supported 1: To Read Only 2: To Read & Write Block Protect 0: Not Supported X: Number of blocks in per group Block Temporary Unprotect 0: Not Supported 1: Supported Block Protect/Unprotect scheme Simultaneous Operation 0: Not Supported 1: Supported Burst Mode 0: Not Supported Page Mode 0: Not Supported VACC Min voltage DQ7~DQ4: 1 V DQ3~DQ0: 100 mV VACC Max voltage DQ7~DQ4: 1 V DQ3~DQ0: 100 mV Top/Bottom Boot Block Flag 2: TH50VSF3582AASB 3: TH50VSF3583AASB Program Suspend 0: Not Supported 1: Supported
45H
0000H
46H
0002H
47H
0001H
48H
0001H
49H
0004H
4AH
0001H
4BH
0000H
4CH
0000H
4DH
0085H
4EH
0095H
4FH
000XH
50H
0001H
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TH50VSF3582/3583AASB
HARDWARE SEQUENCE FLAGS FOR FLASH MEMORY
The TH50VSF3582/3583AASB has a Hardware Sequence flag which allows the device status to be determined during an auto mode operation. The output data is read out using the same timing as that used when CEF = OE = VIL in Read Mode. The RY/ BY output can be either High or Low. The device re-enters Read Mode automatically after an auto mode operation has been completed successfully. The Hardware Sequence flag is read to determine the device status and the result of the operation is verified by comparing the read-out data with the original data.
DQ7 ( DATA polling)
During an Auto-Program or auto-erase operation, the device status can be determined using the data polling function. DATA polling begins on the rising edge of WE in the last bus cycle. In an Auto-Program operation, DQ7 outputs inverted data during the programming operation and outputs actual data after programming has finished. In an auto-erase operation, DQ7 outputs 0 during the erase operation and 1 when the erase operation has finished. If an auto mode operation fails, DQ7 simply outputs the data. When the operation has finished, the address latch is reset. Data polling is asynchronous with the OE signal.
DQ6 (Toggle bit 1)
The device status can be determined by the Toggle Bit function during an Auto Program or Auto Erase operation. The Toggle bit begins toggling on the rising edge of WE in the last bus cycle. DQ6 alternately outputs a 0 or a 1 for each attempt ( OE access) while CEF = VIL while the device is busy. When the internal operation has been completed, toggling stops and valid memory cell data can be read by subsequent reading. If the operation failed, the DQ6 output toggles. DQ6 toggles for around 3 s when an attempt is made to execute an Auto Program operation on a protected block. It then stops toggling. DQ6 toggles for around 100 s when an attempt is made to execute an Auto Erase operation on a protected block. It then stops toggling. After toggling stops the device returns to Read mode.
DQ5 (internal time-out)
DQ5 outputs a 1 when the Internal Timer has timed out during a Program or Erase operation. This indicates that the operation has not completed within the allotted time. An attempt to program 1 into a cell containing 0 will fail (see Auto Program mode). DQ5 outputs 1 in this case. Either a hardware reset or a software reset command is required to put the device into Read mode.
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TH50VSF3582/3583AASB
DQ3 (Block Erase timer)
The Block Erase operation starts 50 s (Erase Hold Time) after the rising edge of WE in the last command cycle. DQ3 outputs a 0 during the Block Erase Hold Time and a 1 when the Erase operation starts. Additional Block Erase commands can only be accepted during this Block Erase Hold Time. Each Block Erase command received within this hold time resets the timer, allowing additional blocks to be marked for erasing. DQ3 outputs a 1 if the Program or Erase operation fails.
DQ2 (Toggle bit 2)
DQ2 is used to detect blocks for Auto Block Erase or to detect whether the device is in Erase Suspend mode. During Auto Block Erase, if data are continuously read from the selected block, DQ2 output toggles. At this time 1 is output from non-selected blocks; thus, the selected block can be detected. When the device is in Erase Suspend mode, if data are continuously read from the selected block for Auto Block Erase, DQ2 output toggles. At this time, because DQ6 output does not toggle, Erase Suspend mode can be detected. When the device is in Programming mode during Erase suspend, if data are read from the address to which data are being written, DQ2 outputs 1.
RY/BY (READY / BUSY )
The TH50VSF3582/3583AASB has a RY/ BY signal to indicate the device status to the host processor. A 0 (Busy state) indicates that an Auto Program or Auto Erase operation is in progress. A 1 (Ready state) indicates that the operation has finished and that the device can accept a new command. The RY/ BY signal outputs a 0 when an operation has failed. The RY/ BY signal outputs a 0 after the rising edge of WE in the last command cycle. During an Auto Block Erase operation, commands other than Erase Suspend are ignored. The RY/ BY signal outputs a 1 during an Erase Suspend operation. The output buffer for the RY/ BY pin is an open drain type circuit, allowing a wired OR connection. A pull-up resistor needs to be inserted between VCC and the RY/ BY pin.
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TH50VSF3582/3583AASB
DATA PROTECTION
The TH50VSF3582/3583AASB features a function which makes malfunction or data damage difficult.
Protection Against Program/Erase Caused by Low Supply Voltage
To prevent malfunction at power on or power down, the device does not receive commands when VCCf is below VLKO. In this state, command input is ignored. If VCCf drops below VLKO during Auto operations, the device terminates Auto Program execution. In this case, Auto operation is not executed again when VCCf return to recommended VCCf voltage Therefore, command need to be input to execute Auto operation again. When VCCf > VLKO, make up countermeasure to be input accurately command in system side please.
Protection Against Malfunction Caused by Glitches
To prevent malfunction caused by noise from the system in operation, the device does not receive pulses shorter than 3 ns(Typ.) input to WE , CEF , or OE . However, if a glitch exceeding 3 ns(Typ.) occurs and the glitch is input to the device, although rare, malfunction may occur. The device uses standard JEDEC commands; thus making command input difficult. It is conceivable that in an extreme case a part of a command sequence input due to system noise may occur. At this time, the device acknowledges the part of the command sequence. Then, even if the proper command is input, the device does not operate. To avoid this, before command input, clear the Command register. In an environment where system noise occurs easily, Toshiba recommends input of a software or hardware reset before command input.
Protection Against Malfunction at Power-on
To prevent damage to data caused by sudden noise at power on, when power is turned on with WE = CEF = VIL and OE = VIL, the device does not latch the command at the first rising edge of WE or CEF . The device automatically resets the Command register and enters Read mode.
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TH50VSF3582/3583AASB
TIMING DIAGRAMS
VIH or VIL Data Invalid
FLASH READ/ID READ OPERATION
tRC
Address tACC tCE
CEF
tOH
tOE tOEE
OE
tDF1
tCEE
tDF2
WE tOEH
DOUT
Hi-Z
Valid Data Out
Hi-Z
SRAM READ CYCLE (see Note 1)
tRC
Address tACC tOH
CE2S
tCO2 tCO1
tOD
CE1S
tOE
tOD
OE
tBA tBE
UB , LB
tODO
tOEE tCOE DOUT Hi-Z tCOE
tBD
Valid Data Out
Hi-Z
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TH50VSF3582/3583AASB
SRAM WRITE CYCLE 1 ( WE -CONTROLLED) (see Note 4)
tWC Address tAS WE tCW CE2S tCW
CE1S
tWP
tWR
tBW
UB , LB
tODW DOUT See Note 2 Hi-Z tDS DIN See Note 5
tOEW See Note 3 tDH See Note 5
Valid Data In
SRAM WRITE CYCLE 2 (CE1S -CONTROLLED) (see Note 4)
tWC Address tAS WE tCW CE2S tCW
CE1S
tWP
tWR
tBW
UB , LB
tBE tCOE DOUT Hi-Z
tODW Hi-Z tDS tDH See Note 5
DIN
See Note 5
Valid Data In
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TH50VSF3582/3583AASB
SRAM WRITE CYCLE 3 (CE2S-CONTROLLED) (see Note 4)
tWC Address tAS WE tCW CE2S tCW
CE1S
tWP
tWR
tBW
UB , LB
tBE tCOE DOUT Hi-Z
tODW Hi-Z tDS tDH See Note 5
DIN
See Note 5
Valid Data In
SRAM WRITE CYCLE 4 ( UB- and LB -CONTROLLED) (see Note 4)
tWC Address tAS WE tCW
CE1S
tWP
tWR
tCW CE2S tBW
UB , LB
tBE tCOE DOUT Hi-Z
tODW Hi-Z tDS tDH See Note 5
DIN
See Note 5
Valid Data In
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TH50VSF3582/3583AASB
FLASH COMMAND WRITE OPERATION
This is the timing of the Command Write Operation. The timing which described follow pages is typically same as this page's. * WE Control
tCMD Address tAS Command Address tAH tAHW
CEF
tCES
tCEH
WE tWELH tDS DIN tDH tWEHH
Command Data
*
CEF Control
tCMD Address tAS Command Address tAH
CEF
tCELH tWES WE tDS DIN tDH tWEH
tCEHH
Command Data
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TH50VSF3582/3583AASB
FLASH ID READ OPERATION (Input command sequence)
BK + 555H BK + 00H tRC BK + 01H
Address
555H tCMD
2AAH
CEF
OE
tOES WE
DIN
AAH
55H
90H Manufacturer Code Device Code
DOUT
Hi-Z Read Mode (Input ID Read Command Sequence) ID Read Mode
(Continued)
Address
555H tCMD
2AAH
555H
CEF
OE
WE
DIN
AAH
55H
F0H
DOUT
Hi-Z ID Read Mode (input of Reset command sequence) Read Mode
Notes: Word mode address shown BK: Bank address
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TH50VSF3582/3583AASB
FLASH AUTO-PROGRAM OPERATION ( WE -CONTROLLED)
Address
555H tCMD
2AAH
555H
PA
PA
CEF
OE
tOEHP tOES tPPW
WE
DIN
AAH
55H
A0H
PD
DOUT tVCS VCCf Note: Word Mode address shown. PA: Program address PD: Program data
Hi-Z
DQ7
DOUT
FLASH AUTO CHIP ERASE/AUTO BLOCK ERASE OPERATION ( WE -CONTROLLED)
Address
555H tCMD
2AAH
555H
555H
2AAH
555H/BA
CEF
OE
tOES WE
DIN tVCS VCCf
AAH
55H
80H
AAH
55H
10H/30H
Notes: Word mode address shown BA: Block address for Auto Block Erase operation
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TH50VSF3582/3583AASB
FLASH AUTO-PROGRAM OPERATION (CEF-CONTROLLED)
Address
555H tCMD
2AAH
555H
PA
PA
CEF
tPPW
OE
tOEHP tOES
WE
DIN
AAH
55H
A0H
PD
DOUT tVCS VCCf Notes: Word mode address shown PA: Program address PD: Program data
Hi-Z
DQ7
DOUT
FLASH AUTO CHIP ERASE/AUTO BLOCK ERASE OPERATION (CEF -CONTROLLED)
Address
555H tCMD
2AAH
555H
555H
2AAH
555H/BA
CEF
OE
tOES WE
DIN tVCS VCCf
AAH
55H
80H
AAH
55H
10H/30H
Note: Word Mode address shown. BA: Block address for Auto Block Erase operation
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TH50VSF3582/3583AASB
FLASH PROGRAM/ERASE SUSPEND OPERATION
Address BK RA
CEF
OE
WE tOE DIN B0H tCE DOUT Hi-Z tSUSP/tSUSE RY/BY Program/Erase Mode RA: Read address BK: Bank address Suspend Mode DOUT Hi-Z
FLASH PROGRAM/ERASE RESUME OPERATION
Address RA BK PA/BA
CEF
OE
tOES WE tDF1 tDF2 30H
tRESP/tRESE
tOE
DIN
tCE DOUT DOUT Hi-Z Flag Hi-Z
RY/BY Suspend Mode PA: Program address BK: Bank address BA: Block address RA: Read address Flag: Hardware Sequence flag Program/Erase Mode
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TH50VSF3582/3583AASB
FLASH RY/BY DURING AUTO-PROGRAM/ERASE OPERATION
CEF
Command input sequence
WE tBUSY During operation
RY/BY
FLASH HARDWARE RESET OPERATION
WE tRB
RESET
tRP tREADY RY/BY
FLASH READ AFTER RESET
tRC
Address tRH
RESET
tACC
tOH
DOUT
Hi-Z
Valid Data Out
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TH50VSF3582/3583AASB
FLASH HARDWARE SEQUENCE FLAG ( DATA Polling)
Address
Last Command Address tCMD
PA/BA
CE
tCE tOE
OE
tDF1
tOEHP WE tPPW /tPCEW /tPBEW DIN
Last Command Data
tDF2
tACC
tOH
DQ7
DQ7
Valid
Valid
DQ0~DQ6 tBUSY RY/BY PA: Program address BA: Block address
Invalid
Valid
Valid
FLASH HARDWARE SEQUENCE FLAG (Toggle Bit)
Address
Last Command Address tCMD
PA/BA
CEF
tOEHT
OE
tCE
tOEHP
WE
tPPW /tPCEW /tPBEW DIN
Last Command Data
tOE
DQ2/DQ6 tBUSY RY/BY
Toggle
Toggle
Stop* Toggle
Valid
PA: Program address BA: Block address *DQ2/DQ6 stops toggling when auto operation has been completed.
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TH50VSF3582/3583AASB
FLASH BLOCK PROTECT OPERATION
BA + 1
Address tCMD A0
BA tCMD
BA tCMD
BA tRC
A1
A6
CEF
OE
tPPLH WE tVPS VID VIH
RESET
DIN
60h
60h
40h tOE
60h
DOUT
Hi-Z
01h*
Notes: BA : Block address BA + 1 : Next Block address * : 01h indicates that block is protected.
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TH50VSF3582/3583AASB
TIMING FOR SWITCHING BETWEEN FLASH AND SRAM MODES
CEF
tCCR
CE1S
tCCR
CE2S
Notes: (1) (2) (3) (4) (5) (6)
WE remains High during a Read cycle. If CE1S goes Low (or CE2S goes High) at the same time as or after WE goes Low, the outputs will remain High-Impedance. If CE1S goes High (or CE2S goes Low) at the same time as or before WE goes High, the outputs will remain High-Impedance. If OE is High during a Write cycle, the outputs will remain High-Impedance. Because I/O pins may be in Output state at this point, input signals of the opposite value must not be applied. DOUT6 stops toggling when the last command has been completed.
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TH50VSF3582/3583AASB
SRAM DATA RETENTION CHARACTERISTICS (Ta = -30~85C)
SYMBOL VDH PARAMETER Data Retention Supply Voltage for SRAM VDH = 3.3 V ICCS4 SRAM Standby Current VDH = 3.0 V Ta = -30~85C Ta = -30~40C Ta = -30~85C MIN 1.5 0 tRC
(1)
TYP.
MAX 3.3 10 1 5
UNIT V
A
tCDR tr
Chip-Deselect-to-Data-Retention-Mode Time Recovery Time
ns ns
(1) Read cycle time
CE1S-CONTROLLED DATA RETENTION MODE (see Note 1)
VCCs Data Retention Mode 2.7 V
VCCs
(See Note 2) VIH
CE1S
(See Note 2) tr
tCDR
VCCs - 0.2 V
GND
CE2S-CONTROLLED DATA RETENTION MODE (see Note 3)
VCCs Data Retention Mode 2.7 V CE2S VIH tCDR tr
VCCs
VIL
0.2 V
GND
Notes: (1) (2) (3)
In CE1S -Controlled Data Retention Mode, Minimum Standby Current Mode is entered when CE2S 0.2 V or CE2S VCCs - 0.2 V. When CE1S is operating at the VIH level, the SRAM standby current is the same as ICCS3 during the transition of VCCs from 2.67 V to 2.3 V. In CE2S-Controlled Data Retention Mode, Minimum Standby Current Mode is entered when CE2S 0.2 V.
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TH50VSF3582/3583AASB
FLOWCHARTS OF FLASH MEMORY OPERATIONS
Auto-Program
Start
Auto-Program Command Sequence (see below)
DATA Polling or Toggle Bit
Address = Address + 1
No
Last Address? Yes Auto-Program Completed
Auto-Program command sequence (address/data)
555H/AAH
2AAH/55H
555H/A0H
Program address/program data
Note: Word mode command sequence is shown.
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TH50VSF3582/3583AASB
Fast Program
Start
Fast Program Set Command Sequence (see below) Fast Program Command Sequence (see below)
DATA Polling or Toggle Bit
Address = Address + 1
No
Last Address? Yes Program Sequence (see below) Fast Program Completed
Fast Program Set command sequence (address/data) 555H/AAH
Fast Program command sequence (address/data) XXXH/A0H
Fast Program Reset command sequence (address/data) XXXH/90H
2AAH/55H
Program address/program data
XXXH/F0H
555H/20H
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TH50VSF3582/3583AASB
Auto-Erase
Start
Auto-Erase Command Sequence (see below)
DATA Polling or Toggle Bit
Auto-Erase Completed
Auto Chip Erase command sequence (address/data)
Auto Block Erase / Multiple-Block Erase command sequence (address/data)
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/80H
555H/80H
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/10H
Block Address/30H
Block Address/30H
Block Address/30H
Additional Block Erase commands are operation
Note: Word mode command sequence is shown.
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TH50VSF3582/3583AASB
DQ7 ( DATA Polling)
Start
Read Byte (DQ0~DQ7) Addr. = VA DQ7 = Data? No No DQ5 = 1? Yes Read Byte (DQ0~DQ7) Addr. = VA DQ7 = Data? No Fail Pass Yes 1) 1) : DQ7 must be rechecked even if DQ5 = 1 because DQ7 may change at the same time as DQ5. Yes
DQ6 (Toggle bit)
Start
Read Byte (DQ0~DQ7) Addr. = VA DQ6 = Toggle? Yes No DQ5 = 1? Yes Read Byte (DQ0~DQ7) Addr. = VA DQ6 = Toggle? Yes Fail Pass No 1) 1) : DQ6 must be rechecked even if DQ5 = 1 because DQ6 may stop toggling at the same time that DQ5 changes to 1. No
VA: Byte address for programming. Any of the addresses within the block being erased during a Block Erase operation. Don't care during a Chip Erase operation. Any address not within the current block during an Erase Suspend operation.
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TH50VSF3582/3583AASB
Block Protect
Start
RESET = VID
Wait to 4 s
PLSCNT = 1
Block Protect Command First Bus Write Cycle (XXXh/60h)
Set up Address Addr. = BPA Block Protect Command Second Bus Write Cycle (BPA/60h)
Wait to 100 s
Block Protect Command Third Bus Write Cycle (XXXh/40h)
PLSCNT = PLSCNT + 1
Verify Block Protect No Data = 01h? Yes Yes Protect Another Block? No Remove VID from RESET Reset Command No PLSCNT = 25? Yes Remove VID from RESET
Reset Command
Device Failed
Block Protect Complete
BPA: Block Address and ID Read Address (A6, A1, A0) ID Read Address = (0, 1, 0)
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TH50VSF3582/3583AASB
PACKAGE DIMENSIONS
Unit: mm
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