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THC63LVD823_Rev2.0
THC63LVD823
Single(135MHz)/Dual(170MHz) Link LVDS Transmitter for SXGA/SXGA+/UXGA
General Description
The THC63LVD823 transmitter is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA+ resolutions and Dual Link transmission between Host and Flat Panel Display up to UXGA resolutions. The THC63LVD823 converts 48bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream. The transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin. In Single Link, the transmit clock frequency of 135MHz, 48bits of RGB data are transmitted at an effective rate of 945Mbps per LVDS channel. Using a 135MHz clock, the data throughput is 472Mbytes per second. In Dual Link, the transmit clock frequency of 85MHz, 48bits of RGB data are transmitted at an effective rate of 595Mbps per LVDS channel. Using a 85MHz clock, the data throughput is 595Mbytes per second.
Features
* Wide dot clock range: 25-135MHz suited for VGA,
SVGA, XGA, SXGA, SXGA+ and UXGA
* PLL requires No external components * Supports Dual Link, Dual-in (TTL)/Dual-out
(LVDS) pixel up to 170MHz dot clock for UXGA
* Supports Single Link, Dual-in (TTL)/Single-out * * * * * * *
(LVDS) pixel up to 135MHz dot clock for SXGA+ Supports Single Link, Single-in (TTL)/Single-out (LVDS) pixel up to 85MHz dot clock for XGA Clock edge selectable Supports Reduced swing LVDS for Low EMI Power down mode Low power single 3.3V CMOS design 100pin TQFP THC63LVDM83R compatible
Block Diagram
CMOS/TTL INPUT 8 MUX 8 8 8 8 8 PARALLEL TO SERIAL LVDS OUTPUT
RED1 1st DATA GREEN1 BLUE1
TA1 +/TB1 +/TC1 +/TD1 +/TCLK1 +/(25 to 135MHz) 1st Link
HSYNC VSYNC DE
TA2 +/PARALLEL TO SERIAL 8 8 8 TB2 +/TC2 +/TD2 +/TCLK2 +/(25 to 85MHz) 2nd Link
RED2 2nd DATA GREEN2 BLUE2 TRANSMITTER CLOCK IN (25 to 85MHz) R/F /PDWN
PLL
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
1
THine Electronics, Inc.
THC63LVD823 _Rev2.0
Pin Out
75 B15 B16 B17 R20 R21 R22 R23 R24 R25 R26 R27 VCC GND G20 G21 G22 G23 G24 G25 G26 G27 B20 B21 B22 B23 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
B13 B12 GND VCC B11 B10 G17 G16 G15 G14 G13 G12 G11 G10 R17 R16 R15 R14 GND VCC R13 R12 R11 R10
B14
LVDS GND TA1TA1+ TB1TB1+ LVDS VCC TC1TC1+ TCLK1TCLK1+ TD1TD1+ LVDS GND TA2TA2+ TB2TB2+ LVDS VCC TC2TC2+ TCLK2TCLK2+ TD2TD2+ LVDS GND
1 B24
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
B25 VCC GND B26 B27 HSYNC VSYNC DE CLKIN R/F RS TEST1 TEST2 MODE1 MODE0 OE 6/8 /PDWN TEST3 TEST4 TEST5 PLL GND PLL VCC PLL GND 2 THine Electronics, Inc.
THC63LVD823 _Rev2.0
Pin Description
Pin Name TA1+, TA1TB1+, TB1TC1+, TC1TD1+, TD1TCLK1+, TCLK1TA2+, TA2TB2+, TB2TC2+, TC2TD2+, TD2TCLK2+, TCLK2R17 ~ R10 G17 ~ G10 B17 ~ B10 R27 ~ R20 G27 ~ G20 B27 ~ B20 DE VSYNC HSYNC CLKIN TEST1, TEST5 TEST3, TEST4 TEST2 /PDWN 6/8 OE Pin # 48, 49 46, 47 43, 44 39, 40 41, 42 36, 37 34, 35 31, 32 27, 28 29, 30 60, 59, 58, 57, 54, 53, 52, 51 68, 67, 66, 65, 64, 63, 62, 61 78, 77, 76, 75, 74, 73, 70, 69 86, 85, 84, 83, 82, 81, 80, 79 96, 95, 94, 93, 92, 91, 90, 89 6, 5, 2, 1, 100, 99, 98, 97 9 8 7 10 13, 22 20, 21 14 19 18 17 Type LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT IN IN IN IN IN IN IN IN IN IN OUT IN IN IN IN IN Data Enable Input. Vsync Input. Hsync Input. Clock Input. Test Pins. Test Pins, must be L for normal operation. Test Pins, must be H for normal operation. H: Normal operation, L: Power down (all outputs are Hi-Z) 6bit/8bit color select. H: 6bit (TDx+/- are GND), L: 8bit. Output enable. H: Output enable, L: Output disable (all outputs are Hi-Z) Pixel Data Mode. MODE1, MODE0 15, 16 IN
MODE1 L L H MODE0 L H H Mode Dual Link (Dual-in/Dual-out) Single Link (Dual-in/Single-out) Single Link (Single-in/Single-out)
Description
The 1st Link. The 1st pixel output data when Dual Link.
LVDS Clock Out for 1st Link.
The 2nd Link. These pins are disabled when Single Link.
LVDS Clock Out for 2nd Link.
The 1st Pixel Data Inputs.
The 2nd Pixel Data Inputs.
RS
12
IN
LVDS swing range select. H: Normal range, L: Reduced range.
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD823 _Rev2.0
Pin Name R/F VCC GND LVDS VCC LVDS GND PLL VCC PLL GND
Pin # 11 3, 55, 71, 87 4, 56, 72, 88 33, 45 26, 38, 50 24 23, 25
Type IN Power Ground Power Ground Power Ground
Description Input Clock Triggering Edge Select. H: Rising edge, L: Falling edge Power Supply Pins for TTL inputs, output and digital circuitry. Ground Pins for TTL inputs, outputs and digital circuitry. Power Supply Pins for LVDS Outputs. Ground Pins for LVDS Outputs. Power Supply for PLL circuitry. Ground Pin for PLL circuitry.
Absolute Maximum Ratings 1
Supply Voltage (VCC) CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Driver Output Voltage Output Current Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 4sec) Maximum Power Dissipation @+25 C -0.3V ~ +4.0V -0.3V ~ (VCC + 0.3V) -0.3V ~ (VCC + 0.3V) -0.3V ~ (VCC + 0.3V) -30mA ~ 30mA +125 C -55 C ~ +125 C +260 C 1.0W
Electrical Characteristics CMOS/TTL DC Specifications
VCC = 3.0V ~ 3.6V, Ta = -10 C ~ +70 C Symbol VIH VIL IINC Parameter High Level Input Voltage Low Level Input Voltage Input Current
0V VIN V CC
Conditions
Min. 2.0 GND
Typ.
Max. VCC 0.8
10
Units V V A
1. "Absolute Maximum Ratings" are those valued beyond which the safety of the device can not be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation.
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD823 _Rev2.0
LVDS Transmitter DC Specifications
VCC = 3.0V ~ 3.6V, Ta = -10 C ~ +70 C Symbol Parameter Conditions Normal swing Reduced swing Min. 250 100 Typ. 350 200 Max. 450 300 35 RL=100 1.125 1.25 1.375 35 VOUT=0V, RL=100 /PDWN=0V, VOUT=0V to VCC -24
10
Units mV mV mV V mV mA A
VOD
Differential Output Voltage
RL=100
VOD VOC VOC IOS IOZ
Change in VOD between complementary output states Common Mode Voltage Change in VOC between complementary output states Output Short Circuit Current Output TRI-State current
Supply Current
VCC = 3.0V ~ 3.6V, Ta = -10 C ~ +70 C Symbol Parameter Condition(*) VESA SXGA ( 60Hz ) Transmitter Supply ITCCG Current (256 Gray Scale Pattern) VESA UXGA ( 60Hz ) CLKIN=81MHz VESA SXGA ( 60Hz ) Transmitter Supply ITCCW Current (Double Checker Pattern) VESA UXGA ( 60Hz ) CLKIN=81MHz ITCCS Transmitter Power Down Supply Current /PDWN = L CLKIN=54MHz CLKIN=54MHz MODE<1:0>=LH RL=100,CL=5pF VCC=3.3V MODE<1:0>=LL RL=100,CL=5pF VCC=3.3V MODE<1:0>=LH RL=100,CL=5pF VCC=3.3V MODE<1:0>=LL RL=100,CL=5pF VCC=3.3 10 A 86 99 mA 53 61 mA 78 89 mA 50 58 mA Typ. Max. Units
(*) VESA is a trademark of the Video Electronics Standards Association.
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD823 _Rev2.0
256 Gray Scale Pattern CLKIN Rx0/Gx0/Bx0 Rx1/Gx1/Bx1 Rx2/Gx2/Bx2 Rx3/Gx3/Bx3 Rx4/Gx4/Bx4 Rx5/Gx5/Bx5 Rx6/Gx6/Bx6 Rx7/Gx7/Bx7 x=1,2 DE
Double Checker Pattern CLKIN R1n/G1n/B1n R2n/G2n/B2n n=0~7 DE
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD823 _Rev2.0
Switching Characteristics
VCC = 3.0V ~ 3.6V, Ta = -10 C ~ +70 C Symbol tTCIT tTCIP tTCH tTCL tTS tTH tTCOP tLVT tTOP1 tTOP0 tTOP6 tTOP5 tTOP4 tTOP3 tTOP2 tTPLL tOE tCK12 CLK IN Period CLK IN High Time CLK IN Low Time TTL Data Setup to CLK IN TTL Data Hold from CKL IN CLK OUT Period LVDS Transition Time Output Data Position0 (tTCOP = 7.4ns) Output Data Position1 (tTCOP = 7.4ns) Output Data Position2 (tTCOP = 7.4ns) Output Data Position3 (tTCOP = 7.4ns) Output Data Position4 (tTCOP = 7.4ns) Output Data Position5 (tTCOP = 7.4ns) Output Data Position6 (tTCOP = 7.4ns) Phase Lock Loop Set OE High to Data Valid Skew Time between TCLK1+ and TCLK2+ 50 0.5 -0.15
t TCOP -------------- - 0.15 7 t TCOP 2 -------------- - 0.15 7 t TCOP 3 -------------- - 0.15 7 t TCOP 4 -------------- - 0.15 7 t TCOP 5 -------------- - 0.15 7 t TCOP 6 -------------- - 0.15 7
Parameter CLK IN Transition time
Min. 11.76 0.35tTCIP 0.35tTCIP 2.5 0.0 11.76 7.4
Typ.
Max. 5.0 40.0
Units ns ns ns ns ns ns 40.0 20.0 ns ns ns ns ns ns ns ns ns ns ms ns ns
0.5tTCIP 0.5tTCIP
0.65tTCIP 0.65tTCIP
Dual Link Single Link
0.5 0.0
tTCOP -------------7 tTCOP 2 -------------7 tTCOP 3 -------------7 tTCOP 4 -------------7 tTCOP 5 -------------7 tTCOP 6 -------------7
+0.15
t TCOP -------------- + 0.15 7 tTCOP 2 -------------- + 0.15 7 tTCOP 3 -------------- + 0.15 7 tTCOP 4 -------------- + 0.15 7 tTCOP 5 -------------- + 0.15 7 tTCOP 6 -------------- + 0.15 7
10.0
AC Timing Diagrams TTL Input
90%
90% 10% tTCIT tTCIT 80% 20%
CLK IN
10%
LVDS Output
Vdiff=(TA+)-(TA-) TA+ 5pF TALVDS Output Load 100
80%
Vdiff
20%
tLVT
tLVT
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD823 _Rev2.0
AC Timing Diagrams TTL Inputs
tTCIP 2.0V
tTCH 2.0V 2.0V
tTCL R/F = L 0.8V 0.8V R/F = H
CLK IN
Hsync Vsync DE Rxn Gxn
Bxn
tTS 2.0V 0.8V
tTH 2.0V 0.8V
x = 1,2 n = 0~7
Phase Lock Loop Set Time
3.0V
VCC
CLKIN
2.0V
/PDWN
tTPLL
Vdiff=0V TCLKx+/-
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD823 _Rev2.0
Power Up Sequence
Power Up Sequence must be Sequence1 or Sequence2. 1)Sequence1
VCC PVCC LVCC
tPW VCC VCC/2 GND tPD VCC
PD
VCC/2
GND
1) 2)
2)Sequence2
tPW < 10msec tPD > tPW
VCC PVCC LVCC
3.0V
VCC
GND
VCC
PD
GND
GND
PD pin must be High after VCC voltage is 3.0V.
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD823 _Rev2.0
AC Timing Diagrams LVDS Outputs
tTOP2 tTOP3 tTOP4 tTOP5 tTOP6 tTOP0 tTOP1
Tyx+/-
Tyx6
Tyx5
Tyx4
Tyx3
Tyx2
Tyx1
Tyx0
Tyx6
Tyx5
Tyx4
Tyx3
Tyx2
Tyx1
TCLKx+
Vdiff = 0V
Vdiff = 0V
x = 1,2 y = A,B,C,D
tTCOP
TCLK1+
Vdiff = 0V
tCK12
TCLK2+
Vdiff = 0V
Note: Vdiff = (Tyx+) - (Tyx-) , (TCLKx+) - (TCLKx-)
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
10
THine Electronics, Inc.
THC63LVD823 _Rev2.0
Pixel Map Table for Single/Dual Link
1st Pixel Data TFT Panel Data 24Bit LSB R10 R11 R12 R13 R14 R15 R16 MSB LSB R17 G10 G11 G12 G13 G14 G15 G16 MSB LSB G17 B10 B11 B12 B13 B14 B15 B16 MSB B17 18Bit R10 R11 R12 R13 R14 R15 G10 G11 G12 G13 G14 G15 B10 B11 B12 B13 B14 B15 823 TTL Input Pin R10 R11 R12 R13 R14 R15 R16 R17 G10 G11 G12 G13 G14 G15 G16 G17 B10 B11 B12 B13 B14 B15 B16 B17 MSB MSB LSB MSB LSB
2nd Pixel Data TFT Panel Data 24Bit LSB R20 R21 R22 R23 R24 R25 R26 R27 G20 G21 G22 G23 G24 G25 G26 G27 B20 B21 B22 B23 B24 B25 B26 B27 18Bit R20 R21 R22 R23 R24 R25 G20 G21 G22 G23 G24 G25 B20 B21 B22 B23 B24 B25 823 TTL Input Pin R20 R21 R22 R23 R24 R25 R26 R27 G20 G21 G22 G23 G24 G25 G26 G27 B20 B21 B22 B23 B24 B25 B26 B27
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD823 _Rev2.0
823 TTL Data Input Timing for Single/Dual Link Example : SXGA+(1400 x 1050)
HSYNC DE CLKIN R1x/G1x/B1x R2x/G2x/B2x n = 0~7 #1 #2 #3 #4 #5 #6 #7 #8 1395 #1397 #1399 1396 #1398 #1400
#1
#2
#1399 #1400
TFT Panel (1400 x 1050)
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD823 _Rev2.0
TTL Data Inputs Timing Diagrams in Dual Link (Dual-in / Dual-out Mode)
Previous Cycle
Current Cycle
TCLK1+
TA1+/-
R16'
R15'
R14'
R13'
R12'
G12
R17
R16
R15
R14
R13
R12
G12''
TB1+/-
G17'
G16'
G15'
G14'
G13'
B13
B12
G17
G16
G15
G14
G13
B13''
TC1+/-
HSYNC'
B17'
B16'
B15'
B14'
DE
VSYNC HSYNC
B17
B16
B15
B14
DE''
TD1+/-
B10'
G11'
G10'
R11'
R10'
L
B11
B10
G11
G10
R11
R10
L''
TCLK2+
TA2+/-
R26'
R25'
R24'
R23'
R22'
G22
R27
R26
R25
R24
R23
R22
G22''
TB2+/-
G27'
G26'
G25'
G24'
G23'
B23
B22
G27
G26
G25
G24
G23
B23''
TC2+/-
HSYNC'
B27'
B26'
B25'
B24'
DE
VSYNC HSYNC
B27
B26
B25
B24
DE''
TD2+/-
B20'
G21'
G20'
R21'
R20'
L
B21
B20
G21
G20
R21
R20
L''
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
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THine Electronics, Inc.
THC63LVD823 _Rev2.0
TTL Data Inputs Timing Diagrams in Single Link (Dual-in / Single-out Mode)
Previous Cycle (2nd Pixel Data)
Current Cycle (1st Pixel Data)
TCLK1+
TA1+/-
R26'
R25'
R24'
R23'
R22'
G12
R17
R16
R15
R14
R13
R12
G22''
TB1+/-
G27'
G26'
G25'
G24'
G23'
B13
B12
G17
G16
G15
G14
G13
B23''
TC1+/-
HSYNC'
B27'
B26'
B25'
B24'
DE
VSYNC HSYNC
B17
B16
B15
B14
DE''
TD1+/-
B20'
G21'
G20'
R21'
R20'
L
B11
B10
G11
G10
R11
R10
L''
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
14
THine Electronics, Inc.
THC63LVD823 _Rev2.0
Package
INDEX PIN No.1
100
76
75
0.5TYP 14.0SQ TYP 0.22 25 51 26 50 1.00TYP 1.2MAX
Copyright 2000-2003 THine Electronics, Inc. All rights reserved 15
UNIT:mm
THine Electronics, Inc.
16.0SQ TYP
THC63LVD823 _Rev2.0
Notes to Users:
1. The contents of this data sheet are subject to change without prior notice. 2. Circuit diagrams shown in this data sheet are examples of application. Therefore, please pay sufficient attention when designing circuits. Even if there are incorrect descriptions, we are not responsible for any problem due to them. Please note that incorrect descriptions sometimes cannot be corrected immediately if found. 3. Our copyright and know-how are included in this data sheet. Duplication of the data sheet and disclosure to other persons are strictly prohibited without our permission. 4. We are not responsible for any problems of industrial proprietorship occurring during THC63LVD823 use, except for those directly related to THC63LVD823's structure, manufacture or functions. THC63LVD823 is designed on the premise that it should be used for ordinary electronic devices. Therefore, it shall not be used for applications that require extremely high-reliability (space equipment, nuclear control equipment, medical equipment that affects people's lives, etc.). In addition, when using THC63LVD823 for traffic signals, safety devices and control/safety units in transportation equipment, etc., appropriate measures should be taken. 5. We are making the utmost effort to improve the quality and reliability of our products. However, there is a very slight possibility of failure in semiconductor devices. To avoid damage to social or official organizations, much care should be taken to provide sufficient redundancy and fail-safe design. 6. No radiation-hardened design is incorporated in THC63LVD823. 7. Judgment on whether THC63LVD823 comes under strategic products prescribed by the Foreign Exchange and Foreign Trade Control Law is the user's responsibility. 8. This technical document was provisionally created during development of THC63LVD823, so there is a possibility of differences between it and the product's final specifications. When designing circuits using THC63LVD823, be sure to refer to the final technical documents.
THine Electronics, Inc. Wakamatsu Bldg, 6F 3-3-6, Nihombashi-Honcho, Chuo-ku, Tokyo, 103-0023 Japan Tel: 81-3-3270-0666 Fax: 81-3-3270-0688
Copyright 2000-2003 THine Electronics, Inc. All rights reserved 16 THine Electronics, Inc.

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