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TQ2061
Figure 1. Pinout Diagram
TESTIN REFCLK
High-Frequency Clock Generator
4
GND
GND
NC
6
11
10
NC
9
8
7
VDD NC TEST1 TEST2 NC NC GND
NC
5
12
Phase
NC NC NC
13 14 15 16 17 18 19 20 21
Control
VCO
/20
Features
* Output frequency range: 500 MHz to 700 MHz * One differential PECL output: 600 mV (min) swing * Common-mode voltage: VDD -1.2 V (max), VDD -1.6 V (min) * Period-to-period output jitter: 25 ps peak-to-peak (typ) 70 ps peak-to-peak (max) * Reference clock input: 25 MHz to 35 MHz TTL-level crystal oscillator * Self-contained loop filter * Optional 200 pull-down resistors for AC-coupled outputs * +5 V power supply * 28-pin J-lead surface-mount package * Ideal for designs based on DEC Alpha AXPTM processors
MUX
3 2
MUX
1 NC 28 NC 27 NC 26
22
23
24
25
AGND
EVDD
PDR2
QN
PDR1
GND
Q
TriQuint's TQ2061 is a high-frequency clock generator. It utilizes a 25 MHz to 35 MHz TTL input to generate a 500 MHz to 700 MHz PECL output. The TQ2061 has a completely self-contained Phase-Locked Loop (PLL) running at 500 MHz to 700 MHz. This stable PLL allows for a low period-to-period output jitter of 70 ps (max), and enables tight duty cycle control of 55% to 45% (worst case). The TQ2061 provides optional 200-ohm on-chip pull-down resistors which are useful if the output is AC-coupled to the device being driven. In order to use these resistors, pin 20 (PDR2) should be connected to pin 21 (QN), and pin 23 (PDR1) should be connected to pin 22 (Q). Various test modes on the chip simplify debug and testing of systems by slowing the clock output or by bypassing the PLL.
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1
SYSTEM TIMING PRODUCTS
TQ2061
Figure 2. Simplified Block Diagram
REFCLK (25MHz to 35 MHz) TESTIN TEST1
Phase
VCO MUX : 20 MUX
QN Q
(500 MHz to 700 MHz)
Control
TEST2
Table 1. Mode Selection
Mode
1 (Test) 2 (Test) 3 (Test) 4 (Bypass) 5 (Normal)
TEST1
0 0 1 1 1
TEST2
0 1 0 1 1
TESTIN 1
"don't care" "don't care" fTESTCLK 0 1
REFCLK
fREFCLK "don't care" "don't care" fREFCLK fREFCLK
Q, QN
fREFCLK2 0, 1 fTESTCLK fREFCLK 20 x fREFCLK3
Notes: 1. In mode 3, TESTIN may be used to bypass the PLL. 2. REFCLK = 25 MHz to 35 MHz. 3. Q, QN = 500 MHz to 700 MHz.
Figure 3. Recommended Layout (Not to scale)
Pin 1 VDD 0.1 F GND GND REFCLK (from TTLoscillator) VDD GND 0.1 F VDD Q 50 OHMS QN
(From TTL Oscillator)
GND
0.1 F
2
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TQ2061
Table 2. Absolute Maximum Ratings
Storage Temperature Ambient temperature with power applied Supply voltage to ground potential DC input voltage DC input current Package thermal resistance (MQuad) Die junction temperature
Note:
-65C to +150C -55C to +110C -0.5 V to +7.0 V -0.5 V to (VDD + 0.5) V -30 mA to +5 mA JA = 45C/W TJ = 150C
Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. The device should be operated only under the DC and AC conditions shown below.
Table 3. DC Characteristics (VDD = +5 V + 5%, TA = 0 C to +70 C) 1
Symbol
VOH VOL VCMO VOUT VIH2 VIL2 IIL IIH II IDDS3 VI
Description
Output HIGH voltage Output LOW voltage Output common mode voltage Output differential voltage Input HIGH level Input LOW level Input LOW current Input HIGH current Input HIGH current Power supply current Input clamp voltage
Test Conditions
Min
Typ
Max
VCC - 0.50 VCC - 1.60 VCC - 1.20 1.2
Unit
V V V V V V SYSTEM TIMING PRODUCTS A A A mA V
VCC = Min PECL load VCC - 1.20 VCC = Min PECL load VCC - 2.00 PECL VCC - 1.60 PECL 0.6 Guaranteed input logical 2.0 HIGH Voltage for all inputs Guaranteed input logical LOW Voltage for all inputs VDD = Max VIN = 0.40 V VDD = Max VIN = 2.7 V VDD = Max VIN = 5.3 V VDD = Max VDD = Min IIN = -18 mA
0.8 -150 0 2 85 -0.70 -400 25 1000 120 -1.2
Table 4. Capacitance
Symbol
CIN COUT
Description
Input Capacitance Output Capacitance
Test Conditions
VIN = 2.0 V at f = 1 MHz VOUT = 2.0 V at f = 1 MHz
Min
Typ
6 9
Max
Unit
pF pF
Notes: 1. Typical limits are at VDD = 5.0 V and TA = 25C. 2. These are absolute values with respect to device ground and include all overshoots due to system or tester noise. 3. This parameter is measured with device not switching and unloaded.
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3
TQ2061
Table 5. AC Characteristics (VDD = +5 V + 5%, TA = 0 C to +70 C)
Symbol
tCPWH tCPWL tIR
Input Clock (REFCLK)
CLK pulse width HIGH CLK pulse width LOW Input rise time (0.8 V - 2.0 V)
Test Conditions (Figure 5)
Figure 5 Figure 5
Min
4 4 --
Typ
-- -- --
Max
-- -- 2.0
Unit
ns ns ns
Symbol
tOR, tOF tCYC tJP2 tSYNC3
Output Clock (Q, QN)
Rise/fall time (20% - 80%) Duty-cycle Period-to-Period Jitter Synchronization Time
Test Conditions (Figures 4 & 5)1
Figure 5 Figure 5
Min
100 45 -- --
Typ
220 50 25 10
Max
350 55 70 500
Unit
ps % ps s
Notes: 1. All measurements are tested with a REFCLK having a rise time of 0.5 ns (0.8 V to 2.0 V). 2. Jitter specification is peak to peak. Period-to-Period jitter is the jitter on the output with respect to the output's previous crossing. 3. tSYNC is the time required for the PLL to synchronize and assumes the presence of a CLK signal.
Figure 4. PECL Test Load
Figure 5. REFCLK and Q-QN Timing
4
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TQ2061
Figure 6. 28-Pin MQuad J-Leaded Package Mechanical Specification
.172 .005 .490 .005 .045 X 45 .445 .005 .132 .005 .040 MIN
PIN 1 8 0.125 VENT PLUG 15 .015 X 45 22
.490 .005 .445 .005 .445 .028 .005 .018
.410 .015
.050 TYP. .060
.050 TYP. NON-ACCUM.
.104 .005
(All dimensions in inches)
Table 6. 28-Pin MQuad Pin Description
Pin # Pin Name
1 2 3 4 5 6 7 8 9 10 11 12 13 14 NC NC NC NC NC NC GND REFCLK TESTIN NC GND VDD NC TEST1
Description
No Connect No Connect No Connect No Connect No Connect No Connect Ground Reference Clock Test Input No Connect Logic Ground Logic VDD (+5 V) No Connect Test Control 1
I/O
-- -- -- -- -- -- -- I I -- -- -- -- I
Pin # Pin Name
15 16 17 18 19 20 21 22 23 24 25 26 27 TEST2 NC NC GND EVDD PDR2 QN Q PDR1 GND AGND AVDD NC
Description
Test Control 2 No Connect No Connect Ground VDD for ECL Output (+5 V) Pull-down Resistor 2 (200 ) Differential PECL Output (-) Differential PECL Output (+) Pull-down Resistor 1 (200 ) Ground Analog Ground Analog VDD (+5 V) No Connect
I/O
I -- O -- -- I O O I -- -- -- --
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5
SYSTEM TIMING PRODUCTS
TQ2061
Ordering Information
To order, please specify as shown below:
TQ2061-MC
High-Frequency Clock Generator
Temperature range: 0C to 70C (Commercial) Package: 28-Pin MQuad
Additional Information
For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: sales@tqs.com Tel: (503) 615-9000 Fax: (503) 615-8900
For technical questions and additional information on specific applications: Email: applications@tqs.com
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright (c) 1997 TriQuint Semiconductor, Inc. All rights reserved. Revision 1.0.A October 1997
6
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