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CMOS STATIC RAM 1 MEG (128K x 8-BIT)
Integrated Device Technology, Inc.
IDT71024S70
FEATURES:
* 128K x 8 CMOS static RAM * Equal access and cycle times -- Commercial: 70ns * Two Chip Selects plus one Output Enable pin * Bidirectional inputs and outputs directly TTL-compatible * Low power consumption via chip deselect * Available in 300 and 400 mil Plastic SOJ packages
DESCRIPTION:
The IDT71024 is a 1,048,576-bit medium-speed static RAM organized as 128K x 8. It is fabricated using IDT's highperformance, high-reliability CMOS technology. This stateof-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for your memory needs. The IDT71024 has an output enable pin which operates as fast as 30ns, with address access times as fast as 70ns available. All bidirectional inputs and outputs of the IDT71024 are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. The IDT71024 is packaged in 32-pin 300 mil Plastic SOJ and 32-pin 400 mil Plastic SOJ packages.
FUNCTIONAL BLOCK DIAGRAM
A0
* * *
A16
ADDRESS DECODER
* * *
1,048,576-BIT MEMORY ARRAY
I/O0 - I/O7
8
I/O CONTROL
8
8
WE OE CS1
CONTROL LOGIC
3568 drw 01
CS2
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc.
MAY 1996
DSC-3568/-
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IDT71024S70 CMOS STATIC RAM 1MEG (128K x 8-BIT)
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 32 2 31 3 30 4 29 5 28 6 S032-3 27 7 SO32-3 26 8 25 24 9 23 10 22 11 21 12 13 20 14 19 15 18 16 17 VCC A15 CS2
WE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM
(2)
Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias StorageTemperature Power Dissipation DC Output Current
Com'L. -0.5 to +7.0
Unit V
TA TBIAS TSTG PT IOUT
0 to +70 -55 to +125 -55 to +125 1.25 50
C C C W mA
A13 A8 A9 A11
OE
A10
CS1
I/O7 I/O6 I/O5 I/O4 I/O3
3568 drw 02
SOJ TOP VIEW
NOTES: 3568 tbl 02 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V.
TRUTH TABLE(1,2)
INPUTS
WE CS1
CAPACITANCE
(TA = +25C, f = 1.0MHz, SOJ package)
I/O High-Z High-Z High-Z High-Z High-Z FUNCTION Deselected-Standby (ISB) Deselected-Standby (ISB1) Deselected-Standby (ISB) Deselected-Standby (ISB1) Outputs Disabled Read Data Write Data
3568 tbl 01
CS2 X X L VLC(3) H H H
OE
Symbol CIN CI/O
Parameter(1) Input Capacitance I/O Capacitance
Conditions VIN = 3dV VOUT = 3dV
Max. 8 8
Unit pF pF
X X X X H H L
H VHC(3) X X L L L
X X X X H L X
NOTE: 3568 tbl 03 1. This parameter is guaranteed by device characterization, but is not production tested.
DATAOUT DATAIN
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0 -- -- Max. 5.5 0 Vcc+0.5 0.8 Unit V V V V
NOTES: 1. H = VIH, L = VIL, X = Don't care. 2. VLC = 0.2V, VHC = VCC -0.2V. 3. Other inputs VHC or VLC.
NOTE: 3568 tbl 04 1. VIL (min.) = -1.5V for pulse width less than 10ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V 10%
IDT71024 Symbol |ILI| |ILO| VOL VOH
.
Parameter Input Leakage Current Output Leakage Current Output LOW Voltage Output HIGH Voltage
Test Condition VCC = Max., VIN = GND to VCC VCC = Max., CS1 = VIH, CS2 = VIL, VOUT = GND to VCC IOL = 8mA, VCC = Min. IOH = -4mA, VCC = Min.
Min. -- -- -- 2.4
Max. 5 5 0.4 --
Unit A A V V
3568 tbl 05
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IDT71024S70 CMOS STATIC RAM 1MEG (128K x 8-BIT)
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS(1)
(VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC - 0.2V)
71024S70 Symbol ICC Parameter Dynamic Operating Current, CS2 VIH and CS2 VIH and CS1 VIL, Outputs Open, VCC = Max., f = fMAX(2) Standby Power Supply Current (TTL Level) CS1 VIH or CS2 VIL, Outputs Open, VCC = Max., f = fMAX(2) Full Standby Power Supply Current (CMOS Level) CS1 VHC, or CS2 VLC Outputs Open, VCC = Max., f = 0(2), VIN VLC or VIN VHC Com'l. Mil. 140 -- Unit mA
ISB
35
--
mA
ISB1
10
--
mA
NOTES: 1.All values are maximum guaranteed values. 2.fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
3568 tbl 06
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 3ns 1.5V 1.5V See Figures 1 and 2
3568 tbl 07
5V 480 DATAOUT 30pF 255
3568 drw 03
5V 480 DATAOUT 5pF* 255
3568 drw 04
Figure 1. AC Test Load
*Including jig and scope capacitance. Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
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IDT71024S70 CMOS STATIC RAM 1MEG (128K x 8-BIT)
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, Commercial Temperature Range)
Symbol Parameter 71024S70 Min. Max. Unit
Read Cycle tRC tAA tACS tCLZ
(2) (2)
Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low-Z Chip Deselect to Output in High-Z Output Enable to Output Valid
(2) (2)
70 -- -- 3 0 -- 0 0 4 0 --
-- 70 70 -- 30 30 -- 30 -- -- 70
ns ns ns ns ns ns ns ns ns ns ns
tCHZ tOE tOLZ
Output Enable to Output in Low-Z Output Disable to Output in High-Z Output Hold from Address Change Chip Select to Power-Up Time Chip Deselect to Power-Down Time
tOHZ tOH tPU tPD
(2) (2)
Write Cycle tWC tAW tCW tAS tWP tWR tDW tDH tOW
(2) (2)
Write Cycle Time Address Valid to End-of-Write Chip Select to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Data Hold Time Output Active from End-of-Write Write Enable to Output in High-Z
70 60 60 0 45 0 30 0 5 0
-- -- -- -- -- -- -- -- -- 30
ns ns ns ns ns ns ns ns ns ns
3568 tbl 08
tWHZ
NOTES: 1. 0C to +70C temperature range only. 2. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
4
IDT71024S70 CMOS STATIC RAM 1MEG (128K x 8-BIT)
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
t RC ADDRESS t AA
OE
t OE
CS1
t OLZ
(5)
CS2 t CLZ (5) DATA OUT Vcc SUPPLY CURRENT Icc Isb
t ACS (3) t OHZ (5) t CHZ (5) DATA OUT VALID t PD
HIGH IMPEDANCE t PU
3568 drw 05
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATAOUT VALID tOH DATAOUT VALID
3568 drw 06
NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS1 is LOW, CS2 is HIGH. 3. Address must be valid prior to or coincident with the later of CS1 transition LOW and CS2 transition HIGH; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured 200mV from steady state.
5
IDT71024S70 CMOS STATIC RAM 1MEG (128K x 8-BIT)
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 5, 7) WE
tWC ADDRESS tAW
CS1
tCW
CS2 tAS
WE
tWR (3) tWP (7) tCHZ (6)
(4)
tWHZ DATAOUT
(4)
(6)
tOW HIGH IMPEDANCE tDH tDW
(6)
DATAIN
DATAIN VALID
3568 drw 07
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS1 AND CS2 CONTROLLED TIMING)(1, 2, 5) CS1
tWC ADDRESS tAW
CS1
CS2 tAS
WE
tCW
tWR
(3)
tDW DATAIN DATAIN VALID
tDH
3568 drw 08
NOTES: 1. WE must be HIGH, CS1 must be HIGH, or CS2 must be LOW during all address transitions. 2. A write occurs during the overlap of a LOW CS1, HIGH CS2, and a LOW WE. 3. tWR is measured from the earlier of either CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CS1 LOW transition or the CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS1 and CS2 must both be active during the tCW write period. 6. Transition is measured 200mV from steady state. 7. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP.
6
IDT71024S70 CMOS STATIC RAM 1MEG (128K x 8-BIT)
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT 71024 Device Type S Power XX Speed X Package X Process/ Temperature Range Blank Commercial (0C to +70C)
TY Y
300-mil SOJ (SO32-2) 400-mil SOJ (SO32-3)
70
Speed in nanoseconds
3568 drw 09
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