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1 CHIP CLP SUBSYSTEM IC
S1T8527C
INTRODUCTION
48-QFP-1010E S1T8527C is a monolithic circuit which can be used in high performance 60MHz MCA type CLP System. The S1T8527C is a subsystem IC for FM / FSK receiving systems and a complete one chip FM / FSK receiver IC for 60MHz system. It's feature includes receiving functions for FM / FSK systems, a compander to remove external noise, and PLL ( Phase Lock Loop ) of channel selection which blocks surrounding frequency interference. The S1T8527C can be used with a wide range of FM / FSK VHF bandwidth systems, including cordless phone, and the narrow band voice and data sending / receiving systems. To make applications easily and simply, peripheral parts are minimized.
FEATURES
* * * * * * * Operating voltage range: 2.0V -- 5.5V Typical supply current: 13.5mA at 3.6V Built-in low battery detection function ( selectable 3.45V, 3.3V, 3.0V, 2.2V, 2.1V ) Built-in speaker amplifier Built-in splatter filter Built-in dual conversion receiver, compander and universal PLL FM Receiver -- Complete dual conversion circuit -- Excellent input sensitivity (0.7Vrms at 12dB SINAD) * Compader -- Easy gain control to use external component -- Included ALC (Automatic Level Control) circuit -- Included Mute logic * Universal PLL -- RX (TX) divided counter range: 1/16 -- 1/16383 -- Reference frequency divided counter range: 1/16 -- 1/4095 -- Lock detector signal output -- Serial interface with MCU for controlling each block
ORDERING INFORMATION
Device S1T8527C01-Q0R0 Package 48-QFP-1010E Operating Temperature -20C -- + 70C
1
S1T8527C
1 CHIP CLP SUBSYSTEM IC
BLOCK DIAGRAM
GND(RX)
VCC(RX)
DSCO
DSCI
36
35
34
33
32
31
30
29
28
27
26
25
X-tal OSC
Limiting IF AMP
FSK COMP
MDO
2LOI
2LOI
2MO
RAO
QCI
LD
LI
Regulator (1V)
VREF
24
VREF
(COMP)
2MI 37 1MO 38 1LOI 39 1LOI 40
2nd MIX
IF AMP (455KHz)
Meter Driver Rectifier
PRI + -
23 22
ALC EPI
RX VCO
Quad Detector AMP
Carrier Detector
21 ERC SUM AMP 20 EO 19 SAI 18 SAO1 SPK AMP 17 SAO2 16 VCC
VCO 41
RX
1st MIX
IF AMP (10.7MHz)
1MI 42 1MI 43 GND
(PLL)
Low Battery Detector
Gain Cell
SPK AMP
Regulator ( 2.15 V )
Buffer
Limiter
44
SUM AMP
+ PRI
(COMP)
PDR 45 VREF
(PLL)
Programmable Counter ( RX ) Gain Cell Programmable Counter ( TX ) Programmable Counter ( REF )
-
15 GND
(COMP)
14 CPI+ 13 CPI -
46 47
ALC 4_25 CNT Rectifier
VCC
(PLL)
TIF 48
RX Phase Detector
TX Phase Detector
Splatter Filter
fMCU
CONTROL
Compandor mute
1
PDT
2
CO
3
SFI
4
SFO
5
CDO/LDT
6
GND(PLL)
7
CLK
8
DATA
9
EN
10
LBD
11
AGIC
12
CRC
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1 CHIP CLP SUBSYSTEM IC
S1T8527C
PIN CONFIGURATION
VCC(RX)
GND(RX)
DSCO 26
DSCI
36 2MI 37 1MO 38 1LOI 39 1LOI 40 VCORX 41 1MI 42 1MI 43 GND(PLL) 44 PDR 45 VREF(PLL) 46 VCC(PLL) 47 TIF 48 1 PDT
35
34
33
32
31
QCI
LD
30
29
28 27
25 24 VREF(COMP) 23 ALC 22 EPI 21 ERC 20 EO
MDO 19 SAI 18 SAO1 17 SAO2 16 VCC(COMP) 15 GND (COMP) 14 CPI+ 13 CPI 12 CRC
2LOI
2LOI
2MO
KB8527B
S1T8527C
2 CO
3 SFI
4 SFO
5 CDO/LDT
6 GND(PLL)
7 CLK
8 DATA
RAO 9 EN
LI
10 LBD
11 AGIC
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S1T8527C
1 CHIP CLP SUBSYSTEM IC
PIN DESCRIPTION
Pin No 1 Symbol PDT3 Description Phase detector output terminal of the transmitter at PLL. If fTX > fREF or fTX is leading the output is negative pulse If fTX < fREF or fTX is lagging the output is positive Pulse if fTX = fREF and the same phase the output is High Impedance Compressor output terminal of compander; connected to the splatter filter amp input terminal. Input terminal of Splatter filter amp. Output terminal of Splatter filter amp. LDT: Output terminal of transmitter lock detector in PLL block. The output is low if PLL is in lock state and the output is high if PLL is in unlock state. CDO: As an output terminal of the carrier detector buffer, connected to (RSSI ) terminal of MCU. This pin outputs the contents of Meter Driver buffer which is turned on / off, according to the signal level detected by Meter Driver. 6 7 8 9 10 GNDPLL CLK DATA EN LBD Ground. Ground of logic section at PLL. These pins are serial interface terminals for programming reference counter, auxiliary reference counter, TX channel counter, RX channel counter and control block that controls internal each block with test mode and power saving mode. Low Battery Detecting output. ( Selectable 3.45V, 3.3V, 3.0V, 2.2V, 2.0V ). During the normal operation, output level is low, but it is high at low battery detection. As this pin is an open collector type, it requires a pull - up resistor. This pin bypasses AC elements at the feedback loop which come from the SUM amp block of COMPRESSOR. A capacitor should be connected between this terminal and GND. ( C = 2.2uF ) Converts waveform from the full wave rectifier to DC element at the rectifier block of Compressor. ( RC = 33msec ) Pre-amp inverting input terminal of Compressor. Adjusts the negative feedback loop gain. ( in application, gain is 5 ) Pre-amp non-inverting input terminal of Compressor. Used as an input terminal for voice signals. Ground of Compander block. Supply voltage. Power supply terminal of Compander. Output terminal of speaker amp 2. This signal is the same as SAO1 output, but phase difference is180 for SAO1. DC voltage level is ( Vcc -- 0.7V ) / 2.
2 3 4 5
CO SFI SFO3 LDT/CDO
11
AGIC
12 13 14 15 16 17
CRC CPI CPI + GND(COMP) Vcc(COMP) SAO 2
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1 CHIP CLP SUBSYSTEM IC
S1T8527C
PIN DESCRIPTION (Continued)
Pin No 18 19 20 21 22 23 Symbol SAO 1 SAI EO ERC EPI - ALC Description Output terminal of Speaker amp 1. DC voltage level is ( Vcc -- 0.7V ) / 2. Speaker Amp 1 input terminal. Between this terminal and Expander output terminal, uses a AC coupled. Output terminal of Expander, from which a regenerated voice signals are emitted. Converts waveform from the full wave rectifier to DC element at the rectifier block of Expander. ( RC = 33 msec ) Pre-amp inverting input terminal of Expander. Adjusts the negative feedback loop gain. ( in application, gain is 5 ). Reference current input terminal of Automatic Level Control ( ALC); Adjusts THD of compressor output voltage to less than 3% or limits the frequency deviation of TX if the input is higher than a certain level. The ALC circuit may be turned off depending on the ALC reference current or the magnitude of output voltage may be limited if it is higher than a certain level.
24 25
VREF(COMP) Reference voltage ( VREF= 1V ). Supplies a regulator voltage to the Compressor and Expander of COMPANDER. MDO Output terminal of the Meter Driver. Amplitude of RF input signal for useful frequency is detected by Meter Driver circuit. The Meter Driver circuit has perfect linear characteristic of 60dB range for input signal level. ( 0.1A / dB ). Output terminal of Data Slicing comparator. Separates Frequency Shift Keying ( FSK ) serial data and executes data shaping and limiting. Input terminal of Data slicing comparator. Non-inverting type with the negative input terminal biased to 1/2 Vcc. Recovered Audio Output terminal. Voice signals detected by the Quadrature Detector are amplified and then output through this terminal. Quadrature coil input terminal. The 455kHz oscillator circuit is an Lp = 680uH, Cp = 180pF valued LC tank circuit. Voice signals are detected by mixture of 455kHz ( by phase difference ) which is converted from mixer 2. Ground . Ground for Receiver. Limiter input and decoupling terminal. Removes amplitude modulation elements caused by fading or FM signal noise. Limiting IF amplifies and limits the second intermediate frequency, 455kHz.The input impedance of the limiting IF amplifier is set to 1.5k. While FM waves are transmitted with constant magnitude, their magnitudes are slightly modulated due to reflection from obstacles, fading phenomenon, noise wave, and mixing with AM wave elements before entering the receiver's antenna.The limiter makes amplitude uniform by removing these AM wave elements.
26
DSCO
27 28 29
DSCI RAO QCI3
30 31 32
GNDRX LD LI
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S1T8527C
1 CHIP CLP SUBSYSTEM IC
PIN DESCRIPTION (Continued)
Pin No 33 34 35 36 37 Symbol VCC(RX) 2MO3 2LOI 2LOI 2MI Supply voltage. Supplies power to the Receiver. Output terminal of Mixer 2. Second intermediate frequency ( 455kHz ), generated by mixing first intermediate frequency ( 10.7MHz ) and Second Local Oscillator is output. Input terminal of second local oscillator. Generates second local oscillator frequency to convert output from mixer 1 ( 10.7MHz ) into second intermediate frequency. It is an oscillator with crystal of 10.24MHz and 10.245MHz. Input terminal of mixer 2. Output from mixer 1 is entered to mixer 2 input terminal via 10.7MHz ceramic filter. Second mixer converts frequency to second intermediate frequency ( 455kHz: AM IF ). Output terminal of mixer 1. The signal from mixer 1 and the frequency of the first local oscillator are mixed to produce the first intermediate frequency, which is the output through this terminal. The output terminal is an emitter follower with an output impedance of 330 to match the 330 input/output impedance of the 10.7MHz ceramic filter. Input terminal of the first local oscillator. The local oscillator is a voltage controlled oscillator. local oscillation frequency and received frequency are mixed at mixer 1 and then converted to the first intermediate frequency of 10.7MHz or 10.695MHz. The terminal which variable capacitor is included in the chip. Used as an input terminal where 1st local oscillation frequency is changed by varying the capacitor connected between 1st local oscillator terminals.The internal variable capacitor has the value of 18.73 ~ 15.86pF depending on the applied voltage. ( 1.0 ~ 2.0 V ). Input terminal of Mixer 1. This mixer is made of double balanced multiplier. The received signal amplified at RF AMP is input to this terminal. Ground. Ground for analog at PLL Phase detector output terminal of the receiver at PLL. If fRX > fREF or fRX is Leading The output is negative pulse If fRX < fREF or fRX is Lagging The output is positive pulse If fRX = fREF and the same phase The output is high impedance PLL voltage reference output pin. An internal voltage regulator provides a stable power supply voltage for the RX and TX PLLs. Power supply terminal of PLL. Input terminal of TX channel counter. AC coupling with TX VCO. Minimum input level is 300mVp-p ( at 60MHz ). Description
38
1MO3
39 40
1LOI 1LOI
41
VCORX
42 43 44 45
1MI 1MI GND (PLL) PDR
46
VREF(PLL)
47 48
VCC(PLL) TIF
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1 CHIP CLP SUBSYSTEM IC
S1T8527C
ABSOLUTE MAXIMUM RATINGS
Characteristic Maximum Supply Voltage Power Dissipation Operating Temperature Storage Temperature Symbol VCC PD TOPR TSTG Value 5.5 600 -20 -- + 70 - 55 -- + 150 Unit V mW C C
CURRENT CONSUMPTION AT EACH MODE ( VCC = 3.6V ) MODES Inactive mode RX mode Communication mode ( Active mode ) Min. - - - Typ. 350uA 6.6mA 13.5mA Max. 600uA -
CURRENT CONSUMPTION IN EACH BLOCK ( VCC = 3.6V )
MODES Receiver part Expander part Speaker part compressor part PLL RX part TX part
Min. - - - - - -
Typ. 5.0mA 1.4mA 1.7mA 3.0mA 1.6mA 0.8mA
Max. 7.5mA 2.1mA 2.5mA 4.5mA 2.4mA 1.2mA
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S1T8527C
1 CHIP CLP SUBSYSTEM IC
ELECTRICAL CHARACTERISTICS
Characteristic Operating Voltage RECEIVER ( VCC = 3.6V, fC = 49.7MHz, fDEV = 3kHz, fMOD = 1kHz,Ta = 25C, unless otherwise specified ) Input for -3dB Sensitivity Input for 20dB Sensitivity S/N Ratio Recovered Audio Output Noise Output Level Recovered Audio Output Voltage Drop Detect Output Voltage Carrier Detector Threshold Comparator Threshold Voltage Difference Comparator Output Voltage 1 Comparator Output Voltage 2 First Mixer Conversion Voltage Gain Second Mixer Conversion Voltage Gain Detector Output Distortion Detector Output Resistance Detector Output DC Voltage Change Ratio Meter Drive Slope First Mixer Input Resistance First Mixer Input Capacitance Limiter Input Sensitivity Second Mixer Input Sensitivity VLIM VI(SEN) S/N VO(RA) VNO VO(RAD) VO(DET) VTH(DET) VTH VOH VOL GV(1M) GV(2M) THDDET RO(DET) VO(DET) MDS RI(1M) CI(1M) VI(LIM) SV(2M) fc = 50MHz fc = 50MHz fc = 455kHz, 20dB SINAD fc = 10.7MHz, 20dB SINAD -3dB Point Modulation Input Modulation Input No Modulation Input RFin = 1mVrms RFin = No Input Vcc = 5V 2V RFin = 1mVrms RFin = 1mVrms RFin = No Input VCOMP = 150mVp-p R L = 180k VCOMP = 150mVp-p RL = 180k VCOMP = 150mVp-p R L = 180k VI(43) = 1mVrms R L(38) = 330 VI(37) = 1mVrms R L(34) = 1.5k RFin = 1mVrms RFin = 1mVrms RFin = 1mVrms - - 48 145 - -8 1.0 0.49 70 2.7 - 14 17 - - - 70 500 - - - 0.7 0.7 55 185 130 -3.3 1.5 0.60 110 3.0 0.25 18 21 1.5 1.2 0.15 100 690 7.2 100 10 2.0 2.0 - 225 205 - 2.0 0.73 150 - 0.5 22 25 2.5 - 0.23 135 - 10 250 25 Vrms Vrms dB mVrms mVrms dB V V mV V V dB dB % k V/kHz nA/dB pF Vrms Vrms Symbol Vcc Test Conditions - Min. 2.0 Typ. - Max. 5.5 Unit V
8
1 CHIP CLP SUBSYSTEM IC
S1T8527C
ELECTRICAL CHARACTERISTICS (Continued)
Characteristic First Mixer 3rd Order Sensitivity Low Battery Detector Symbol 3RD LBD3 Test Conditions - Min. - Typ. -22 3.45 3.3 3.0 2.2 2.1 25 Max. - 0.1 Unit dBm V
LBD0-- LBD3 = 0 ( Default ) -0.15 Only LBD2 = 0 Only LBD1 = 0 Only LBD3 = 0 LBD0 -- LBD3 = 1 -0.1 25
0.075 - dB
AM Rejection Ratio Compressor
AMRR
RFin = 1mVrms -- 10mVrms AM MOD = 30%
( Vcc = 3.6V, fc = 1kHz, Ta = 25C, unless otherwise specified ) Reference Voltage Standard Output Voltage Compressor Gain Difference VREF Vo(com) No Signal Vinc = 13mVrms ( 0dB ), Ralc = GND 0.9 255 -1.0 1.0 300 -0.5 1.1 345 - V mVrms dB
GV1(COM) Vinc=1.3mVrms (-20dB), Gv1 (COM) = 20 x log (Voc1/Voc) + 10K GV2(COM) Vinc = 0.13mVrms (-40dB) Gv2 (COM) = 20 x log (Voc2/Voc) + 20K
-2.0
-1.0
-
dB
Compressor Output Distortion Mute Attenuation Ratio Compressor Limiting Voltaget ALC Splatter filter Expander
THDCOM ATTMUTE VLIM(COM) VALC Vo(SF)
Vinc = 0dB Vinc = 0dB Vinc = Variable IALC = 8uA ( RALC = 120k ) VINC = 13mVrms = 0dB
- 60 1.41 280 255
0.5 80 1.65 330 300
1.0 - 1.83 380 345
% dB Vp-p mVrms mVrms
(Vcc = 3.6V, fc = 1kHz, Ta = 25C, unless otherwise specified) Standard Output Voltage VO(EXP) Vine=30mVrms ( 0dB ) 104 130 156 mVrms
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S1T8527C
1 CHIP CLP SUBSYSTEM IC
ELECTRICAL CHARACTERISTICS (Continued)
Characteristic Expander Gain Difference Symbol GV1(EXP) Test Conditions Vine = 9.5mVrms (-10dB) Gv1(EXP) = 20 x log (Voe1/ Voe) + 20 Vine = 3mVrms (-20dB) Gv2 (EXP) = 20 x log (Voe2/Voe) + 40T Vine = 0.95mVrms (-30dB) Gv3 (EXP) = 20 x log (Voe3/Voe) + 60K VinE = 0dB VinE = 0dB Min. 0 Typ. 0.5 Max. 1.0 Unit dB
GV2(EXP)
0
1.0
2.0
dB
GV3(EXP)
0
1.5
3.0
dB
Expander Output Distortion Mute Attenuation Ratio Expander Maximum Output Voltage Speaker amp output 1 Speaker amp output 2 PLL
THDEXP ATTMUTE
- 60 500 104 104
0.5 80 600 130 130
1.0 - - 156 156
% dB mVrms mVrms mVrms
VOEXP(MAX) VinE = Variable THD = 10%l Vo( SA1) Vo( SA1) VINE = 30mVrms = 0 dB VINE = 30mVrms = 0 dB
( Vcc = 3.6V, Ta = 25C, unless otherwise specified ) Operating Current Input Current ICCPLL IIH IIL Input Voltage VIH VIL Output Current IOH IOL Output Voltage VOH1 VOL1 VOH2 VOL2 PLL regulator voltage VPLLREG Vout = Vcc Vout = 0V PDT, PDR: Io = -0.3mA ( Sourcing ) PDT, PDR: Io = 0.3mA ( Sinking ) LD, fMCU: Io = -0.1mA ( Sourcing ) LD, fMCU: Io = 0.1mA ( Sinking ) Vcc = 3.6V Vin = Vcc Vin = 0V - - - - -5 Vcc-0.3 - 0.3 0.3 Vcc-0.4 - Vcc-0.5 - 1.95 2.0 - - - - - - - - - - 2.15 3.5 5 - - 0.3 - - - 0.4 - 0.5 2.25 mA A A V V mA mA V V V V V
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1 CHIP CLP SUBSYSTEM IC
S1T8527C
PLL PROGRAM SUMMARY
MCU ( MICOM ) SERIAL INTERFACE ( MSB : 1ST INPUT ) Use CLK (Pin 7 ), DATA (Pin 8 ) , EN (Pin 9 ) terminals for program. DATA and CLK terminals are used for loading data to internal Shift - Register. When EN terminal is `Low' It is possible to program TX-Channel Counter, RX Channel Counter and various control functions of PLL. When EN terminal is `High' Program 1st Local Oscillator Capacitor Selection in receiver for U.S.A - 25 CH function. -- TX - Register, RX-Register, Control Register
MSB DATA
PMC0 PMC1 14 Bit DATA
LSB
EN CLK
-- Reference - Register
MSB DATA
PMC0 PMC1 UK_S1 UK_S0 12 Bit DATA
LSB
EN CLK
-- RECEIVER -1st local oscillator internal capacitor selection register & low battery detector voltage register [ CLO_LBD-Register ]
MSB DATA
PMC LBD3 LBD2 LBD1 LBD0 CLO5 CLO4 CLO3 CLO2 CLO1
LSB
CLO0
<1> EN CLK
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S1T8527C
1 CHIP CLP SUBSYSTEM IC
*
Programmable Counter -- RX - counter: Setting frequency for RX.VCO ( 14 Bits --> 1/16 -- 1/16383 ) [ Default_CH. = USA_#21 ( REMOTE ): 36.075MHz ( Div._NO = 7215 )]c < RX. Register (16bits) > Bit Name Default value 7215 Bit 15 PMC0 * Bit 14 PMC1 Bit 13 D13 0 Bit 12 D12 1 Bit 11 D11 1 Bit 10 D10 1 Bit 9 D9 0 Bit 8 D8 0
Bit Name Default value 7215
Bit 7 D7 0
Bit 6 D6 0
Bit 5 D5 1
Bit 4 D4 0
Bit 3 D3 1
Bit 2 D2 1
Bit 1 D1 1
Bit 0 D0 1
-- TX - counter: Setting frequency for TX.VCO ( 14 Bits --> 1/16 -- 1/16383 ) [ Default_CH. = USA_#21 ( REMOTE ): 49.830MHz ( Div._NO = 9966 )]' < TX. Register (16 bits) > Bit Name Default value 9966 Bit 15 PMC0 * Bit 14 PMC1 Bit 13 D13 0 Bit 12 D12 1 Bit 11 D11 1 Bit 10 D10 1 Bit 9 D9 0 Bit 8 D8 0
Bit Name Default value 9966
Bit 7 D7 1
Bit 6 D6 1
Bit 5 D5 1
Bit 4 D4 0
Bit 3 D3 1
Bit 2 D2 1
Bit 1 D1 1
Bit 0 D0 0
* Program mode control PMC0 0 1 PMC1 0 0 Program mode Control Block UPLL_Ref. Block PMC0 0 1 PMC1 1 1 Program mode UPLL_RX. Block UPLL_TX. Block
12
1 CHIP CLP SUBSYSTEM IC
S1T8527C
-- Ref - counter: Setting reference frequency for phase detector ( 12 Bits --> 1/16 ~ 1/4095 ) [ Default_Divider = 2048, X-tal_OSC = 10.240 MHz --> Fref = 5kHz ] < Ref. Register (16bits) > Bit Name Default value 2048 Bit 15 PMC0 * Bit 14 PMC1 Bit 13 UK_S1 Bit 12 UK_S0 Bit 11 D11 1 Bit 10 D10 0 Bit 9 D9 0 Bit 8 D8 0
Ref.freq. selection for United KingdomD
Bit Name Default value 2048
Bit 7 D7 0
Bit 6 D6 0
Bit 5 D5 0
Bit 4 D4 0
Bit 3 D3 0
Bit 2 D2 0
Bit 1 D1 0
Bit 0 D0 0
-- UK_Selection
UK_S0 0 1 0 1
UK_S1 0 0 1 1
FR1 fREF (A) fREF (A) fREF/4 (B) fREF/4 (B)
FR2 - fREF/4 (B) fREF/25 (C) fREF/25 (C)
FrefTX fREF (A) fREF/4 (B) fREF/4 (B) fREF/25 (C)
FrefRX fREF (A) fREF/4 (B) fREF/25 (C) fREF/4 (B)
fREF (A) 12 Bits Reference program divider. /4 / 25 fREF / 4 (B) fREF / 25 (C) FR2
PD_TX
FR1
LD
PDT PDR
PD_RX
Figure 1. < Reference frequency selection >
13
S1T8527C
1 CHIP CLP SUBSYSTEM IC
*
Control program -- Control register (16 Bits) Bit
Name
Bit 15
PMC0
Bit 14
PMC0 Program Mode Control_1
Bit 13
Don't Care
Bit 12
PLLTX-BS PLL_Tx Battery Save 0:Normal (PLL_TX-On) 1:PLL_TX Power-Off
Bit 11
CO_M Compress or Mute Selection 0:Normal 1:Mute
Bit 10
CO_BS Compress or Battery Save
Bit 9
CO_BS Expander Mute Selection
Bit 8
EX_BS Expander Battery Save 0: EX-On 1: Normal ( EX-part Power-Off )
Description Program Mode Control_0 Function
* Don't Program Latch Assign Care
0:Normal 0: CO-On 1: Normal ( CO-part 1:Mute Power-Off )
Bit
Name
Bit 7
LDT_ CDO
Bit 6
LBD-BS Low Battery Detector Battery Save 0:Normal (LBD-ON) 1:LBD-Part Power-Off
Bit 5
Rx-Bs RX Battery Save
Bit 4 -
Don't care
Bit 3 -
Don't care
Bit 2 -
Don't care
Bit 1
TEST2 TEST Mode 2
Bit 0
TEST1 TEST Mode 1
Description LDT or CDO Select
Function
LDT or CDO Select
0:Normal (RX-ON) 1:RX-Part Power-Offf
-
*** Function Test On each block of UPLL
*** TEST Mode & LDT-CDO Mode LDT/CDO 0 TEST1 0 1 0 1 1 0 1 0 1 TEST2 0 0 1 1 0 0 1 1 LDT / CDO Rx block CDO Rx block CDO 4_25cnt block FR2 4_25cnt block FR2 PLL block LDT PLL block LDT PLL block LDT Test PLL_TX Remark Default
14
1 CHIP CLP SUBSYSTEM IC
S1T8527C
*
Operating internal circuit blocks in each mode Mode ( state ) Active state ( Communication mode ) Operating circuit blocks PLL regulator/MICOM I/F ( Data, CLK, EN ) / 2nd local oscillator / Receiver / 1st local oscillator / RX PLL / Carrier detector / FSK comparator / Low battery detector / TX PLL / Expander & speaker amp / Compressor / Splatter filter amp PLL regulator / MICOM I/F ( Data, CLK, EN )/ 2nd local oscillator / Receiver / 1st local oscillator / RX PLL / Carrier detector / FSK comparator / Low battery detector. PLL regulator / MICOM I/F( Data, CLK, EN )
Receiving mode
Inactive state
*
CLO_LBD - Register Program [ Rx - 1'st local oscillation internal cap. for U.S.A - 25CH & Alarm sensor detect voltage ] -- CLO register ( 6 bits ) : Receiver 1'st local oscillator internal capacitor selection Bit Name
Default Value 0
Bit10 (MSB) PMC 1 ***** -
Bit 5 CLO5 0 0:Normal 1:Internal Cap. for USA 25 Channel = 4.4pF
Bit 4 CLO4 0 0:Normal 1:Internal Cap. for USA 25 Channel = 1.0pF
Bit 3 CLO3 0 0:Normal 1:Internal Cap. for USA 25 Channel = 3.6pF
Bit 2 CLO2 0 0:Normal 1:Internal Cap. for USA 25 Channel = 2.4pF
Bit 1 CLO1 0 0:Normal 1:Internal Cap. for USA 25 Channel = 1.2pF
Bit 0 CLO0 0 0:Normal 1:Internal Cap. for USA 25 Channel = 0.6pF
Function
*****PMC ( Program Mode Control ) PMC = `HIGH' & EN = `HIGH' ---> CLO_LBD Register Program Modeap -- Rx - Low Battery Detect Voltage Bit Name Default Value Function Bit 10(MSB) PMC 1* * * * * 1 Bit 9 LBD3 0 0 1 1 0 1 Bit 8 LBD2 0 0 0 1 1 1 Bit 7 LBD1 0 0 1 0 1 1 Bit 6 LBD0 0 0 1 1 1 1 Low Battery Detector Voltagef - 3.45V 3.3V 3.0V 2.2V 2.1V Remark
Default - - - - -
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S1T8527C
1 CHIP CLP SUBSYSTEM IC
***** PMC ( Program Mode Control ) PMC = `HIGH' & EN = `HIGH' ---> CLO - LBD Register Program Mode * Example 1 > Low battery detector voltage : 2.1V U.S.A _CH-#1 ( REMOTE ) ---> 1st local osc. varicap value = 15.86pF, Internal cap = 7.0pF ( Ext_L = 0.45uH, EXT_C = 30pF ) -- 12 bit data format
MSB Dummy
PMC bit 1( 0 ) LBD3 LBD2 1 1
LSB
LBD1 LBD0 CLO5 CLO4 CLO3 CLO2 CLO1 CLO0 1 1 0 1 1 1 0 0
DATA
1
EN CLK
In case the 12 bits programming, insert 1 don't care bit ( Dummy bit ) between PMC and LBD3. -- In case of setting 16 bit data format
MSB
PMC
Dummy bit
LSB
LBD3 LBD2 LBD1 LBD0 CLO5 CLO4 CLO3 CLO2 CLO1 CLO0
DATA
1
1( 0 ) 1( 0 ) 1( 0 ) 1( 0 ) 1( 0 )
1
1
1
1
0
1
1
1
0
0
EN CLK
In case of 16 bits programming, insert 5 don't care bits between the PMC and LBD3
16
1 CHIP CLP SUBSYSTEM IC
S1T8527C
EXAMPLE DATA FOR U.S.A 25_CHANNEL SELECTION
1' t Local Osc. Internal Capacitor Select s Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 (CLO5) (CLO4 (CLO3) (CLO2) (CLO1) (CLO0) 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 1 0 1 0 0 01 -- 04CH. 05 -- 10CH. 11 -- 15CH 01 -- 06CH. 07 -- 15CH. Base Hand Channels Channels 1-- 25CH. 16 -- 25CH. 16 -- 25CH. 1-- 25CH. Varicap Value
1.0V-- 2.0V
External C 27pF ( 30pF ) 27pF 30pF 27pF 27pF 27pF 30pF 30pF
External L 0.45uH 0.45uH 0.45uH 0.45uH 0.45uH 0.45uH 0.45uH 0.45uH
Internal C pF -
TYP 1.5Vo 18.73 -- 15.86pF
18.73 -- 15.86pF 18.73 -- 15.86pF 18.73 -- 15.86pF 18.73 -- 15.86pF 18.73 -- 15.86pF 18.73 -- 15.86pF
0.6 1.6 1.2 0.6 7.0 5.8
*
Phase detector / Lock Detector Output Waveforms
fREF (A) 12 Bits Reference program divider. FR1
REF.Freq
LD
/4 / 25
fREF / 4
(B) FR2
PD_TX
2LOI
fREF / 25
(C)
TIF / N
PDT
14 Bits TX. program divider.
TIF
17
S1T8527C
1 CHIP CLP SUBSYSTEM IC
REF.Freq.
TIF / N
PDT
LD
Figure 2. ( Phase Detector / Lock Detector Output Waveform )
18
C38 220uF L5 22uH R28
1 CHIP CLP SUBSYSTEM IC
CVI 20P T5
R33 C40 22K 10N
Y1 C45 10.24MHz 20P FLT3 455kHz C44 C43 33P 10N
R32 470K
VR1 50K R29 10K R30 27K C37 10N 10K C39 10N
C42 68N
33N
R34 51K C41
R31 27K
36 35 34 33 32 31 30 29 28 27 26 25 LD 2LDI 2LOI 2MO QCI RAO DSCI DSCO FET2 10.7MHz 37 2MI 38 1MO
C47 30P
LI
CDO
APPLICATION CIRCUIT (BASE SET)
(COMP) 24
VREF
C35 4.7uF R26 120K C34 3.3uF 100N C32 100N C33
R2 50K
VCC(RX)
ANT
39 1LOI 40 1LOI 41 VCORX 42 1MI 43 1MI 44 GND(PLL) 45 PDR 46 VREF(PLL) 47 VCC(PLL) 48 TIF PDT CO SFI SFO CLK EN LBD CRC 1
C17 12N R10 R11 10K 10K C24 2.2uF R44 10K DATA FROM MICOM (MCU)
GND(RX)
ALC 23 EPI 22 ERC 21 EO 20 SAI 19
R35 22 C46 10N T4 C49 (AW) R36
100N C50 2P T2 (AY) 56K R24 33K R25 51K C30 1.0N
FET1 25K544
C48 10N
L1 1.8uH
C51 10N
T3 (AY)
S1T8527C
SAO1 18 SAO2 17 VCC(COMP) 16 GND (COMP) 15 CPI+ 14 CPI- 13
68K C29 10N C28
RX DATA OUT RX OUT
R22
R37 100 RX
R39 R40 C57 10K 47N C58 10N
C52 0.47uF
MAIN POWER
10
ANT CDO/LDT GND(PLL) DATA AGIC
R41
COMPRESSOR INPUT
R19 100N C26 1.0uF R14 560
TX DUPLEX 2 3 4 5 6 7 8 9 10 11 12
C25 3.3uF
10
3.9K C53 10uF C56 10N
to MICOM (MCU)
TX VCO
to MICOM (MCU)
S1T8527C
19
S1T8527C
C43
10N
LD
2LDI
2LOI
2MO
QCI
RAO
DSCI
APPLICATION CIRCUIT (HAND SET)
VCC(RX)
GND(RX)
38 1MO
C47
DSCO
FET2 10.7MHz 37 2MI ALC 23 EPI 22
3.3uF 100N C32 100N R24 33K
C31 10P
LI
CDO
PDT
CO
SFI
SFO
CDO/LDT
GND(PLL)
CLK
DATA
EN
LBD
AGIC
CRC
20
C38 220uF L5 22uH R28 CVI 20P T5
R33 C40 22K 10N R31 27K
Y1 C45 10.24MHz 20P FLT3 455kHz C44 33P
R32 470K
VR1 50K R29 10K R30 27K C37 10N C36 68N R2 50K C35 4.7uF R26 120K C34 C33 10K C39 10N
C42 68N
R34 51K C41 33N
36 35 34 33 32 31 30 29 28 27 26 25
(COMP) 24
VREF
ANT
39 1LOI 40 1LOI 41 VCORX 42 1MI 43 1MI 44 GND(PLL) 45 PDR 46 VREF(PLL) 47 VCC(PLL) 48 TIF 1
C17 12N R10 R11 22K 10K C24 2.2uF R44 10K DATA FROM MICOM (MCU)
R35 22 C46 10N ERC 21 EO 20 SAI 19 T4 47P C49 (AW) R36
100N C50 2P T2 (AY) 120K
FET1 25K544
C48 10N
L1 1.8uH
C21 6P SAO1 18 SAO2 17 VCC(COMP) 16 GND (COMP) 15 CPI+ 14 CPI- 13
20K R19 C26 1N C29 10N R39 1.0K R40
C51 10N
T3 (AY)
S1T8527C
R25 51K C30 1.0N SPK 1 2
RX DATA OUT
R22
R37 100
C57 47N C58 10N
C52 1.0uF
RX
MAIN POWER
10 C28
ANT
10
R41
COMPRESSOR INPUT
100N
TX DUPLEX 2 3 4 5 6 7 8 9 10 11 12
C25 3.3uF
4.3K C53 10uF C56 10N
to MICOM (MCU)
TX VCO
1 CHIP CLP SUBSYSTEM IC
to MICOM (MCU)

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