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TDC1044A
Monolithic Video A/D Converter
4-Bit, 25 Msps Features
* * * * * * 4-bit resolution 1/4 LSB non-linearity Sample-and-hold circuit not required 25 Msps conversion rate Selectable output format 16-lead DIP and 20-lead PLCC packages
Description
The TDC1044A is a 25 Msps (Megasample per second) fullparallel analog-to-digital converter, capable of converting an analog signal with full-power frequency components up to 12.5 MHz into 4-bit digital words. Use of a sample-and-hold circuit is not necessary for operation of the TDC1044A. All digital inputs and outputs are TTL compatible. The TDC1044A consists of 15 latching comparators, encoding logic, and an output register. A single convert signal controls the conversion operation. Output formats are true/inverted binary or true/inverted offset two's complement codes.
Applications
* * * * Digital communications Video special effects Radar data conversion Medical imaging
Block Diagram
NMINV NLINV CONV VIN RT R1 R 2 R 1
R RM R 8 15 TO 4 DECODER LATCH 4 D1-D4
R 14
65-1044A-01
R 15 R/2 RB REFERENCE RESISTOR CHAIN
DIFFERENTIAL COMPARATORS (15)
Rev. 1.1.2
TDC1044A
PRODUCT SPECIFICATION
Functional Description
General Information
The TDC1044A has three functional sections: a comparator array, encoding logic, and an output register. The comparator array compares the input signal with 15 reference voltages to produce an N-of-15 thermometer code. All the comparators referred to voltages more positive than the input signal will be off, and those referred to voltages more negative than the input signal will be on. Encoding logic converts the N-of-15 code into binary or two's complement coding and can invert either output code. This coding function is controlled by DC signals on pins NMINV and NLINV. The output register holds the output constant between updates.
Controls
Two function control pins, NMINV and NLINV, set the output format to be either straight binary or offset two's complement, in either true or inverted sense, according to Table 1. These pins are active LOW as signified by the prefix "N" in the signal name. They may be tied to VCC for a logic "1" and DGND for a logic "0." NMINV controls the MSB, D1; NLINV controls the three LSBs: D2, D3 and D4.
Convert
The TDC1044A requires a CONVert (CONV) signal. A sample is taken (the comparators are latched) within tSTO after a rising edge of CONV. The coded result is translated to the output latches on the next rising edge. The outputs hold the previous data a minimum time (tHO) after the rising edge of the CONV signal. New data becomes valid after a maximum delay time, tD.
Power
The TDC1044A operates from two power supply voltages, +5.0V and -5.2V. The return for ICC (the current drawn from the +5.0V supply) is DGND. The return for IEE (the current drawn from the -5.2V supply) is AGND. All power and ground pins must be connected.
Analog Input
The TDC1044A uses latching comparators which cause the input impedance to vary slightly with the signal level. For optimal performance, the source impedance of the driving circuit must less than 25 Ohms. Within the range of VEE to +0.5V, the input signal will not damage the device. If the input signal is at a voltage between VRT and VRB, the output will be a binary code between 0 and 15 inclusive. A signal outside this range will indicate either full-scale positive or full-scale negative, depending on whether the signal is offscale in the positive or negative direction.
Reference
The TDC1044A converts analog signals in the range VRB VIN VRB into digital form. VRB (the voltage applied to RB at the bottom of the reference resistor chain) and VRT (the voltage applied to RB at the top of the reference resistor chain) should be between +0.1V and -1.1V. VRT should be more positive than VRB within that range. The voltage applied across the reference resistor chain (VRT - VRB) must be between 0.4V and 1.3V. Nominal voltages are VRT = 0.00V and VRB = -1.00V. These voltages may be varied dynamically up to 10MHz. Due to slight variation in the reference currents with clock and input signals, RT and RB should be low-impedance points. For circuits in which the reference is not varied, a bypass capacitor to ground is recommended. If the reference inputs are varied dynamically (as in an Automatic Gain Control circuit), a low-impedance reference source is required. A reference middle, RM, is also provided; this may be used as an input to adjust the mid-scale point in order to improve integral linearity. This point may also be used as a tap to supply a mid-scale voltage to offset the analog input. If VRM is used as an output, it must be connected to a high input impedance device which has small input current. Noise at this point may adversely affect the performance of this device.
Outputs
TDC1044A outputs are TTL compatible, and capable of driving four low-power Schottky TTL (54/74 LS) unit loads. The outputs hold the previous data a minimum time (tHO) after the rising edge of the CONV signal. Data becomes valid after a maximum delay time (tD) after the rising edge of CONV. For optimum performance, 2.2 kOhm pull-up resistors are recommended.
No Connects
Pin 3 of the TDC1044A is labeled No Connect (NC), and has no connection to the chip. Connect this pin to AGND for best noise performance.
2
PRODUCT SPECIFICATION
TDC1044A
Table 1. Output Coding1
Binary Range -1.00V FS 0.000V -0.067V -0.133V -0.200V -0.267V -0.333V -0.400V -0.467V -0.533V -0.600V -0.667V -0.733V -0.800V -0.867V -0.933V -1.000V True NMINV = 1 NLINV = 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Inverted 0 0 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Offset Two's Complement True 0 1 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 Inverted 1 0 0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000
Note: 1. Input voltages are at code centers.
Pin Assignments
D1 (MSB) D4 (LSB) DGND
D3
D2
18
17
16
15
NC CONV AGND VIN NC
14
AGND VCC NMINV RM NLINV NC VIN NC RT RB VEE NLINV RM
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
65-1044A-03
CONV D4 (LSB) D3 D2 D1 (MSB) DGND VCC NMINV
19 20 1 2 3
13 12 11 10 9
4
5
6
7
RT
NC
NC
RB
VEE
8
65-1044A-02
20 Lead PLCC
16 Lead DIP
3
TDC1044A
PRODUCT SPECIFICATION
Pin Descriptions
Pin Number Pin Name Power VCC VEE DGND AGND Reference RT RM RB Control NMINV NLINV Convert CONV Analog Input VIN Output D1 D2 D3 D4 NC 12 13 14 15 3 15 16 17 18 3, 5, 6, 9, 19 TTL TTL TTL TTL AGND LSB Output No Connect MSB Output 2 2 0V to -1V Analog Input Signal 16 20 TTL Convert 9 7 12 10 TTL TTL Not MSB Invert Not LSB Invert 4 8 5 4 11 7 0.0V -0.5V -1.0V Reference Resistor, Top Reference Resistor, Middle Reference Resistor, Bottom 10 6 11 1 13 8 14 1 +5.0V -5.2V 0.0V 0.0V Positive Supply Voltage Negative Supply Voltage Digital Ground Analog Ground DIP PLCC Value Description
4
PRODUCT SPECIFICATION
TDC1044A
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Type Supply Voltages Parameter VCC (measured to DGND) VEE (measured to AGND) AGND (measured to DGND) Input Voltages CONV, NMINV, NLINV (measured to DGND) VIN, VRT, VRB (measured to AGND) VRT (measured to VRB) Output Applied voltage (measured to DGND Applied current, externally Temperature Operating, ambient Operating, junction Lead, soldering (10 seconds) Storage -65 forced3,4 )2 Min -0.5 +0.5 -0.5 -0.5 +0.5 -2.2 -0.5 -1.0 -55 Max 7.0 -7.0 +0.5 +5.5 VEE +2.2 +5.5 +6.0 1 +125 +150 +300 +150 Unit V V V V V V V mA sec C C C C
Short circuit duration (single output in high state to ground)
Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as positive when flowing into the device.
Operating Conditions
Parameter VCC VEE VAGND tPWL tPWH VIL VIH IOL IOH VRT VRB VRT - VRB VIN TA Positive Supply Voltage (measured to DGND) Negative Supply Voltage (measured to AGND) Analog Ground Voltage (measured to DGND) CONV Pulse Width, LOW CONV Pulse Width, HIGH Input Voltage, Logic LOW Input Voltage, Logic HIGH Output Current, Logic LOW Output Current, Logic HIGH Most Positive Reference Most Negative Reference Reference Differential Input Voltage Ambient Temperature, Still Air -1.9 -2.1 0.2 VRB 0 0.0 -1.0 1.0 2.0 4.0 -400 0.1 -0.1 2.0 VRT 70 Min. 4.75 -4.9 -0.1 17 17 0.8 Nom. 5.0 -5.2 0.0 Max. 5.25 -5.5 0.1 Units V V V ns ns V V mA mA V V V V C
5
TDC1044A
PRODUCT SPECIFICATION
Electrical Characteristics
Within specified operating conditions Parameter ICC IEE Positive Supply Current Negative Supply Current Test Conditions VCC = Max, static1 VEE = Max, static TA = 0C to 70C TA = 70C IREF RREF RIN CIN ICB IIL Reference Current Total Reference Resistance Input Equivalent Resistance Input Capacitance Input Constant Bias Current Input Current, Logic LOW VEE = Max VCC = Max, VI - 0.5V CONV NMINV, NLINV IIH II VOL VOH IOS CI Input Current, Logic HIGH Input Current, Max Input Voltage Output Voltage, Logic LOW Output Voltage, Logic HIGH Short Circuit Output Current Digital Input Capacitance VCC = Max, VI = 2.4V VCC = Max, VI = 5.5V VCC = Min, IOL = Max VCC = Min, IOH = Max VCC = Max, One pin to ground, one second duration, Output HIGH TA = 25C, F = 1 MHz 2.4 -300 15 -0.8 -0.8 200 1.0 0.5 mA mA mA mA V V mA pF VRT, VRB = Nom, VIN = VRB VRT, VRB = Nom 500 250 25 40 -50 -40 2 mA mA mA Ohms Kohms pF mA Min. Max. 15 Units mA
Note: 1. Worst case: all digital inputs and outputs LOW.
Switching Characteristics
Within specified operating conditions Parameter FS tSTO tD tHO Maximum Conversion Rate Sampling Time Offset Digital Output Delay Digital Output Hold Time Test Conditions VCC = Min, VEE = Min VCC = Min, VEE = Min VCC = Min, VEE = Min, Load 1 VCC = Max, VEE = Max, Load 1 5 Min. 25 10 30 Max. Units Msps ns ns ns
6
PRODUCT SPECIFICATION
TDC1044A
System Performance Characteristics
Within specified operating conditions Parameter ELI ELD CS EOT EOB TCO BW tTR EAP Linearity Error Integral Independent Linearity Error Differential Code Size Offset Error Top Offset Error Bottom Offset Error Temperature Coefficient Bandwidth, Full Power Input Transient Response, Full Scale Aperture Error 12.5 10 30 VRT, VRB = Nom VIN = VRT VIN = VRB 75 Test Conditions VRB = Nom Min. Max. 1.6 1.6 125 +30 +40 20 Units % % % Nominal mV mV mV/C MHz ns ps
Timing Diagram
1 FS CONV tPWH tPWL
SAMPLE N
SAMPLE N+1
SAMPLE N+2
ANALOG INPUT tSTO DIGITAL OUTPUT tHO tD DATA N-1 DATA N DATA N+1
65-1044A-04
7
TDC1044A
PRODUCT SPECIFICATION
Equivalent Circuits
VIN CIN ICB
VIN
1-OF-15 COMPARATORS
RIN
VRB REFERENCE RESISTOR CHAIN VEEA
65-1044A-05
VEE
VEE
Figure 1. Simplified Analog Input Equivalent Circuit
VCC TO OUTPUT PIN VCC 20K 10K OUTPUT
+VCC 8101/2
40pF
1N3062
INPUT OUTPUT EQUIVALENT CIRCUIT LOAD 1 TEST LOAD FOR DELAY MEASUREMENTS
65-1044A-07
65-1044A-06
Figure 2. Digital Input Equivalent Circuit
Figure 3. Output Circuits
8
PRODUCT SPECIFICATION
TDC1044A
Applications Discussion
Calibration
To calibrate the TDC1044A, adjust VRT and VRB to set the 1st and 15th thresholds to the desired voltages. Assuming a 0V to -1V desired range, continuously strobe the converter with -0.0033V (1/2 LSB from 0.000V) on the analog input, and adjust VRT for output toggling between codes 0000 and 0001. Then apply -0.976V (1/2 LSB from -1.000V) and adjust VRB for toggling between codes 1110 and 1111. Instead of adjusting VRT, RT can be connected to analog ground and the 0V end of the range calibrated with an amplifier offset control. RB is a convenient point for gain adjustment that is not in the analog signal path.
input increases from zero to one volt, VIN of the TDC1044A decreases from zero to -1 volt. With true binary selected (NMINV = 1 and NLINV = 1), output codes increase from 0000 to 1111. A small value resistor, R12, serves to isolate the small input capacitance of the A/D converter from the amplifier output and insure frequency stability. Pulse and frequency response of the amplifier are optimized by variable capacitor C12. The reference voltage for the TDC1044A is generated by amplifier U3. System gain is adjusted by varying R9, which controls the reference voltage level to the A/D converter. Input voltage range and input impedance for the circuit are determined by resistors R1 and R2. Formulas for calculating values for these input resistors are: 1 R1 = ---------------------------------2VR o 1 ae ----------- - ----------e Z IN o 1000 and 1000 R1 R2 = Z IN - ae ------------------------ o e 1000 + R1 o where VR is the input voltage range of the circuit, ZIN is the input impedance of the circuit, and the constant 1000 comes from the value of R3. As shown, the circuit is set up for 1Vp-p 75 Ohm video input.
Typical Interface Circuit
The TDC1044A does not require a special input buffer amplifier to drive the analog input because of its low input capacitance. A terminated low-impedance transmission line (<100 Ohms) connected to the VIN terminal of the device is sufficient if the input voltage levels match those of the A/D converter. However, many driver circuits lack sufficient offset control, drive current, or gain stability. The typical interface circuit in Figure 4 shows a simple amplifier and voltage reference circuit that may be used with the device. U2 is a wide-band operational amplifier with a gain factor of -1. As the video
9
TDC1044A
PRODUCT SPECIFICATION
+5V R5 220 L1 FERRITE BEAD INDUCTOR
C1 10 25V
+
10 VCC D0 (MSB) 3 NC D1 13 12
R13 2.2K
C12 1-6pF VIDEO INPUT 1Vp-p R1 37.4 R2 39.2 R3 1K R4 2K
R14 2.2K
C9 10 0.1 14 - 50V R6 2K
U2 HA-2539
R7 1K
8
R12 27
2 1 4
R15 2.2K VIN AGND RT D3 (LSB) 15 D2 14 R16 2.2K
1
+ 3
C3 + 10 24V
U4 LM313
R9 2K 10-TURN "GAIN"
C10 0.1 50V
C7 0.1 50V
R8 2K 10-TURN "OFFSET"
C8 0.1 50V R11 10K
L2 FERRITE BEAD INDUCTOR
AGND 8 5 RM RB
2
7 -
U3 LM741C
C5 0.1 50V 6 C6 0.1 50V
C4 10 25V
C11 0.1 50V 11
U1 TDC1044A
DGND NLINV 7 9 NMINV 16 CONV VEE 4 + C2 10 25V
65-1044A-08
3
+ 4
DGND
CLK -5.2V
Figure 4. Typical Interface Circuit
10
PRODUCT SPECIFICATION
TDC1044A
Notes:
11
TDC1044A
PRODUCT SPECIFICATION
Notes:
12
PRODUCT SPECIFICATION
TDC1044A
Mechanical Dimensions
16-Lead Ceramic DIP Package
Inches Min. A b1 b2 c1 D E e eA L Q s1 a Max. Millimeters Min. Max. 8 2 8 4 4 5, 9 7 3 6 Notes: Notes 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 8, 9 and 16 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within .010 (.25mm) of its exact longitudinal position relative to pins 1 and 16. 6. Applies to all four corners (leads number 1, 8, 9, and 16). 7. "eA" shall be measured at the center of the lead bends or at the centerline of the leads when "a" is 90. 8. All leads - Increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. 9. Fourteen spaces. D
8 1
Symbol
-- .200 .014 .023 .050 .065 .008 .015 .745 .840 .220 .310 .100 BSC .300 BSC .115 .160 .015 .060 .005 -- 90 105
-- 5.08 .36 .58 1.27 1.65 .20 .38 18.92 21.33 5.59 7.87 2.54 BSC 7.62 BSC 2.92 4.06 .38 1.52 .13 -- 90 105
NOTE 1
E
9
16
s1 eA
e
A Q L b1 a c1
13
TDC1044A
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
16-Lead Plastic DIP Package
Inches Min. A A1 A2 B B1 C D D1 E E1 e eB L N -- .015 .115 Max. .210 -- .195 Millimeters Min. -- .38 2.93 Max. 5.33 -- 4.95 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are shown for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2
Symbol
.014 .022 .045 .070 .008 .015 .745 .840 .005 -- .300 .325 .240 .280 .100 BSC -- .430 .115 .160 16
.36 .56 1.14 1.78 .20 .38 18.92 21.33 .13 -- 7.62 8.26 6.10 7.11 2.54 BSC -- 10.92 2.92 4.06 16
2
5
D 8 1
E1
D1
9
16
E e A A1 L B1 B eB A2 C
14
PRODUCT SPECIFICATION
TDC1044A
Mechanical Dimensions (continued)
20-Lead PLCC Package
Inches Min. A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 2. Corner and edge chamfer (J) = 45 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .245" (.101mm)
Symbol
.165 .180 .090 .120 .020 -- .013 .021 .026 .032 .385 .395 .350 .356 .200 BSC .050 BSC .042 .048 5 20 -- .004
4.19 4.57 2.29 3.05 .51 -- .33 .53 .66 .81 9.78 10.03 8.89 9.04 5.08 BSC 1.27 BSC 1.07 1.22 5 20 -- 0.10
3
2
E E1 J
D
D1
D3/E3
e
B1
J
A A1 A2 B -C- LEAD COPLANARITY
ccc C
15
TDC1044A
PRODUCT SPECIFICATION
Ordering Information
Product Number TDC1044AB9C TDC1044AN9C TDC1044AR4C Temperature Range 0C to 70C 0C to 70C 0C to 70C Screening Commercial Commercial Commercial Package 16-Lead Ceramic DIP 16-Lead Plastic DIP 20-Lead PLCC Package Marking 1044AB9C 1044AN9C 1044AR4C
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS7001044A O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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