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FEATURES 200 MSPS Guaranteed Conversion Rate 135 MSPS Low Cost Version Available 350 MHz Analog Bandwidth 1 V p-p Analog Input Range Internal +2.5 V Reference and T/H Low Power: 500 mW +5 V Single Supply Operation TTL Output Interface Single or Demultiplexed Output Ports APPLICATIONS RGB Graphics Processing High Resolution Video Digital Data Storage Read Channels Digital Communications Digital Instrumentation Medical Imaging
VREF IN
8-Bit, 200 MSPS A/D Converter AD9054
FUNCTIONAL BLOCK DIAGRAM
VREF OUT
AD9054
AIN AIN ENCODE ENCODE T/H QUANTIZER
2.5V REFERENCE 8 ENCODE LOGIC DEMULTIPLEXER 8
DA7 -DA0 DB7 -DB0
TIMING
VDD
GND
DEMUX
DS
DS
GENERAL DESCRIPTION
The AD9054 is an 8-bit monolithic analog-to-digital converter optimized for high speed, low power, small size and ease of use. With a 200 MSPS encode rate capability and full-power analog bandwidth of 350 MHz, the component is ideal for applications requiring the highest possible dynamic performance. To minimize system cost and power dissipation, the AD9054 includes an internal +2.5 V reference and track-and-hold circuit. The user provides only a +5 V power supply and an encode clock. No external reference or driver components are required for many applications.
The AD9054's encode input interfaces directly to TTL, CMOS or positive-ECL logic and will operate with single-ended or differential inputs. The user may select dual-channel or singlechannel digital outputs. The dual (demultiplexed) mode interleaves ADC data through two 8-bit channels at one-half the clock rate. Operation in demultiplexed mode reduces the speed and cost of external digital interfaces while allowing the ADC to be clocked to the full 200 MSPS conversion rate. In the singlechannel (nondemultiplexed) mode, all data is piped at the full clock rate to the Channel A outputs. Fabricated with an advanced BiCMOS process, the AD9054 is provided in a space-saving 44-lead TQFP surface mount plastic package (ST-44) and specified over the full industrial (-40C to +85C) temperature range.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1997
AD9054-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (V
Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes Gain Error1 Gain Tempco1 ANALOG INPUT Input Voltage Range (With Respect to AIN) Compliance Range AIN or AIN Input Offset Voltage Input Resistance Input Capacitance Input Bias Current Analog Bandwidth, Full Power 2 REFERENCE OUTPUT Output Voltage Temperature Coefficient SWITCHING PERFORMANCE Maximum Conversion Rate (f S) Minimum Conversion Rate (f S) Encode Pulsewidth High (tEH) Encode Pulsewidth Low (t EL) Aperture Delay (tA) Aperture Uncertainty (Jitter) Data Sync Setup Time (t SDS) Data Sync Hold Time (t HDS) Data Sync Pulsewidth (t PWDS) Output Valid Time (t V)3 Output Propagation Delay (t PD)3 DIGITAL INPUTS HIGH Level Current (I IH)4 LOW Level Current (I IL)4 Input Capacitance DIFFERENTIAL INPUTS Differential Signal Amplitude (VID) HIGH Input Voltage (VIHD) LOW Input Voltage (V ILD) Common-Mode Input (V ICM) DEMUX INPUT HIGH Input Voltage (V IH) LOW Input Voltage (V IL) DIGITAL OUTPUTS HIGH Input Voltage (V OH) LOW Input Voltage (V OL) Output Coding +25C Full +25C Full Full +25C Full I VI I VI VI I V Temp
DD
= +5 V, external reference, fS = max unless otherwise noted)
Test Level Min AD9054BST-200 Typ Max 8 0.9 1.0 0.6 0.9 Guaranteed 2 160 +1.5/-1.0 +2.0/-1.0 1.5 2.0 7 AD9054BST-135 Min Typ Max 8 0.9 1.0 0.6 0.9 Guaranteed 2 160 +1.5/-1.0 +2.0/-1.0 1.5 2.0 7 Units Bits LSB LSB LSB LSB % FS ppm/C
Full Full +25C Full +25C Full +25C +25C Full +25C Full Full Full Full +25C +25C +25C +25C +25C +25C +25C Full Full Full Full +25C Full Full Full Full Full Full Full Full
V V I VI I VI V I VI V VI V VI IV IV IV V V IV IV IV VI VI VI VI V IV IV IV IV IV IV VI VI
512 1.8 4 8 62 4 25 350 2.4 2.5 110 2.6 2.4 3.2 16 19 1.8
512 4 8 62 4 25 350 2.5 110 2.6 3.2 16 19
36 23
36 23 50 75
50 75
mV p-p V mV mV k k pF A A MHz V ppm/C MSPS MSPS ns ns ns ps rms ns ns ns ns ns A A pF mV V V V V V V V
200 2.0 2.0 0.5 2.3 0 0.5 2.0 2.7 25 15 15
135 3.0 3.0 0.5 2.3 0 0.5 2.0 2.7 7.9 625 625 25 15 15
5.1 5.9 500 500 3
5.7 7.5 500 500 3
8.5 625 625
400 1.5 0 1.5 2.0 0 2.4
VDD VDD - 0.4
400 1.5 0 1.5 2.0 0 2.4
VDD VDD - 0.4
VDD 0.8
VDD 0.8
0.4 Binary Binary
0.4
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AD9054
Parameter POWER SUPPLY VDD Supply Current (IDD) Power Dissipation5, 6 Power Supply Sensitivity 7 DYNAMIC PERFORMANCE Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 19.7 MHz fIN = 49.7 MHz fIN = 70.1 MHz Signal-to-Noise Ratio (SINAD) (With Harmonics) fIN = 19.7 MHz fIN = 49.7 MHz fIN = 70.1 MHz Effective Number of Bits fIN = 19.7 MHz fIN = 49.7 MHz fIN = 70.1 MHz 2nd Harmonic Distortion fIN = 19.7 MHz fIN = 49.7 MHz fIN = 70.1 MHz 3rd Harmonic Distortion fIN = 19.7 MHz fIN = 49.7 MHz fIN = 70.1 MHz Two-Tone Intermod Distortion (IMD) fIN = 19.7 MHz fIN = 49.7 MHz fIN = 70.1 MHz
8
Temp Full Full +25C +25C +25C
Test Level VI VI I V V
AD9054BST-200 Min Typ Max 100 500 0.005 1.5 1.5 145 725 0.015
AD9054BST-135 Min Typ Max 100 500 0.005 1.5 1.5 140 700 0.015
Units mA mW V/V ns ns
+25C Full +25C Full +25C Full
IV V I V I V
42 42 42
45 45 45 45 45 45
42 42
45 45 45 45
dB dB dB dB dB dB
+25C Full +25C Full +25C Full +25C +25C +25C +25C +25C +25C +25C +25C +25C
IV V I V I V IV I I IV I I IV I I
40 40 39
43 43 43 43 42 42 6.85 6.85 6.85 63 59 55 56 54 50
40 40
43 43 43 43
dB dB dB dB dB dB Bits Bits Bits dBc dBc dBc dBc dBc dBc
6.35 6.35 6.18 58 54 52 48 48 43
6.35 6.35
6.85 6.85
58 54
63 59
48 48
56 54
+25C +25C +25C
V V V
60 55 50
60 55
dBc dBc dBc
NOTES 1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference). 2 3 dB bandwidth with full-power input signal. 3 tV and tPD are measured from the threshold crossing of the ENCODE input to valid TTL levels of the digital outputs. The output ac load during test is 5 pF (Refer to equivalent circuits Figures 5 and 6). 4 IIH and IIL are valid for differential input voltages of less than 1.5 V. At higher differential voltages, the input current will increase to a maximum of 1.25 mA. 5 Power dissipation is measured under the following conditions: analog input is -1 dBfs at 19.7 MHz. 6 Typical thermal impedance for the ST-44 (TQFP) 44-lead package (in still air): JC = 20C/W, CA = 35C/W, JA = 55C/W. 7 A change in input offset voltage with respect to a change in V DD. 8 SNR/harmonics based on an analog input voltage of -1.0 dBfs referenced to a 1.024 V full-scale input range. Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS Test Level
IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at +25C; guaranteed by design and characterization testing for industrial temperature range.
I. 100% production tested. II. 100% production tested at +25C and sample tested at specified temperatures. III. Sample tested only.
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AD9054
ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS Pin Number 1 Name ENCODE Function Encode Clock for ADC (ADC Samples on Rising Edge of ENCODE). Encode Clock Complement (ADC Samples on Falling Edge of ENCODE). Power Supply (+5 V). Ground.
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to 0.0 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to 0.0 V VREF IN, VREF OUT . . . . . . . . . . . . . . . . . . . VDD to 0.0 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . +175C Maximum Case Temperature . . . . . . . . . . . . . . . . . . +150C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
2
ENCODE
3, 5, 15, 18, 28, VDD 30, 31, 36, 41 4, 6, 16, 17, 27, GND 29, 32, 35, 37, 40 14-7 DA0-DA7 19-26
Table I. Output Coding
Step 255 254 253 * * * 129 128 127 126 * * * 2 1 0
AIN-AIN 0.512 V 0.508 V 0.504 V * * * 0.006 V 0.002 V -0.002 V -0.006 V * * * -0.504 V -0.508 V -0.512 V
Code 255 254 253 * * * 129 128 127 126 * * * 2 1 0
Binary 1111 1111 1111 1110 1111 1101 * * * 1000 0001 1000 0000 0111 1111 0111 1110 * * * 0000 0010 0000 0001 0000 0000
33
34 38
39 42
43 44
Digital Outputs of ADC Channel A. DA7 is the MSB, DA0 the LSB. DB0-DB7 Digital Outputs of ADC Channel B. DB7 is the MSB, DB0 the LSB. VREF OUT Internal Reference Output (+2.5 V typical); Bypass with 0.1 F to Ground. VREF IN Reference Input for ADC (+2.5 V typical, 4%). AIN Analog Input--Complement. Connect to input signal midscale reference. AIN Analog Input--True. DEMUX Format Select. LOW = Dual. Channel Mode, HIGH = Single. Channel Mode (Channel A Only). DS Data Sync Complement. DS Data Sync--Aligns output channels in Dual-Channel Mode. PIN CONFIGURATION
Model AD9054BST-200 AD9054BST-135 AD9054/PCB
Temperature Range -40C to +85C -40C to +85C +25C
Package Option* ST-44 ST-44 Evaluation Board
VREF IN GND VDD GND AIN AIN GND VDD DEMUX DS DS
VREF OUT
GND
GND
VDD
GND
VDD
VDD
DB7 (MSB)
ORDERING GUIDE
DB6
DB5
DB4
DB3 DB2 DB1 DB0 (LSB)
*ST = Plastic Thin Quad Flatpack (TQFP).
AD9054
TOP VIEW (PINS DOWN)
VDD GND GND VDD DA0 (LSB) DA1
PIN 1 IDENTIFIER
DA2
ENCODE
DA7 (MSB)
VDD
GND
VDD
ENCODE
GND
DA6
DA5
DA4
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9054 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
DA3
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AD9054
SAMPLE N SAMPLE N+3 SAMPLE N+4
SAMPLE N-1
AIN
SAMPLE N+1 SAMPLE N+2
tA tEH ENCODE tEL
1/fS
ENCODE tPD
tV
D7 -D 0
DATA N-5
DATA N-4
DATA N-3
DATA N-2
DATA N-1
DATA N
Figure 1. Timing--Single Channel Mode
SAMPLE N-1
SAMPLE N
SAMPLE N+3
SAMPLE N+4
SAMPLE N+5
AIN
SAMPLE N-2 SAMPLE N+1 1/fS SAMPLE N+2 SAMPLE N+6
tA tEH tEL
ENCODE ENCODE
tHDS tSDS
tHDS tSDS
DS DS tPWDS PORT A D7 -D 0
DATA N-7 OR N-8
tPD
DATA N-7 OR N-6 INVALID IF OUT OF SYNC DATA N-4 IF IN SYNC
tV
DATA N-2
DATA N
PORT B D7 -D 0
DATA N-8 OR N-7
DATA N-6 OR N-7
INVALID IF OUT OF SYNC DATA N-5 IF IN SYNC
DATA N-3
DATA N-1
DATA N+1
Figure 2. Timing--Dual Channel Mode
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AD9054
EQUIVALENT CIRCUITS
VDD
17.5k DEMUX 300 300
VDD
AIN
AIN
7.5k
Figure 3. Equivalent Analog Input Circuit
VDD
Figure 6. Equivalent DEMUX Input Circuit
VDD
VREF IN
DIGITAL OUTPUTS
Figure 4. Equivalent Reference Input Circuit
VDD 17.5k ENCODE OR DS 300 300 ENCODE OR DS
Figure 7. Equivalent Digital Output Circuit
VDD
7.5k
VREF OUT
Figure 5. Equivalent ENCODE and Data Select Input Circuit
Figure 8. Equivalent Reference Output Circuit
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Typical Performance Characteristics- AD9054
55
45.4 45.2
50
50MHz 20MHz
SNR 45
45.0 44.8
dB
dB
SINAD 40 NYQUIST FREQUENCY (100MHz)
70MHz 44.6 44.4 44.2
35
30
0
20
40
60 80 fIN - MHz
100
120
140
44.0 -45
0
25 TC - C
70
90
Figure 9. SNR vs. fIN: fS = 200 MSPS
Figure 12. SNR vs. Temperature, fS = 135 MSPS
50 49 48 47 46
46.0 45.8 45.6 20MHz 45.4 50MHz 45.2
SNR
dB
dB
45 44 43 42 41 40 25 50 75
45.0 44.8 44.6 44.4 44.2
70MHz
SINAD
100 125 150 175 200 225 250 270 fS - MSPS
300
44.0 -60
-40
-20
0
20 40 TC - C
60
80
100
Figure 10. SNR vs. fS: fIN = 19.7 MHz
Figure 13. SNR vs. Temperature, fS = 200 MSPS
50 SNR 45 SINAD 40
50 48 46 44 42 FS = 135MSPS FIN = 10.3MHz
dB
dB
35
SNR 40 38
30
SINAD 36
25
34 32
20 25
50
75
100
125 150 175 200 225 250 fS - MSPS
270 300
30 0.0
1.0
2.0
3.0 4.0 5.0 6.0 ENCODE PULSEWIDTH - ns
7.0
8.0
Figure 11. SNR vs. fS: fIN = 70.1 MHz
Figure 14. SNR vs. Clock Pulsewidth, (tPWH): fS = 135 MSPS
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AD9054
50 48 46 44 SINAD 42
dBc -70
FS = 200MSPS FIN = 10.3MHz
-68
2ND HARMONIC
SNR
-66 -64 -62 -60 -58 -56 -54 -52 -50 -48 3RD HARMONIC
dB
40 38 36 34 32 30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ENCODE PULSEWIDTH - ns 4.5 5.0
-46 25
50
75
100 125 150 175 200 225 250 fS - MSPS
270 300
Figure 15. SNR vs. Clock Pulsewidth, (tPWH): fS = 200 MSPS
Figure 18. Harmonic Distortion vs. fS: fIN = 19.7 MHz
46 45
-60
-50 44 20MHz -40 43 3RD HARMONIC 70MHz 50MHz 41 40 39 38 -60 -10 -20 -30 2ND HARMONIC
dB
42
-40
-20
0
20 40 TC - C
60
80
100
0 25
50
75
100 125
150 175
200 225 250 270 300
fS - MSPS
Figure 16. SINAD vs. Temperature: fS = 135 MSPS
Figure 19. Harmonic Distortion vs. fS: fIN = 70.1 MHz
46 45
-40
-45
44 20MHz 43 50MHz
-50
dB
dB
42 70MHz 41
-55 70MHz -60
40 39 38 -60
50MHz -65 20MHz
-40
-20
0
20 40 TC - C
60
80
100
-70 -60
-40
-20
0
20 TC - C
40
60
80
100
Figure 17. SINAD vs. Temperature: fS = 200 MSPS
Figure 20. 2nd Harmonic vs. Temperature: fS = 135 MSPS
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AD9054
-40 0 -45 -1
-50
-2
dB
-55 70MHz -60 50MHz -65 20MHz -70 -60 -40 -20 0 20 TC - C 40 60 80 100
dB
-3
-4 NYQUIST FREQUENCY 100MHz -5
-6 0 50 100 150 200 250 300 fIN - MHz 350 400 450 500
Figure 21. 2nd Harmonic vs. Temperature: fS = 200 MSPS
Figure 24. Frequency Response: fS = 200 MSPS
-40
0 -10 FUNDAMENTAL = -0.5dBfs SNR = 45.8dB SINAD = 45.2dB 2ND HARMONIC = 69.8dB 3RD HARMONIC = 61.6dB
-45
-20
-50 70MHz 50MHz
-30 -40
dB
dB
-55 20MHz -60
-50 -60 -70
-65
-80
-70 -60
-40
-20
0
20 TC - C
40
60
80
100
-90 0
10
20
30
40
50 60 MHz
70
80
90
100
Figure 22. 3rd Harmonic vs. Temperature: fS = 135 MSPS
Figure 25. Spectrum: fS = 200 MSPS, fIN = 19.7 MHz
-40
0 -10 FUNDAMENTAL = -0.5dBfs SNR = 44.6dB SINAD = 37.6dB 2ND HARMONIC = -63.1dB 3RD HARMONIC = -39.1dB
-45 70MHz -50 50MHz
dB
dB
-20 -30 -40 -50 -60 -70
-55 20MHz -60
-65
-80
-70 -60
-90
-40
-20
0
20 TC - C
40
60
80
100
0
10
20
30
40
50 60 MHz
70
80
90
100
Figure 23. 3rd Harmonic vs. Temperature: fS = 200 MSPS
Figure 26. Spectrum: fS = 200 MSPS, fIN = 70.1 MHz
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AD9054
0 -10 -20 -30 -40
dB
7
F1 = 55.0MHz F2 = 56.0MHz F1 = F2 = -7.0dBfs
6 5 4
ns
tPD tV
-50 -60 -70 -80
3 2 1
-90 -100 0 10 20 30 40 50 60 MHz 70 80 90 100
0 -60 -40 -20 0 20 TC - C 40 60 80 100
Figure 27. Two Tone Intermodulation Distortion
Figure 30. Output Delay vs. Temperature
5.0 4.5 4.0 3.5
2.55 2.54 2.53 2.52
VOH - Volts
3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0 -1.0 -2.0 -3.0 -4.0 -5.0 -6.0 -7.0 -8.0 -9.0 -10.0 IOH - mA
VREF OUT - Volts
2.51 2.50 2.49 2.48 2.47 2.46 2.45 -20 -18 -16 -14 -12 -10 -8 -6 IREF OUT - mA -4 -2 0 2
Figure 28. Output Voltage HIGH vs. Output Current
Figure 31. Reference Voltage vs. Reference Load
1.0 0.9 0.8
2.502
2.501
VREF OUT - Volts 0.7
VOL - Volts
0.6 0.5 0.4 0.3
2.500
2.499
0.2 0.1 0.0 0.0 1.0 2.0 3.0 4.0 5.0 IOL - mA 6.0 7.0 8.0
2.498 3.0
3.5
4.0
4.5 5.0 VDD - Volts
5.5
6.0
6.5
Figure 29. Output Voltage LOW vs. Output Current
Figure 32. Reference Voltage vs. Power Supply Voltage
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AD9054
2.502
rapidly slewing signal. The AD9054's extremely wide bandwidth Track/Hold circuit processes these signals without difficulty.
Using the AD9054
2.501
2.500
2.499
Good high speed design practices must be followed when using the AD9054. To obtain maximum benefit, decoupling capacitors should be physically as close to the chip as possible. We recommend placing a 0.1 F capacitor at each power-ground pin pair (9 total) for high frequency decoupling, and including one 10 F capacitor for local low frequency decoupling. The VREF IN pin should also be decoupled by a 0.1 F capacitor. The part should be located on a solid ground plane and output trace lengths should be short (<1 inch) to minimize transmission line effects. This avoids the need for termination resistors on the output bus and reduces the load capacitance that needs to be driven, which in turn minimizes on-chip noise due to heavy current flow in the outputs. We have obtained optimum performance on our evaluation board by tying all VDD pins to a quiet analog power supply system, and tying all GND pins to a quiet analog system ground.
Minimum Encode Rate
VREF OUT - Volts
2.498 -40
-20
0
20
40
60
80
100
TAMB - C
Figure 33. Reference Voltage vs. Temperature
APPLICATION NOTES
THEORY OF OPERATION
The AD9054 combines Analog Devices' patented MagAmp bitper-stage architecture with flash converter technology to create a high performance, low power ADC. For ease of use the part includes an onboard reference and input logic that accepts TTL, CMOS or PECL levels. The analog input signal is buffered by a high-speed differential amplifier and applied to a track-and-hold (T/H) circuit. This T/H captures the value of the input at the sampling instant and maintains it for the duration of the conversion. The sampling and conversion process is initiated by a rising edge on the ENCODE input. Once the signal is captured by the T/H, the four Most Significant Bits (MSBs) are sequentially encoded by the MagAmp string. The residue signal is then encoded by a flash comparator string to generate the four Least Significant Bits (LSBs). The comparator outputs are decoded and combined into the eight-bit result. If the user has selected Single Channel Mode (DEMUX = HIGH), the eight-bit data word is directed to the Channel A output bank. Data are strobed to the output on the rising edge of the ENCODE input with four pipeline delays. If the user has selected Dual Channel Mode (DEMUX = LOW) the data are alternately directed between the A and B output banks and have five pipeline delays. At power-up, the N sample data can appear at either the A or B port. To align the data in a known state the user must strobe DATA SYNC (DS, DS) per the conditions described in the Timing section.
Graphics Applications
The minimum sampling rate for the AD9054 is 25 MHz. To achieve very high sampling rates, the track/hold circuit employs a very small hold capacitor. When operated below the minimum guaranteed sampling rate, the T/H droop becomes excessive. This is first observed as an increase in offset voltage, followed by degraded linearity at even lower frequencies. Lower effective sampling rates may be easily supported by operating the converter in dual port output mode and using only one output channel. A majority of the power dissipated by the AD9054 is static (not related to conversion rate) so the penalty for clocking at twice the desired rate is not high.
Reference
The AD9054 internal reference, VREF, provides a simple, cost effective reference for many applications. It exhibits reasonable accuracy and excellent stability over power supply and temperature variations. The VREF OUT pin can simply be strapped to the VREF IN pin. The internal reference can be used to drive additional loads (up to several mA), including multiple A/D converters as might be required in a triple video converter application. When an external reference is desired for accuracy or other requirements, the AD9054 should be driven directly by the external reference source connected to pin VREF IN (VREF OUT can be left floating). The external reference can be set to 2.5 V 0.25 V. If VREF IN is raised by 10% (set to 2.75 V) the analog full-scale range will increase by 10% to 1.024 x 1.1 = 1.1264 V. The new input range will then be AIN 0.5632 V.
Digital Inputs
The high bandwidth and low power of the AD9054 make it very attractive for applications that require the digitization of presampled waveforms, wherein the input signal rapidly slews from one level to another and is relatively stable for a period of time. Examples of these include digitizing the output of computer graphic display systems and very high speed solid state imagers. These applications require the converter to process inputs with frequency components well in excess of the sampling rate (often with subnanosecond rise times), after which the A/D must settle and sample the input in well under one pixel time. The architecture of the AD9054 is vastly superior to older flash architectures, which not only exhibit excessive input capacitance (which is very hard to drive) but can make major errors when fed a very REV. 0
SNR performance is directly related to the sampling clock stability in A/D converters, particularly for high input frequencies and wide bandwidths. A low jitter clock (<10 ps @ 100 MHz) is essential for optimum performance when digitizing signals that are not presampled. ENCODE and Data Select (DS) can be driven differentially or single-ended. For single-ended operation, the complement inputs (ENCODE, DS) are internally biased to VDD/3 (~1.5 V) by a high impedance on-chip resistor divider (Figure 5), but they may be externally driven to establish an alternate threshold if desired. A 0.1 F decoupling capacitor to ground is sufficient to maintain a threshold appropriate for TTL or CMOS logic.
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AD9054
When driven differentially, ENCODE and DS will accommodate differential signals centered between 1.5 V and 4.5 V with a total differential swing 800 mV (VID 400 mV). Note the 6-diode clock input protection circuitry in Figure 5. This limits the differential input voltage to ~ 2.1 V. When the diodes turn on, current is limited by the 300 series resistor. Exceeding 2.1 V across the differential inputs will have no impact on the performance of the converter, but be aware of the clock signal distortion that may be produced by the nonlinear impedance at the converter.
VIH D VIC M VIL D VID CLOCK NC = NO CONNECT NC VREF OUT 0.1 F VREF IN AIN 1k VIN 0.1 F AIN A PORT
AD9054
+5V
DEMUX
DS CLOCK CLOCK ENC ENC
DS
ENC
ENC 0.1 F
a. Driving Differential Inputs Differentially
VIH D VID VIC M VIL D
Figure 35. Single Port Mode--AC-Coupled Input--SingleEnded Encode
Dual Port Mode
CLOCK
ENC ENC
0.1 F
b. Driving Differential Inputs Single-Endedly
Figure 34. Input Signal Level Definitions
Single Port Mode
In Dual Port Mode (DEMUX = LOW), the conversion results are alternated between the two output ports (Figure 2). This limits the data output rate at either port to 1/2 the conversion rate (ENCODE), and supports conversion at up to 200 MSPS with TTL/CMOS compatible interfaces. Dual Channel Mode is required for guaranteed operation above 100 MSPS, but may be enabled at any specified conversion rate. The multiplexing is controlled internally via a clock divider, which introduces a degree of ambiguity in the port assignments. Figure 2 illustrates that, prior to synchronization, either Port A or Port B may produce the even or odd samples. This is resolved by exercising the Data Sync (DS) control, a differential input (identical to the ENCODE input), which facilitates operation at high speed. At least once after power-up, and prior to using the conversion data, the part needs to be synchronized by a falling edge (or a positive-going pulse) on DS (observing setup and hold times with respect to ENCODE). If the converter's internal timing is in conflict with the DS signal when it is exercised, then two data samples (one on each port) are corrupted as the converter is resynchronized. The converter then produces data with a known phase relationship from that point forward. Note that if the converter is already properly synchronized, the DS pulse has no effect on the output data. This allows the converter to be continuously resynchronized by a pulse at 1/2 the ENCODE rate. This signal is often available within a system, as it represents the master clock rate for the demultiplexed output data. Of course, a single DS signal may be used to synchronize multiple A/D converters in a multichannel system. Applications that call for the AD9054 to be synchronized at power-up or only periodically during calibration/reset (i.e., valid data is not required prior to synchronization), need only be concerned with the timing of the falling edge of DS. The falling edge of DS must satisfy the setup time defined by Figure 2 and
When operated in a Single Port mode (DEMUX = HIGH), the timing of the AD9054 is similar to any high speed A/D Converter (Figure 1). A sample is taken on every rising edge of ENCODE, and the resulting data is produced on the output pins following the FOURTH rising edge of ENCODE after the sample was taken (four pipeline delays). The output data are valid tPD after the rising edge of ENCODE, and remain valid until at least tV after the next rising edge of ENCODE. The maximum clock rate is specified as 100 MSPS. This is recommended because the guaranteed output data valid time equals the Clock Period (1/fS) minus the Output Propagation Delay (tPD) plus the Output Valid Time (tV), which comes to 4.8 ns at 100 MHz. This is about as fast as standard logic is able to capture the data with reasonable design margins. The AD9054 will operate faster in single-channel mode if you are able to capture the data. When operating in Single-Channel Mode, the outputs at Port B are held static in a random state. Figure 35 shows the AD9054 used in single-channel output mode. The analog input (0.5 V) is ac coupled and the ENCODE input is driven by a TTL level signal. The chip's internal reference is used.
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AD9054
the specification table. In this case the DS hold time specification on the rising edge can be ignored. Applications that will continuously update the synchronization command need to treat the DS signal as a pulse and satisfy timing requirements on both rising and falling edges. It is easiest to consider the DS signal in this case to be a pulse train at one half the encode rate, the positive pulse nominally bracketing the ENCODE falling edge on alternate cycles as shown in the timing diagram (Figure 2). The falling/rising edge of DS has to satisfy a minimum setup time (TSDS) before the rising/falling edge of ENCODE; similarly, the rising/falling edge of DS has to satisfy a minimum hold time (THDS) relative to the rising/falling edge of ENCODE. DS can fall a minimum of THDS after ENCODE falls and a maximum of TSDS before the next ENCODE rises. DS can rise a minimum of THDS after ENCODE rises and a maximum of TSDS before ENCODE falls. This timing requirement produces a tight timing window at higher encode rates. Synchronization by a single reset edge results in a simpler timing solution in many applications. For example, synchronization may be provided at the beginning of each graphics line or frame. The data are presented at the output of the AD9054 in a pingpong (alternating) fashion to optimize the performance of the converter. It may be aligned for presentation as sixteen bits in parallel by adding a register stage to the output. In Dual Channel Mode, the converted data is produced five clock cycles after the rising edge of ENCODE on which the sample is taken (five pipeline delays).
VREF OUT 0.1 F VREF IN AIN 1k VIN 0.1 F B PORT AIN A PORT
AD9054
'573
DEMUX
DS DS CLOCK '74 DIVIDE BY 2
DS
ENC
ENC 0.1 F
NC
NC = NO CONNECT
Figure 36. Dual Port Mode--Aligned Output Data
In Figure 36, the converter is operating in Dual Port Mode, with data coming alternately out of Port A and Port B. The figure illustrates how the output data may be aligned with an output latch to produce a 16-bit output at 1/2 the conversion clock rate. The Data Sync input must be properly exercised to time the A Port with the synchronizing latch.
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AD9054
EVALUATION BOARD Voltage Reference
The AD9054 evaluation board offers an easy way to test the AD9054. It provides dc biasing for the analog input, generates the latch clocks for both full speed and demuxed modes, and includes a reconstruction DAC. The board has several different modes of operation, and is shipped in the following configuration: * * * * DC-Coupled Analog Input Demuxed Outputs Differential Clocks Internal Voltage Reference.
DC BIAS S102 AIN S103 VREF OUT VREF IN 50 AIN A PORT '574 VREF EXT
The AD9054 has an internal 2.5 V voltage reference. An external reference may be employed instead. The evaluation board is configured for the internal reference. To use an external reference, connect it to the (VREF) pin on the power connector and move jumper S102.
Single Port Mode
Single Port Mode sets the AD9054 to produce data on every clock cycle on output port A only. To test in this mode, jumper S104 should be set to single channel and S106 and S107 must be set to F (for Full). The maximum speed in single port mode is 100 MSPS.
Dual Port Mode
AD9054
AIN RESET BUTTON 5V D D FF C S105 CLK A DS DS ENC ENC S104 DEMUX A PORT '574
Dual Port or half speed output mode sets the ADC to produce data alternately on Port A and Port B. In this mode, the reset function should be implemented. To test in this mode, set jumper S104 to Dual Channel, and set S106 and S107 to D (for Dual Port). The maximum speed in this mode is 200 MSPS.
RESET
CLK B ENC 50 ENC ENC 50 CLK A
DAC
RESET drives the AD9054's Data Sync (DS) pins. When operating in Single Port Mode, RESET is not used. In DualChannel Mode it is needed for two reasons: to synchronize the timing of Port A data and Port B data with a known clock edge, as described in the data sheet, and to synchronize the evaluation board's latch clocks with the data coming out of the AD9054. Reset can be driven in two ways: by pushing the reset button on the board, or externally, with a TTL pulse through connector J5 or J6.
DAC Out
ENC CLOCKING CLK B
The DAC output is a representation of the data on output Port A only. Output Port B is not reconstructed.
Troubleshooting
Figure 37. PCB Block Diagram
Analog Input
If the board does not seem to be working correctly, try the following: * Check that all jumpers are in the correct position for the desired mode of operation. * Push the reset button. This will align the 9054's data output with the half speed latch clocks. * Switch the jumper S105 from A-R to R-B or vice-versa, then push the reset button. In demuxed mode, this will have the effect of inverting the half speed latch clocks. * At high encode rates, the evaluation board's clock generation circuitry is sensitive to the +5 V digital power supply. At high encode rates, the +5 V digital power should be kept below +5.2 V. This is an evaluation board sensitivity and not an AD9054 sensitivity. The AD9054 Evaluation Board is provided as a design example for customers of Analog Devices, Inc. ADI makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose.
The evaluation board accepts a 1 V input signal centered at ground. The board's input circuitry then biases this signal to +2.5 V in one of two ways: 1. DC-coupled through an AD9631 op amp; this is the mode in which it is shipped. Potentiometer R7 provides adjustment of the bias voltage. 2. AC-coupled through C1. These two modes are selected by jumpers S101 and S103. For dc coupling, the S101 jumper is connected between the two left pins and the S103 jumper is connected between the two lower pins. For ac coupling, the S101 jumper is connected between the two right pins and the S103 jumper is connected between the two upper pins.
ENCODE
The AD9054 ENCODE input can be driven two ways: 1. Differential TTL, CMOS, or PECL; it is shipped in this mode. 2. Single-ended TTL or CMOS. To use in this mode, remove R11, the 50 chip resistor located next to the ENCODE input, and insert a 0.1 F ceramic capacitor into the C5 slot. C5 is located between the ENC connector and the ENCODE input to the DUT and is marked on the back side of the board. In this mode, ENCODE is biased with internal resistors to 1.5 V, but it can be externally driven to any dc voltage.
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C35 0.1 F 1 33 R21
GND VDD VDD GND VDD GND DB7 DB6 DB5 DB4
GND +5VA +5VA GND +5VA GND
VDD GND VDD GND
+5V +5V +5VA 1 11
+5VA GND +5VA GND
GND 1 R12 1k 4 2 D Q 3 PR 5
ENC ENC
B1 BUTTON
C4 0.1 F
+5V
RST
DA7 DA6 DA5 DA4 DA3
BNC J3
4 6 S1 2 7 D1 Q1 6 11
ENC
U6 5 10H131
DVDD
AVDD
COMP2
COMP1
FSADJ
REFIO
REFLO
Figure 38. Evaluation Board Schematic
SLEEP
R11 49.9
2 3
10H125 U7
4
28
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB)
REV. 0
R8 2k C2 0.1 F 3 2 C3 10 F
R6 2k
R7 1k
R3 100
S102 JUMPER U4 74F574DW H20SM J5 R21-R39 100
23 RST GND 1 12
VREF
C37 DRPF J6
20 RESET
U1 AD9631R
3 6 2 R5 10 1 R4 140 2 3
S103 JUMPER
S101 JUMPER R2
BNC J1 UA1
3
140
AIN
C1 0.1 F 11 1 R9 100
2
9 8 7 6 5 4 3 2 12 13 14 15 16 17 18 19 11 10 9 8 7 6 5 4 1D 2D 3D 4D 5D 6D 7D 8D CK 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q OE +5VA GND GND +5VA
R1 49.9
1
AD9054BST
U5 74F574DW
9 8 7 6 5 4 3 2 1D 2D 3D 4D 5D 6D 7D 8D CK 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q OE 1 11 12 13 14 15 16 17 18 19
29 28 27 26 25 24 23 22
B1B B2B B3B B4B B5B B6B B7B B8B 2 2
C36, C37, AND R17-R20 NOT INSTALLED FOR STANDARD OPERATION
GND 2 3
34 35 GND 36 +5VA 37 GND 38 39 40 GND 41 +5VA 42 43 S104 44 JUMPER DB3 DB2 DB1 (LSB) DB0 VDD GND GND VDD (LSB) DA0 DA1 DA2 13 14 15 16 17 18 19 20 22 21 20 19 18 17 16 15 14 13 12
VREF OUT VREF IN GND VDD GND AIN AIN GND VDD DEMUX DS DS
DRB 30 31 32 33 34 35 36 37 B8A B7A B6A B5A B4A B3A B2A B1A 3 R39 21
6 CQ CL U2 1 74F74
S105 JUMPER
3 2 1
DRA
BNC J2
+5V
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5PB 510 RP1 AD96685R U3
3 12 -5.2V GND
123456
ENC
C5
R10 49.9
1 2 3 4 5 6 7 8 9 10 22 CLK
BNC J4 U8 AD9760AR
A I OUT B R16 49.9 21 R15 49.9
DAC OUT
10H125 U7 6
7 5 +5V
27 24 23 19 C6 0.1 F
18
17 16 15 R14 2k C8 0.1 F
TB1
1 2 3 -5.2V GND +5V 4 5 +5VA 3 2 1 VREF
Q1 3 R1 4
S107 JUMPER
3 2 1
10H125 10 U7
11
12
S106 JUMPER
C7 0.1 F
10H125 14 U7
15
+5V 13
VREF +5V ANALOG -5.2V GROUND +5V DIGITAL
+5V C12 0.1 F C13 0.1 F -5.2V C26 0.1 F C27 0.1 F C29 0.1 F C30 10 F C31 0.1 F C32 0.1 F C33 0.1 F C34 0.1 F C14 0.1 F C15 0.1 F C16 0.1 F C17 0.1 F C18 0.1 F C19 0.1 F C20 0.1 F C21 0.1 F C22 0.1 F C28 0.1 F
C9 10 F
C10 0.1 F
C11 0.1 F
+5VA
AD9054
C23 10 F
C24 0.1 F
C25 0.1 F
AD9054
Figure 39. Assembly--Top View
Figure 41. Conductors--Top View
Figure 40. Assembly--Bottom View
Figure 42. Conductors--Bottom View
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AD9054
BILL OF MATERIALS
GS00104 REV. B ITEM 11 QTY 30 PART NUMBER GRM40Z5U104M050BL REFERENCE C1, C2, C4, C6-8, C10-C22, C24-C29, C31-C35 R5 R3, R9, R21-R39 C3, C9, C23, C30 R2, R4 R12 R6, R8, R14 R7 J6 R1, R10, R11, R15, R16 RP1 TB1 TB1 J1-J4 U6 U7 U2 J5 J5 U3 S101-S107 S101-S107, GND DESCRIPTION 0.1 F CER CHIP CAP 0805 MFG/DISTRIBUTOR TTI
12 13 14 15 16 17 18 19 10
1 21 4 2 1 3 1 1 5
P10FBK-ND P100FBK-ND T491C106M016AS P140FBK-ND P1KFBK-ND P2KFBK-ND 3296W-102-ND K44-C37S-QJ P49.9FBK-ND
10 SURFACE MT RES 1206 100 SURFACE MT RES 1206 10 F TANTALUM CHIP CAP 140 SURFACE MT RES 1206 1 k SURFACE MT RES 1206 2 k SURFACE MT RES 1206 1k TRIM POT TOP ADJ, 25 TURN 37P D CONN RT ANG PCMT FEM 49.9 SURFACE MT RES 1206 510 6P BUSED RES NETWORK 8291Z 3-PIN TERMINAL BLOCK 8291Z 2-PIN TERMINAL BLOCK BNC COAX CONN PCMT 5 LEAD DIP-16 DUAL D FLIP-FLOP DIP-16 QUAD ECL TO TTL TRANS SO-14 FAST TTL DUAL D FLIP-FLOP HEADER STRIP 20P GOLD MALE 40P HEADER HIGH SPEED COMP SOIC-16 SHORTING JUMPER 3-PIN HEADER (DIVIDE 1 OF THE 8 FOR 3 GND HOLES) SO-20 OCTAL D TYPE FLIP-FLOP SOIC-8 OP AMP 10-BIT CMOS DAC SOIC-28 TQFP-44 DUAL 8-BIT ADC SURFACE MOUNT MOMENTARY PUSHBUTTON BUMPON PROTECTIVE BUMPER
DIGI-KEY DIGI-KEY TTI DIGI-KEY DIGI-KEY DIGI-KEY DIGI-KEY CENTURY ELEC DIGI-KEY
11 12 13 14 15 16 17 18 ALT: 19 20 21
1 1 1 4 1 1 1 1 1/2 1 7 8
CSC06A-01-511G 51F54113 51F54112 AMP-227699-2 MC10H131P MC10H125P 74F74SC-ND TSW-120-08-G-S 90F3987 AD96685BR S90F9280 89F4700
TTI NEWARK NEWARK TIME ELEC HAMILTON/HALLMARK HAMILTON/HALLMARK DIGI-KEY SAMTEC NEWARK ANALOG DEVICES, INC. NEWARK NEWARK
22 23 24 25 26
2 1 1 1 1
MC74F574DW AD9631AR AD9760AR AD9054ST P8002SCT-ND
U4, U5 U1 U8 UA1 B1
HAMILTON/HALLMARK ANALOG DEVICES, INC. ANALOG DEVICES, INC. ANALOG DEVICES, INC. DIGI-KEY
27
4
90F1533
-
NEWARK
PARTS NOT ON BILL OF MATERIALS, AND NOT TO BE INSTALLED: C5, C36, C37, R17-R20.
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AD9054
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Lead Plastic Thin Quad Flatpack (TQFP) (ST-44)
0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45)
34 33
0.472 (12.00) SQ
23 22
SEATING PLANE TOP VIEW
(PINS DOWN)
0.394 (10.0) SQ
44 1 11
12
0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.35)
0.031 (0.80) BSC
0.018 (0.45) 0.012 (0.30)
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C3146-8-10/97
PRINTED IN U.S.A.

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