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Features
* * * * * * * * *
Supports PCMCIA PC Card Standard - Release 2.1 Directly connects to PCMCIA Connector No Additional Circuits Required 256 x 8 Internal Parallel E2PROM for CIS Endurance: 10,000 Write Cycles Data Retention: 10 Years Internally Controlled Write Algorithm Operates over VCC = 4.5 to 5.5 Volts 64 Pin TQFP, Max. Height = 1.2 mm Mounted Usage is Two Devices Per Card Dual Mode Device with Mode Select Pin Supports Up to 64 Mbytes of: Flash E2PROM SRAM ROM OTP
Description
The AT43101 is a low power, high integration PCMCIA interface chip set for memory cards. It provides a complete PCMCIA PC Card Standard Release 2.1 compliant interface with no other support devices. Two AT43101's are used on each memory card. A mode select pin configures the device for operation as a low order address and data buffer when low and as the high order address buffer/decoder when high. The two devices together form a complete address and data buffer, address decoder, memory device selection logic, read and write control logic and a Card Information Structure (CIS). Eight chip enable outputs are provided, supporting 16 memory devices. The device is pinned out for direct connection to the PCMCIA connector without PC trace cross-overs. Its 1.0 mm thick body allows population of both sides of a Type 1 PCMCIA card.
PCMCIA Card Memory Interface Circuit with 256 Bytes of Internal Attribute Memory EEPROM AT43101
B/A*=VSS
ICE0*
ICE1*
ICE2*
ICE3*
ICE4*
ICE5*
ICE6* 51
CE2*
CE1*
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
64
63
62
61
60
59
58
57
56
55
54
53
52
50
ICE7*
REG*
SEL1
VDD
VDD
IA23
IA24
D0
D8
OE* D1 D9 D2 D10 D3 D11 VSS D4 D12 D5 D13 D6 D14 D7 D15
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43
A8 ID1 ID9 ID2 ID10 ID3 ID11 VSS ID4 ID12 ID5 ID13 ID6 ID14 ID7 ID15
49
B/A*=VDD
SGL/DBL*
WP IWP*
WE*
A7
A6
A5
A4
A0
A3
A2
A1
A10 A11 A17 A18 A19 A20 A21 VSS SEL0 A9 A13 A14 A16 A15 A12 A22
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43
IA10 IA11 IA17 IA18 IA19 IA20 IA21 VSS Reset IA9 IA13 IA14 IA16 IA15 IA12 IA22
AT43101
MODE A
42 41 40 39 38 37 36 35 34 33
AT43101
MODE B
42 41 40 39 38 37 36 35 34 33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
17
18
19
20
21
22
23
24
25
26
27
28
29
30 IOEL*
31 IWEH*
IA8
IA7
IA6
IA5
IA4
WPATT IA3
VDD
IA2
IA1
R/B*
A23
REG*
OE*
A24
VDD
IR*
IOEH*
Reset
IR/B*
CE2*
CE1*
A0
DEC0
DEC1
DEC2
ID0
ID8
WE*
IWEL*
32
Pin Configuration
AT43101 pins are defined by the following two tables. The Pin Descriptions Table lists and describes the function of each signal used in the chip set. The Pin Assignment Table lists the signals connected to each pin for each mode and the buffer type implemented for the corresponding pin. The buffer type listed in the Pin Assignment Table does not always agree with the signal type listed in the Pin Description Table because the chip implements buffer types that support both modes of each pin. The pullup resistors included on chip as shown in the table have a nominal value of 375K ohms. An asterisk, "*", appended to a signal name indicates the signal is active low.
AT43101 Logical Pin Descriptions
Name D[15:0] A[24:0] CE2* CE1* OE* WE* REG* ID[15:0] IA[24:1] SGL/DBL* SEL[1:0] B/A* DEC[2:0] IOEH* IOEL* IWEH* IWEL* IWP* WP ICE[7:0]* Reset IR* WPATT R/B* IR/B* Type Bidir Input Input Input Input Input Input Bidir Output Input Input Input Input Output Output Output Output Input Output Output Input Output Input Output Input Description PCMCIA Data Bus PCMCIA Address Bus Active low, PCMCIA byte enable for odd byte Active low, PCMCIA byte enable for even byte Active low, PCMCIA output enable signal Active low, PCMCIA write enable signal PCMCIA signal high for common memory, low for attribute memory Memory data bus Memory address bus Address decoder mode control input per function table Address decoder selection inputs per function table Mode select input. Low selects mode A, High selects mode B. Address Inputs decoded to generate ICE[7:0]* outputs Active low output enable for upper byte of memory Active low output enable for lower byte of memory Active low write enable for upper byte of memory Active low write enable for lower byte of memory Input from write protect switch Output to PCMCIA write protect signal Active low chip enable outputs for 8 pairs of memory devices Active high reset Output of inverted reset Active high attribute memory protect signal Output from IR/B* and attribute memory Ready/Busy* Active low Ready/Busy* input for common memory
2
AT43101
AT43101
AT43101 Physical Pin Assignments
Pkg Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Mode A OE* D1 D9 D2 D10 D3 D11 VSS D4 D12 D5 D13 D6 D14 D7 D15 Reset pd IR* IA8 IA7 IA6 IA5 IA4 VDD WPATT pd IA3 IA2 IA1 ID0 ID8 R/B* IR/B* pu Mode B A10 A11 A17 A18 A19 A20 A21 VSS SEL0 pu A9 A13 A14 A16 A15 A12 A22 CE2* pu CE1* pu WE* pu REG* pu OE* pu A23 A24 VDD A0 DEC0 DEC1 DEC2 IOEH* IOEL* IWEH* IWEL* Input Bidir Bidir Bidir Bidir Bidir Output Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Input Bidir Bidir Bidir Bidir Bidir Bidir Type Input Bidir Bidir Bidir Bidir Bidir Bidir Mode A ID15 ID7 ID14 ID6 ID13 ID5 ID12 ID4 VSS ID11 ID3 ID10 ID2 ID9 ID1 A8 B/A* D8 D0 A1 A2 A3 A0 VDD A4 A5 A6 A7 REG* pu WE* pu CE1* pu CE2* pu Mode B IA22 IA12 IA15 IA16 IA14 IA13 IA9 Reset pd VSS IA21 IA20 IA19 IA18 IA17 IA11 IA10 B/A* ICE7* ICE6* ICE5* ICE4* ICE3* ICE2* VDD ICE1* ICE0* IA24 IA23 SEL1 pu IWP* WP SGL/DBL* pu Bidir Bidir Bidir Bidir Input Input Bidir Input Bidir Bidir Bidir Bidir Bidir Bidir Bidir Input Bidir Bidir Bidir Bidir Bidir Bidir Type Bidir Bidir Bidir Bidir Bidir Bidir Bidir Bidir Pkg Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Note: pu after a pin name indicates a pull up. pd after a pin name indicates a pull down.
3
System Block Diagram
WP DEC[2:0] SEL[1:0] WE* REG* A0 SGL/DBL* A[24:9] CE2* CE1* OE* RESET IWP* ICE[7:0]* IWEH* IOEH* IOEL* IWEL*
IA[24:9]
AT43101"B"
OE* CE* WE*
MEMORY DEVICE
OE* CE* WE*
MEMORY DEVICE
OE* CE* WE*
MEMORY DEVICE
DATA
DATA
DATA
D[15:0] REG* OE* WE* CE1* CE2* A[8:0]
IR/B*
INTERNAL DATA BUS: ID[15:0]
AT43101"A"
WPATT
IA[8:1]
DATA
DATA
DATA
MEMORY DEVICE
MEMORY DEVICE
MEMORY DEVICE
OE* CE* WE*
OE* CE* WE*
OE* CE* WE*
RESET R/B*
IR*
Operation
The AT43101 is used in pairs to implement PCMCIA Release 2.1 compatible memory cards as shown in the system block diagram and in the internal chip block diagrams. Both PCMCIA signals and memory devices connect directly to the AT43101 with no additional components required. The AT43101 acts as a data and address buffer and address and control signal decoder for both an external memory array and an internal 256x8 E2PROM which contains the Card Information Structure. The memory card is mapped into the Common Memory Address Space of PCMCIA according to the address signals connected to the DEC[2:0], SEL[1:0], and SGL/DBL* inputs. In a typical configuration, SGL/DBL* and SEL[1:0] are tied high or left floating since they are pulled up internally. Then DEC[2:0] function as direct inputs to the address/chip enable decoder. For example, A[25:23] are connected to DEC[2:0] and IA[22:1] are connected to A[21:0] of sixteen 4 Mbyte devices. Note that A0 is used in conjunction with CE1* and CE2* to 4 decode the data access and is not used as a common memory address. A[25:23] then determine which ICE[7:0] line is active. Mixed memory size applications can use SGL/DBL* pulled low to enable a mixed mode decoding. This then enables either DEC[2:0] or SEL[1:0] as inputs to the address/chip enable decoder based on the state of SEL[1:0]. For example, the common memory space contains eight 1 Mbyte SRAM devices and six 4 Mbyte Flash devices. A[22:21] are connected to DEC[1:0] (DEC[2] is a don't care) and A[24:23] are connected to SEL[1:0]. Then IA[22:1] are used to connect to A[19:0] of the SRAM and A[21:0] of the Flash devices. ICE[3:0]* are connected to the four SRAM banks and ICE[7:5] to the three Flash banks. The SRAM is then memory mapped to the lower 4 M words of addressing and the Flash to the next 12 M words. All addressing is contiguous. Notice that ICE4* can not be used with this decoding scheme.
AT43101
AT43101
Address Decoder Operation
SGL/DBL* = H SEL[1:0] XX XX XX XX XX XX XX XX DEC[2:0] LLL LLH LHL LHH HLL HLH HHL HHH ICE[7:0]* HHHHHHHL HHHHHHLH HHHHHLHH HHHHLHHH HHHLHHHH HHLHHHHH HLHHHHHH LHHHHHHH LH HL HH XXX XXX XXX HHLHHHHH HLHHHHHH LHHHHHHH SEL[1:0] LL LL LL LL SGL/DBL* = L DEC[2:0] XLL XLH XHL XHH ICE[7:0]* HHHHHHHL HHHHHHLH HHHHHLHH HHHHLHHH
The AT43101 provides separate output and write enables for the upper and lower bytes of the memory array to implement byte addressing. The assertion of these outputs under the
control of A0, CE2*, CE1*, OE* and WE* is given by the following table when REG* is high.
Byte Control Logic Operation
OE* H L L L L L H H H H H WE* H H H H H H L L L L L CE2* X H H H L L H H H L L CE1* X H L L H L H L L H L A0 X X L H X X X L H X X IOEL* H H L H H L H H H H H IOEH* H H H L L L H H H H H IWEL* H H H H H H H L H H L IWEH* H H H H H H H H L L L
The IWP* input provides write protection for common memory. When IWP* is low, assertion of IWEL* and IWEH* is inhibited. The WPATT input provides write protection for the attribute memory when high. This signal is pulled down internally for applications not requiring write
protection. In addition, the AT43101 is disabled for 3 milliseconds during power up to prevent writes from occurring to either attribute or common memory. The state of the A*/B pin is also latched at this time. The AT43101 does not support the optional PCMCIA WAIT* signal.
5
Block Diagram for Mode B Operation
ADDRESS BUFFER
A[24:9]
IA[24:9]
ICE7*
SGL/DBL* DEC[2:0] SEL[1:0] SGL/DBL* LOGIC
3
DEC
ONE OF EIGHT DECODER
ICE6* ICE5* ICE4* ICE3* ICE2* ICE1* ICE0*
REG*
EN EN EN
Reset WE*
WP
BYTE WRITE CONTROL LOGIC
IWEH* IWEL*
IWP*
CE1* CE2* A0 OE*
The AT43101 supports both Common and Attribute Memory read and write cycles of word and byte width. Common memory, the external memory devices on the PC card, is selected when REG* is high and can be accessed in either byte or word mode. Attribute memory, the internal 256x8 E2PROM, is selected when REG* is low and can only be accessed as the even byte of it's 512 byte address space. Byte/word addressing is controlled by CE1*, CE2* and A0. OE* functions as an active low output enable. WE* functions as an active low write enable. Memory access functionality is defined by the following table. When Attribute Memory is selected by the assertion
BYTE READ CONTROL LOGIC
IOEH* IOEL*
of REG*, only the lower data bus, D[7:0] is valid and only even numbered addresses may be accessed. Accordingly, an entry of "H or L" in the REG* of the function table means the access is supported for both Common Memory and Attribute Memory. An entry of "H only" means the access is supported for Common Memory accesses but not for Attribute Memory accesses. During word accesses of Common Memory, D[15:0] and ID[15:0] are active. During byte accesses (other than Odd Byte Only accesses), the PCMCIA transfers take place on D[7:0] and the AT43101 performs the required byte lane swapping based on A0 to and from D[15:8] or D[7:0]
6
AT43101
AT43101
Memory Access Functions
Mode Standby Byte Read, Even Byte Read, Odd Word Read Odd byte only Read Byte Write, Even Byte Wrtite, Odd Word Write Odd byte only Write REG* X H or L H only H only H only H or L H only H only H only CE2* H H H L L H H L L CE1* H L L L H L L L H A0 X L H X X L H X X OE* X L L L L H H H H WE* X H H H H L L L L D[15:8] High Z High Z High Z D(Odd) D(Odd) X X D(Odd) D(Odd) D[7:0] High Z D(Even) D(Odd) D(Even) High Z D(Even) D(Odd) D(Even) X
The E2PROM includes address and data latches which are clocked at the leading edge of the effective write pulse that results from the gating of the PCMCIA control signals. The Tsu(CE), Tsu(REG), Tsu(WE) timing parameters shown in the AC Write Characteristics guarantee adequate pulse width for the latch clock signals. The actual write is trig-
gered by the rising edge of the first of WE* or CE1* to go high. Writes to the E2PROM Attribute Memory must observe either a 10 ms. write recovery/cycle time or wait until R/B* goes inactive before another write can be initiated.
7
Block Diagram for Mode A Operation
ID[15:0]
ENB
D[15:0]
ENB
M U X
WPATT
Write Protect
DATAOUT DATAIN
256 X 8 EEPROM
CE OE WE
Reset R/B*
Ready/Busy* ADDR
IR/B* IA[8:1] IR*
A[8:1]
WE* CE1* CE2* REG* OE* A0 CONTROL LOGIC
Absolute Maximum Ratings*
Operating Temperature ........................0C to +70C Storage Temperature ..................... -65C to +150C Voltage on Any Pin With Respect to VSS .................-0.6 V to Vcc +0.6 V Maximum Operating Voltage ............................ 6.1 V
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stess rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
8
AT43101
AT43101
Pin Capacitance (F = 1 MHz, T = 25C) (1)
Max Cin Cout 12 12 Units pf pf Conditions Vin = 0 V Vout = 0 V
Note: 1. These parameters are characterized and not 100% tested.
DC and AC Operating Range
AT43101 Operating Temperature (Case) VCC Power Supply 0C to 70C 4.5 V to 5.5 V
DC Characteristics
Symbol ILI ILO ILIP ISB ICCA ICCP VIL VIH VOL VOH Parameter Input Load Current Output Leakage Current Input Load Current Standby Current Operating Current E2PROM Write Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 4 mA VCC = 4.5 V IOH = -4 mA, VCC = 4.5 V 2.4 .7VCC 0.45 Condition Vin = 0 V to VCC Vin = 0 V to VCC Inputs with pullups/downs VCC=5.5 V Inputs=0 or VCC I out=0mA VCC =5.5 V Inputs=0 or VCC, I out=0mA VCC =5.5 V Inputs=0 or VCC, I out=0mA Min -10 -10 -150 Max 10 10 +150 200 5 5 0.3VCC Units A A A A mA mA V V V V
9
AC Read Characteristics
Symbol tia(A) tda(A) ten(CE) ten(OE) ten(REG) tdis(CE) tdis(OE) tdis(REG) tioel(A0) tioel(CE) tioel(OE) tioel(REG) tioeh(A0) tioeh(CE) tioeh(OE) tioeh(REG) tv(A) td(ID) tice(A) tice(REG) tice(CE) Ten (reset) Tdis (reset)
Notes:
Parameter Delay to IA[24:0], from A[24:0] Data access time, from A[8:0] to D[7:0] Output enable time from CE* Output enable time from OE* Output enable time from REG* Output disable time from CE* Output disable time from OE* Output disable time from REG* Delay to IOEL*, IOEH* assertion from A0 Delay to IOEL*, IOEH* assertion from CE* Delay to IOEL*, IOEH* assertion from OE* Delay to IOEL*, IOEH* assertion from REG* Delay to IOEL*, IOEH* de-assertion from A0 Delay to IOEL*, IOEH* de-assertion from CE* Delay to IOEL*, IOEH* de-assertion from OE* Delay to IOEL*, IOEH* de-assertion from REG* Delay to data change, from change of address Delay from ID[15:0] to D[15:0] Delay to ICE[7:0]* from DEC[2:0], SEL[1:0], SGL/DBL* Delay to ICE[7:0]* from REG* Delay to ICE[7:0]* from CE1*, CE2* Chip active enable time from reset Chip active disable time from reset
Min 0 ns 5 ns 5 ns
Max 30 ns 250 ns 36 ns 36 ns 36 ns 58 ns 58 ns 58 ns 28 ns 28 ns 25 ns 28 ns 28 ns 28 ns 25 ns 28 ns
Notes
3 1 2 1
1 2 1 2
0 ns 27 ns 38 ns 38 ns 30 ns 50 ns 50 ns 4 4 4 5 5
1. Either or both of CE1*, CE2* assert according to function truth table. 2. REG* asserted only for Attribute Memory read. 3. tda(A) applies to Attribute Memory read. Access time for Common Memory read is derived from tia(A), td(ID), and external device access time. 4. Symmetrical for assertion and de-assertion. Also applies to write cycles. 5. Not shown in timing diagram.
Input Test Waveforms and Measurement Level
VDD VDD/2 0V tR1t<5 ns, test load capacitance is 50pf AC MEASUREMENT LEVEL
10
AT43101
AT43101
AC Read Waveforms
A[24:0], SGL/DBL*, DEC[2:0], SEL[1:0] tia(A) IA[24:0] tice(A) ICE[7:0]* tice(REG) tice(CE) tda(A) REG* tdis(REG) ten(REG) CE1*, CE2* tdis(CE) ten(CE) OE* ten(OE) D[15:0] HIGH Z tdis(OE) DATA VALID tioel(CE) tioel(OE) tioel(REG) tioel(A0) IOEH*, IOEL* td(ID) ID[15:0] DATA VALID tioeh(OE) tioeh(REG) tioeh(CE) tioeh(AO) ADDRESS VALID tv(A)
11
AC Write Characteristics
Symbol tia(A) tid(D) tsu(A) th(A) tsu(D) th(D) tsu(CE) th(CE) twc twr tsu(REG) th(REG) tiwel(A0) tiwel(CE) tiwel(WE) tiwel(REG) tiweh(A0) tiweh(CE) tiweh(WE) tiweh(REG) twp(IWP) twe(IWP) tRB(WE) tRB(IRB)
Notes:
Parameter Delay to IA[24:0], from A[24:0] Delay to ID[15:0], from D[15:0] Setup time, A[24:0] valid before WE* assertion Hold time, A[24:0] after WE* de-assertion Setup time, D[15:0] valid before WE* de-assertion Hold time, D[15:0] after WE* de-assertion Setup time, CE*, CE* before WE* de-assertion Hold time, CE*, CE* after WE* de-assertion Write cycle time Minimum active pulse of WE*, CE1* Setup time, REG* to WE* Hold time, REG* after WE* de-assertion Delay to IWEL*, IWEH* assertion from A0 Delay to IWEL*, IWEH* assertion from CE* Delay to IWEL*, IWEH* assertion from WE* Delay to IWEL*, IWEH* assertion from REG* Delay to IWEL*, IWEH* de-assertion from A0 Delay to IWEL*, IWEH* de-assertion from CE* Delay to IWEL*, IWEH* de-assertion from WE* Delay to IWEL*, IWEH* de-assertion from REG* Delay to WP, from IWP* Delay to IWEH*, IWEL* from IWP* Delay to R/B* from start of Delay to R/B* from IR/B* E2PROM write
Min 0 0 26 ns 11 ns 10 ns 10 ns 190 ns 0
Max 30 ns 31 ns
Note
1 1 1 1 2 2 10 ms 1 1
190 ns 190 ns 0 0 0 0 0 0 0 0 0 0 0 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns 25 ns 50 ns 40 ns
4 4 4 4 2 3 5 5 1
1. Parameter applies to writes of internal E2PROM. 2. Either or both of CE1*, CE2* assert according to function truth table. 3. REG* asserted only for Attribute Memory write. REG* must be stable during the write at the level appropriate to the memory type being accessed. 4. One or both of IWEH*, IWEL* assert per A0, CE1*, CE2*, provided REG* is high. 5. Not shown in timing diagrams.
12
AT43101
AT43101
A. C. Write Waveforms - WE* Control
A[24:0] tia(A) IA[24:0] ADDRESS VALID th(A) tiweh(A0)
D[15:0]
DATA VALID tsu(D) tid(D) th(D)
ID[15:0] tsu(A) WE* tiweh(WE) tsu(CE) CE1*, CE2* tsu(REG) REG* tiwel(CE) tiwel(REG) tiwel(A0) IWEH*, IWEL* tiweh(REG) th(REG) th(CE) tiweh(CE) twr tiwel(WE)
Ready/Busy* Waveforms
WE*1
tRB(WE)
R/B*
twc 1) CE* or WE* dependant on controlling signal
IR/B*
R/B*
tRB(IRB)
13
AC Write Waveforms - CE Control
A[24:0] tia(A) IA[24:0] ADDRESS VALID th(A) tiweh(A0)
D[15:0]
DATA VALID tsu(D) tid(D) th(D)
ID[15:0] tsu(A) CE1*, CE2* tiwel(WE) tsu(CE) WE* tsu(REG) REG* tiwel(CE) tiwel(REG) tiwel(A0) IWEH*, IWEL* tiweh(REG) th(REG) th(CE) twr
tiweh(WE)
tiweh(CE)
Packaging and Ordering Information
Package Type TQFP Pin Count, Dimensions 64 pins, 1 mm thick Part Number AT43101
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AT43101

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