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| A/D, D/C Converters for Image Signal Processing MN65702H Low Power 8-Bit, 3-Channel CMOS D/A Converter for Image Processing Overview The MN65702H is a high-speed 8-bit, 3-channel CMOS digital-to-analog converter. (Two channels use serial input.) It uses both a matrix cell and weighted current technology to achieve both low power consumption and high speed. It features built-in output resistor, reference resistor, and low pass filter, and provides independent output amplitude adjustment for the Y (luminance) and C (chroma) synchronization signals. The Y (luminance signal) can be superimposed with an external SYNC signal. Pin Assignment Features Maximum conversion rate: 20 MSPS (min.) Linearity error: 0.2 LSB (typ.) Differential linearity error: 0.2 LSB (typ.) Power supply voltage: VDD= 3.3 0.3 V, VCC= 4.8 0.3 V Full scale current: 2.33 mA (typ.) Power consumption: 100 mW (typ.) (fCLK=15 MHz) Built-in LPF and synchronization function. Applications Digital television Digital video equipment Digital image processing equipment DY4 DY3 DY2 DY1 SYNC VCC DVSS N.C. N.C. AVDD COMPS N.C. 1 2 3 4 5 6 7 8 9 10 11 12 N.C. DC3 DC2 DC1 UVSEL DVDD DVSS CLK DY8 DY7 DY6 DY5 37 38 39 40 41 42 43 44 45 46 47 48 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 DC4 DC5 DC6 DC7 DC8 DVSS DVDD N.C. AVSS VREFC N.C. COMPC N.C. VOUT VCC UOUT AVSS VCC YOUT AVSS VREFY N.C. COMPY VREFS (TOP VIEW) QFH048-P-0707 1 2 DC8 DC7 SYNC 5 CLK 44 MN65702H Block Diagram UVSEL DY7 46 45 DY8 4 DY1 DY2 3 2 DY3 DY4 1 DY5 48 DY6 47 DC4 36 DC5 35 DC6 34 40 DC1 DC2 39 DC3 38 32 33 41 VCC + - 11 6 Latch Latch Latch Latch 13 V REFS DVDD 30 COMPS DVDD Latch Latch Latch 42 DVSS 7 Current Source DVSS 31 DVSS 43 27 Decoder Latch Latch Decoder Latch + - 14 16 VREFY VREFC Decoder Latch + - COMPC 25 COMPY AVCC Current cell 10 Current cell Current cell Current Source Current Source VCC 19 Current cell VCC 22 AVSS Low pass filter 17 Low pass filter AVSS 23 21 20 Low pass filter N.C. AVSS VOUT UOUT 28 18 YOUT A/D, D/C Converters for Image Signal Processing 12 37 29 26 24 15 9 8 A/D, D/C Converters for Image Signal Processing Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Symbol DY4 DY3 DY2 DY1 SYNC VCC DVSS N.C. N.C. AVDD COMPS N.C. VREFS COMPY N.C. VREFY AVSS YOUT VCC AVSS UOUT VCC VOUT N.C. COMPC N.C. VREFC AVSS N.C. DVDD DVSS DC8 DC7 DC6 DC5 DC4 N.C. DC3 DC2 DC1 UVSEL DVDD Function Description Y (luminance) digital input Y (luminance) digital input Y (luminance) digital input Y (luminance) digital input (MSB) SYNC signal judgment signal Filter power supply for analog circuits Ground for digital circuits No connection No connection Power supply for analog circuits Phase compensation No connection SYNC reference voltage input Phase compensation No connection Luminance reference voltage input Ground for analog circuits Y signal analog current output Filter power supply for analog circuits Ground for analog circuits U signal analog current output Filter power supply for analog circuits V signal analog current output No connection Phase compensation No connection Chroma reference voltage input Ground for analog circuits No connection Power supply voltage for digital circuits Ground for digital circuits C (chroma) digital input (LSB) C (chroma) digital input C (chroma) digital input C (chroma) digital input C (chroma) digital input No connection C (chroma) digital input C (chroma) digital input C (chroma) digital input (MSB) U/V signal discrimination for C (chroma) signal Power supply voltage for digital circuits MN65702H 3 MN65702H Pin Descriptions (continued) Pin No. 43 44 45 46 47 48 Symbol DVSS CLK DY8 DY7 DY6 DY5 A/D, D/C Converters for Image Signal Processing Function Description Power supply for digital circuits Sampling clock Y (luminance) digital input (LSB) Y (luminance) digital input Y (luminance) digital input Y (luminance) digital input Ta=25C Absolute Maximum Ratings Parameter Power supply voltage Power supply voltage for analog circuits Input voltage Output voltage Operating ambient temperature Storage temperature Symbol DVDD/AVDD VCC VI VO Topr Tstg Rating - 0.3 to +7.0 - 0.3 to +7.0 - 0.3 to DVDD +0.3 - 0.3 to AVDD +0.3 -20 to +70 -55 to +125 Unit V V V V C C Recommended Operating Conditions Parameter Power supply voltage Reference voltage External compensation capacitor Digital input voltage Clock "H" level "L" level "H" level pulse width "L" level pulse width VDD=AVDD=DVDD=3.3V, VCC=4.8V, VSS=AVSS=DVSS=0V, Ta=25C Symbol VCC VDD VREFS/Y/C CCOMPS, Y, C VIH VIL tWH tWL min 4.5 3.0 -- 0.33 2.4 VSS 20 20 typ 4.8 3.3 2.15/1.96/1.93 1.0 -- -- -- -- max 5.1 3.6 -- 3.3 VDD 0.8 -- -- Unit V V V F V V ns ns Electrical Characteristics Parameter Power supply voltage Resolution Linearity error Differential linearity error Full scale current Setup time Hold time Settling time Maximum conversion speed Analog output delay time DVDD=AVDD=3.0V, VCC=4.8V, DVSS=AVSS=0V, Ta=25C Symbol Conditions IDD/ICC fCLK=15MHz, Output amplitude = 0.7 V, RES EL ED IFS tS tH tST FC(max.) tdY/tdc VDD=3.3V, VCC=4.8V Y*C output amplitude =0.7VP-P f=100kHz VDD=3.3V, VCC=4.8V Y (luminance) output amplitude =0.7Vp-p C (chroma) output amplitude =0.7Vp-p min -- -- -- -- -- 15 5 -- 20 -- typ 12/12 8 0.2 0.2 2.33 -- -- 30 -- 90/140 max 21/21 -- 0.5 0.5 -- -- -- 50 -- -- Unit mA bit LSB LSB mA ns ns ns MSPS ns 4 A/D, D/C Converters for Image Signal Processing Filter Characteristics Parameter Y filter I/O gain Y filter f characteristic (fck/2) Y filter f characteristic (3MHz) Y filter group delay UV filter I/O gain UV filter f characteristic (fck/4) UV filter f characteristic (1MHz) UV filter group delay DVDD=AVDD=3.0V, VCC=4.8V, DVSS=AVSS=0V, Ta=25C MN65702H Symbol GYF FYFCK FYFCL DYF GCF FCFCK FCFCL DCF Conditions f=100kHz f=100kHz 6.35MHz f=100kHz 3.0MHz f=100kHz f=100kHz f=100kHz 3.18MHz f=100kHz 1.0MHz f=100kHz min -1.2 -10 -3 60 -1.2 -15 -3 100 typ - 0.2 -7 -1 80 - 0.2 -10 -1 130 max 0.8 -4 1.0 100 0.8 -6 1.0 160 Unit dB dB dB dB dB dB dB ns Timing Chart M SELECT = "H," Y and U(C), 3-channel output SYNC CLK DY1 to DY8 Y-1 Y0 Y1 Y2 Y3 Y4 Y5 DC1 to DC8 Y-2 U0 V0 U2 V2 U4 V4 UVSEL Two clock cycles YOUT Y-2 Y-1 Y0 Y1 Y3 tds UOUT U-4 U-2 U0 U2 tds VOUT V-4 V-2 Two clock cycles td tst V0 V2 tds: SYNC delay time td: Analog output delay time tst: Settling time 5 MN65702H Package Dimensions (Unit:mm) QFH048-P-0707 A/D, D/C Converters for Image Signal Processing 9.00.2 7.00.2 36 25 (0.75) 7.00.2 37 24 48 13 1 (0.75) 0.5 12 0.20.1 (1.0) 2.9 max. 2.50.2 +0.10 -0.05 9.00.2 0.15 0.10.1 0.1 SEATING PLANE 0.50.2 0 to 10 6 |
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