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PHB/PHD101NQ03LT
TrenchMOSTM logic level FET
Rev. 02 -- 25 February 2003 Product data
1. Description
N-channel logic level field-effect power transistor in a plastic package using TrenchMOSTM technology. Product availability: PHB101NQ03LT in SOT404 (D2-PAK) PHD101NQ03LT in SOT428 (D-PAK).
2. Features
s Low gate charge s Low on-state resistance.
3. Applications
s Optimized as a control FET in DC to DC convertors
4. Pinning information
Table 1: Pinning - SOT404, SOT428 simplified outline and symbol Simplified outline
mb mb
Pin Description 1 2 3 mb gate (g)
Symbol
d
drain (d) source (s) mounting base, connected to drain (d)
[1]
g s
MBB076
2 2 1 3
MBK116
1 Top view
3
MBK091
SOT404 (D2-PAK)
[1]
SOT428 (D-PAK)
It is not possible to make connection to pin 2 of the SOT404 and SOT428 packages.
Philips Semiconductors
PHB/PHD101NQ03LT
TrenchMOSTM logic level FET
5. Quick reference data
Table 2: VDS ID Ptot Tj RDSon Quick reference data Conditions 25 Tj 175 C Tmb = 25 C; VGS = 5 V Tmb = 25 C Tj = 25 C; VGS = 10 V; ID = 25 A Tj = 25 C; VGS = 5 V; ID = 25 A Typ 4.5 5.8 Max 30 75 166 175 5.5 7.0 Unit V A W C m m drain-source voltage (DC) drain current (DC) total power dissipation junction temperature drain-source on-state resistance Symbol Parameter
6. Limiting values
Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS VGSM ID IDM Ptot Tstg Tj IS ISM drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage (DC) gate-source voltage drain current (DC) peak drain current total power dissipation storage temperature junction temperature source (diode forward) current (DC) Tmb = 25 C peak source (diode forward) current Tmb = 25 C; pulsed; tp 10 s unclamped inductive load; ID = 43 A; tp = 0.19 ms; VDD 15 V; RGS = 50 ; VGS = 10 V; starting Tj = 25 C tp 50 s; pulsed; duty cycle 25%; Tj 150 C Tmb = 25 C; VGS = 5 V; Figure 2 and 3 Tmb = 100 C; VGS = 5 V; Figure 2 Tmb = 25 C; pulsed; tp 10 s; Figure 3 Tmb = 25 C; Figure 1 Conditions 25 Tj 175 C 25 Tj 175 C; RGS = 20 k Min -55 -55 Max 30 30 20 25 75 75 240 166 +175 +175 75 240 185 Unit V V V V A A A W C C A A mJ
Source-drain diode
Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy
9397 750 10929
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 -- 25 February 2003
2 of 13
Philips Semiconductors
PHB/PHD101NQ03LT
TrenchMOSTM logic level FET
120 Pder (%) 80
03aa16
120 Ider (%) 80
03ai19
40
40
0 0 50 100 150 200 Tmb (C)
0 0 50 100 150 200 Tmb (C)
P tot P der = ---------------------- x 100% P
tot ( 25 C )
ID I der = ------------------ x 100% I
D ( 25 C )
Fig 1. Normalized total power dissipation as a function of mounting base temperature.
Fig 2. Normalized continuous drain current as a function of mounting base temperature.
103 ID (A)
03ai21
Limit RDSon = VDS / ID tp = 10 s 100 s
102
DC 10
1 ms
10 ms
1 1 10 VDS (V) 102
Tmb = 25 C; IDM is single pulse; VGS = 10V.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 10929
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 -- 25 February 2003
3 of 13
Philips Semiconductors
PHB/PHD101NQ03LT
TrenchMOSTM logic level FET
7. Thermal characteristics
Table 4: Rth(j-mb) Rth(j-a) Thermal characteristics Conditions Min Typ Max Unit 75 0.9 K/W K/W thermal resistance from junction to mounting base Figure 4 thermal resistance from junction to ambient SOT428 mounted on a PCB; SOT428 minimum footprint; vertical in still air mounted on a PCB; SOT404 minimum footprint; vertical in still air Symbol Parameter
SOT404 and SOT428
-
50
-
K/W
7.1 Transient thermal impedance
10 Zth(j-mb) (K/W) 1 = 0.5 0.2 10-1 0.1 0.05 0.02 P 10-2 single pulse tp T 10-3 10-5 10-4 10-3 10-2 10-1
03ai20
=
tp T
t
tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 10929
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 -- 25 February 2003
4 of 13
Philips Semiconductors
PHB/PHD101NQ03LT
TrenchMOSTM logic level FET
8. Characteristics
Table 5: Characteristics Tj = 25 C unless otherwise specified Symbol Parameter Static characteristics V(BR)DSS drain-source breakdown voltage ID = 0.25 mA; VGS = 0 V Tj = 25 C Tj = -55 C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 9 Tj = 25 C Tj = 175 C Tj = -55 C IDSS drain-source leakage current VDS = 30 V; VGS = 0 V Tj = 25 C Tj = 175 C IGSS RDSon gate-source leakage current drain-source on-state resistance VGS = 20 V; VDS = 0 V VGS = 5 V; ID = 25 A; Figure 7 and 8 Tj = 25 C Tj = 175 C VGS = 10 V; ID = 25 A; Figure 7 Tj = 25 C Dynamic characteristics Qg(tot) Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf VSD trr Qr total gate charge gate-source charge gate-drain (Miller) charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12 reverse recovery time recovered charge IS = 10 A; dIS/dt = -100 A/s; VGS = 0 V VDD = 15 V; ID = 25 A; VGS = 4.5 V; RG = 5.6 ; resistive load VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 11 ID = 50 A; VDD = 15 V; VGS = 5 V; Figure 13 23 10.5 8 600 225 23 90 37 33 0.85 37 33 1.2 nC nC nC pF pF pF ns ns ns ns V ns nC 4.5 5.5 m 5.8 10.5 7 12.6 m m 0.05 10 1 500 100 A A nA 1 0.6 1.9 2.5 2.9 V V V 30 27 V V Conditions Min Typ Max Unit
2180 -
Source-drain diode
9397 750 10929
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 -- 25 February 2003
5 of 13
Philips Semiconductors
PHB/PHD101NQ03LT
TrenchMOSTM logic level FET
80 ID (A) 60 Tj = 25 C 10 V 5 V 4.5 V 4V
03ai22
80 ID (A) 60 VDS > ID x RDSon
03ai24
3.8 V
3.6 V 40
3.4 V
40
3.2 V 20 3V VGS = 2.8 V 0 0 0.2 0.4 0.6 0.8 1 VDS (V) 0 0 1 2 3V 4 GS (V) 20 175 C Tj = 25 C
Tj = 25 C
Tj = 25 C and 175 C; VDS > ID x RDSon
Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values.
Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values.
16 RDSon (m) 12 Tj = 25 C
03ai23
2 a 1.5
03af18
VGS = 3.8 V
4V 8 1
4.5 V 5V 10 V
4
0.5
0 0 20 40 60 ID (A) 80
0 -60 0 60 120 Tj (C) 180
Tj = 25 C
R DSon a = --------------------------R DSon ( 25 C )
Fig 7. Drain-source on-state resistance as a function of drain current; typical values.
Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature.
9397 750 10929
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 -- 25 February 2003
6 of 13
Philips Semiconductors
PHB/PHD101NQ03LT
TrenchMOSTM logic level FET
3.2 VGS(th) (V) max 2.4 typ 1.6
03ai29
10-1 ID (A) 10-2
03ai28
10-3
min
typ
max
10-4 min 0.8 10-5
0 -60 0 60 120 Tj (C) 180
10-6 0 0.8 1.6 2.4 VGS(V) 3.2
ID = 1 mA; VDS = VGS
Tj = 25 C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of junction temperature.
Fig 10. Sub-threshold drain current as a function of gate-source voltage.
104
03ai26
C (pF) Ciss
103 Coss
Crss
102 10-1
1
10
2 VDS (V) 10
VGS = 0 V; f = 1 MHz
Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values.
9397 750 10929
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 -- 25 February 2003
7 of 13
Philips Semiconductors
PHB/PHD101NQ03LT
TrenchMOSTM logic level FET
80 IS (A) 60 VGS = 0 V
03ai25
10 VGS (V) 8 ID = 50 A Tj = 25 C VDD = 15 V 6
03ai27
40 4 20 175 C Tj = 25 C 2
0 0 0.3 0.6 0.9 V 1.2 SD (V)
0 0 10 20 30 40 50 QG (nC)
Tj = 25 C and 175 C; VGS = 0 V
ID = 50 A; VDD = 15 V
Fig 12. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values.
Fig 13. Gate-source voltage as a function of gate charge; typical values.
9397 750 10929
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 -- 25 February 2003
8 of 13
Philips Semiconductors
PHB/PHD101NQ03LT
TrenchMOSTM logic level FET
9. Package outline
Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped) SOT404
A E A1 mounting base
D1
D
HD
2
Lp
1
3
b c Q
e
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 4.50 4.10 A1 1.40 1.27 b 0.85 0.60 c 0.64 0.46 D max. 11 D1 1.60 1.20 E 10.30 9.70 e 2.54 Lp 2.90 2.10 HD 15.80 14.80 Q 2.60 2.20
OUTLINE VERSION SOT404
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 99-06-25 01-02-12
Fig 14. SOT404 (D2-PAK)
9397 750 10929 (c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 -- 25 February 2003
9 of 13
Philips Semiconductors
PHB/PHD101NQ03LT
TrenchMOSTM logic level FET
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads (one lead cropped)
SOT428
seating plane y A E b2 A A1 mounting base A2 E1
D1 D HE L2
2
L L1
1
b1 e e1 b
3
wM A c
0
10 scale
20 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 2.38 2.22 A1(1) 0.65 0.45 A2 0.93 0.73 b 0.89 0.71 b1 1.1 0.9 b2 5.46 5.26 c 0.4 0.2 D 6.22 5.98 D1 min. 4.0 E 6.73 6.47 E1 e e1 HE 10.4 9.6 L 2.95 2.55 L1 min. 0.5 L2 0.9 0.5 w 0.2 y max. 0.2
4.81 2.285 4.57 4.45
Note 1. Measured from heatsink back to lead. OUTLINE VERSION SOT428 REFERENCES IEC JEDEC TO-252 JEITA SC-63 EUROPEAN PROJECTION ISSUE DATE 99-09-13 01-12-11
Fig 15. SOT428 (D-PAK).
9397 750 10929 (c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 -- 25 February 2003
10 of 13
Philips Semiconductors
PHB/PHD101NQ03LT
TrenchMOSTM logic level FET
10. Revision history
Table 6: 02 Revision history CPCN Description Product data (9397 750 10929) Modifications:
Rev Date 20030225
* * *
01 20020220 -
Removal of PHP101NQ03LT (Now in separate data sheet). Section 7 "Thermal characteristics" Clarification of thermal resistance table. Graphics updated to latest standard.
Product data (9397 750 09307); initial version
9397 750 10929
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 -- 25 February 2003
11 of 13
Philips Semiconductors
PHB/PHD101NQ03LT
TrenchMOSTM logic level FET
11. Data sheet status
Level I II Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
12. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
13. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
14. Trademarks
TrenchMOS -- is a trademark of Koninklijke Philips Electronics N.V.
Contact information
For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
9397 750 10929
Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 -- 25 February 2003
12 of 13
Philips Semiconductors
PHB/PHD101NQ03LT
TrenchMOSTM logic level FET
Contents
1 2 3 4 5 6 7 7.1 8 9 10 11 12 13 14 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Transient thermal impedance . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
(c) Koninklijke Philips Electronics N.V. 2003. Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 25 February 2003 Document order number: 9397 750 10929

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