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tm
TE CH
T2316162A
DRAM
FEATURES
* Industry-standard x 16 pinouts and timing functions. * Single 5V (10%) power supply. * All device pins are TTL- compatible. * 1K-cycle refresh in 16ms. * Refresh modes: RAS only, CAS BEFORE RAS (CBR) and HIDDEN. * Extended data-out (EDO) PAGE MODE access cycle. * BYTE WRITE and BYTE READ access cycles.
1024K x 16 DYNAMIC RAM
EDO PAGE MODE GENERAL DESCRIPTION
The T2316162A is a randomly accessed solid state memory containing 16,777,216 bits organized in a x16 configuration. The T2316162A has both BYTE WRITE and WORD WRITE access cycles via two CAS pins. It offers Fast Page mode with Extended Data Output. The T2316162A CAS function and timing are determined by the first CAS to transition low and by the last to transition back high. Use only one of the two CAS and leave the other staying high during WRITE will result in a BYTE WRITE. CASL transiting low in a WRITE cycle will write data into the lower byte (DQ0~DQ7), and CASH transiting low will write data into the upper byte (DQ8~DQ15).
OPTION
TIMING MARKING 45ns -45 50ns -50 60ns -60 PACKAGE 42-pin SOJ J 44/50-pin TSOPII S
PIN ASSIGNMENT ( Top View )
VDD 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 Vss DQ15 DQ14 DQ13 DQ12 Vss DQ11 DQ10 DQ9 DQ8 NC
VDD DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 NC NC WE RAS NC NC A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
Vss DQ15 DQ14 DQ13 DQ12 Vss DQ11 DQ10 DQ9 DQ8 NC CASL CASH OE A9 A8 A7 A6 A5 A4 Vss
DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 NC
NC NC WE RAS NC NC A0 A1 A2 A3 VDD
15 16 17 18 19 20 21 22 23 24 25
36 35 34 33 32 31 30 29 28 27 26
NC CASL CASH OE A9 A8 A7 A6 A5 A4 Vss
TM Technology Inc. reserves the right P. 1 to change products or specifications without notice.
Publication Date: APR. 2002 Revision:E
tm
TE CH
T2316162A
FUNCTIONAL BLOCK DIAGRAM
WE CASL CASH CONTROL LOGIC
CAS
DATA-IN BUFFER DQ0 16
. .
DQ15
NO.2 CLOCK GENERATOR DATA-OUT BUFFER 10 COLUMN DECODER
10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 10
COLUMN. ADDRESS BUFFER
OE
1 6
1024 REFRESH CONTROLLER 16 SENSE AMPLIFIERS I/O GATING 1024x 16
REFRESH COUNTER 10 ROW DECODER ROW. ADDRESS BUFFERS(10)
10
1024
1024x 1024 x 16 MEMORY ARRAY
RAS
NO.1 CLOCK GENERATOR
Vcc Vss
PIN DESCRIPTIONS
SYM. A0-A9 RAS CASH CASL WE OE DQ0 - DQ15 Vcc Vss NC TYPE Input Input Input Input Input Input Input/ Output Supply Ground Address Input Row Address Strobe Column Address Strobe /Upper Byte Control Column Address Strobe /Lower Byte Control Write Enable Output Enable Data Input/ Output Power, 5V Ground No Connect DESCRIPTION
TM Technology Inc. reserves the right P. 2 to change products or specifications without notice.
Publication Date: APR. 2002 Revision:E
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TE CH
T2316162A
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any pin Relative to VSS.... -1V to +7V Operating Temperature, Ta (ambient)..... .........0C to +70C Storage Temperature (plastic)...... -55C to +150C Power Dissipation ........................................ 1.2W Short Circuit Output Current........................ 50mA
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(0C Ta 70C; VCC = 5V 10 % unless otherwise noted) DESCRIPTION CONDITIONS Supply Voltage Supply Voltage Input High (Logic) voltage Input Low (Logic) voltage Input Leakage Current 0V VIN 7V 0V VOUT 7V Output Leakage Current Output(s) disabled Output High Voltage IOH = -5 mA Output Low Voltage IOL = 4.2 mA Note: 1.All Voltages referenced to Vss MAX DESCRIPTION Operating Current TTL Standby Current CONDITIONS RAS , CAS cycling , tRC = min TTL interface, RAS , CAS =VIH, DOUT=High-Z tRC = min tPC = min tRC = min SYM. -45 -50 -60 UNITS NOTES Icc1 190 180 170 mA 1,2 Icc2 Icc3 Icc4 Icc5 2 2 2 mA mA mA mA mA 1 2 1,3 SYM. Vcc Vss VIH VIL ILI ILO VOH VOL MIN 4.5 0 2.4 -1.0 -10 -10 2.4 0 MAX 5.5 0 Vcc+1 0.8 10 10 Vcc 0.4 UNITS V V V V uA uA V V NOTES 1 1 1
RAS -only refresh Current EDO Page Mode Current CAS Before RAS Refresh Current CMOS Standby Current
190 180 170 150 140 130 190 180 170 1.0 1.0 1.0
CMOS interface, RAS , CAS >Vcc- Icc6 0.2V
Note: 1. Icc depends on output load condition when the device is selected. Icc max is specified at the output open condition. 2. Address can be changed twice or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH.
TM Technology Inc. reserves the right P. 3 to change products or specifications without notice.
Publication Date: APR. 2002 Revision:E
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TE CH
T2316162A
CAPACITANCE
(Ta =25C, Vcc =5V 10 %) Parameter Input Capacitance (address) Input Capacitance (clocks) Output Capacitance (data-in, data-out) Symbol CI1 CI2 Typ Max 5 7 Unit pF pF Notes 1 1 1
CDQ 10 pF Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
AC ELECTRICAL CHARACTERISTICS (note 14)
(Ta =0 to 70C, Vcc=5V 10 %, Vss=0V) Test Conditions (note 29) AC CHARACTERISTICS PARAMETER Read or Write Cycle Time Read Write Cycle Time EDO-Page-Mode Read or Write Cycle Time EDO-Page-Mode Read-Write Cycle Time Access Time From RAS Access Time From CAS Access Time From OE Access Time From Column Address Access Time From CAS Precharge RAS Pulse Width RAS Pulse Width (EDO Page Mode) RAS Hold Time RAS Precharge Time CAS Pulse Width CAS Hold Time CAS Precharge Time (EDO Page Mode) RAS to CAS Delay Time CAS to RAS Precharge Time Row Address Setup Time Row Address Hold Time RAS to Column Address Delay Time Column Address Setup Time Column Address Hold Time Column Address Hold Time (Reference to RAS ) Column Address to RAS Lead Time -45 MIN MAX tRC 80 tRWC 105 tPC 16 tPCM 46 tRAC 45 tCAC 11 SYM tOAC tAA tACP tRAS tRSH tRP tCAS tCSH tCP tRCD tCRP tASR tRAH tRAD tASC tCAH tAR tRAL 45 11 28 6 40 5 10 5 0 5 8 0 6 35 19 34 10K tRASC 45 11 19 22 10K 100K 50 50 13 30 8 40 6 12 5 0 8 10 0 8 38 23 37 10K -50 MIN MAX 84 113 20 58 50 13 13 25 27 10K 100K 60 60 15 40 15 60 10 20 5 0 10 12 0 10 45 30 45 10K -60 UNIT Notes MIN MAX 110 ns 140 ns 25 ns 22 70 ns 22 60 ns 4 15 15 30 35 10K 100K ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 26 19 23 7,18 19 27 5,20 13,20 20
26
28
30
8 18 18
TM Technology Inc. reserves the right P. 4 to change products or specifications without notice.
Publication Date:APR. 2002 Revision:E
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TE CH
T2316162A
-45 -50 -60 UNIT Notes MIN MAX MIN MAX MIN MAX 0 0 0 ns 15,18 0 0 0 ns 9,15,19 0 3 3 15 8 0 6 35 6 9 8 0 6 35 61 35 27 2.5 10 10 10 6 5 3 2 0 6 4 3 7 50 16 0 8 38 8 9 8 0 8 38 64 39 27 2.5 10 10 10 10 5 5 5 0 10 5 3 10 50 16 0 3 3 15 8 0 10 45 15 10 10 0 10 45 85 55 40 2.5 10 10 10 15 5 10 10 0 10 5 3 15 50 16 0 3 3 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 20 10,17, 20 17,28 11,15,1 8 15,27 15 15 15 15,19 12,20 12,20 11 11 11,18
AC ELECTRICAL CHARACTERISTICS (continued)
AC CHARACTERISTICS PARAMETER Read Command Setup Time Read Command Hold Time Reference to CAS Read Command Hold Time Reference to RAS CAS to Output in Low-Z SYM tRCS tRCH tRRH tCLZ
Output Buffer Turn-off Delay From CAS or tOFF1 RAS tOFF2 Output Buffer Turn-off to OE Write Command Setup Time Write Command Hold Time Write Command Hold Time (Reference to RAS ) Write Command Pulse Width Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Setup Time Data-in Hold Time Data-in Hold Time (Reference to RAS ) RAS to WE Delay Time Column Address to WE Delay Time CAS to WE Delay Time Transition Time (rise or fall) Refresh Period (1024 cycles) RAS to CAS Precharge Time CAS Setup Time (CBR REFRESH) CAS Hold Time (CBR REFRESH) OE Hold Time From WE During ReadModify-Write Cycle OE Low to CAS High Setup Time OE High Hold Time From CAS High OE High Pulse Width OE Setup Prior to CAS During Hidden Refresh Cycle Last CAS Going Low to First CAS Returning High Data Output Hold After CAS Returning Low Output Disable Delay From WE tWCS tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tRWD tAWD tCWD tT tREF tRPC tCSR tCHR tOEH tOES tOEHC tOEP tORD tCLCH tCOH tWHZ
ns 2,3 ms ns ns ns ns ns ns ns ns ns ns ns 21 1,18 1,19 16
TM Technology Inc. reserves the right P. 5 to change products or specifications without notice.
Publication Date:APR. 2002 Revision:E
tm
TE CH
T2316162A
12. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 13. During a READ cycle, if OE is low then taken HIGH before CAS goes high, I/O goes open, if OE is tied permanently low, a LATE WRITE or READ-MODIFY-WRITE operation is not possible. 14. An initial pause of 100ms is required after power-up followed by eight RAS refresh cycles ( RAS only or CBR) before proper device operation is assured. The eight RAS cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 15. WRITE command is defined as WE going low. 16. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOFF2 and tOEH met ( OE high during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycles. 17. The I/Os open during READ cycles once tOFF1 or tOFF2 occur. 18. The first CAS edge to transition low. 19. The last CAS edge to transition high. 20. Output parameter (I/O) is referenced to corresponding CAS input, IO1~8 by CASL and IO9~16 by CASH . 21. Last falling CAS edge to first rising CAS edge. 22. Last rising CAS edge to next cycle's last rising CAS edge. 23. Last rising CAS edge to first falling CAS edge. 24. First IOs controlled by the first CAS to go low. 25. Last IOs controlled by the last CAS to go high. 26. Each CAS must meet minimum pulse width. 27. Last CAS to go low. 28. All IOs controlled, regardless CASL and CASH . 29. Data outputs are measured with a load of 50pF. The output reference levels are VOH/VOL =2.0V/0.8V; The input levels are VIH/VIL= 3.0V/0V.
Notes: 1. Enables on-chip refresh and address counters. 2. VIH(2.4V) and VIL(0.8V) are reference levels for measuring timing of input signals. Transition times are measured between VIH (2.4V) and VIL (0.8V). 3. In addition to meet the transition rate specification, all input signals must transit between VIH and VIL in a monotonic manner. 4. Assume that tRCD < tRCD(max). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 5. Assume that tRCD tRCD(max) . 6. If CAS is low at the falling edge of RAS , data-out will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS and RAS must be pulsed high. 7. Operation within the tRCD(max) limit ensures that tRAC(max) can be met. tRCD(max) is specified as a reference point only; if tRCD is greater than the specified tRCD(max) limit, access time is controlled by tCAC. 8. Operation within the tRAD limit ensures that tRAC(max) can be met. tRAD(max) is specified as a reference point only; if tRAD is greater than the specified tRAD(max) limit, access time is controlled by tAA. 9. Either tRCH or tRRH must be satisfied for a READ cycle. 10. tOFF1(max) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 11. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycles only. If tWCS tWCS(min), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tRWD tRWD(min), tAWD tAWD(min) and tCWD tCWD(min), the cycle is READ-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held high and WE taken low after CAS goes low result in a LATE WRITE( OE controlled) cycle.
TM Technology Inc. reserves the right P. 6 to change products or specifications without notice.
Publication Date:APR. 2002 Revision:E
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RAS V V CAS V V
TE CH
READ CYCLE
t t
T2316162A
RC RAS
t
RP
IH IL
t t t
CRP
CSH RSH
t t
CRP
t
t
RRH
RCD
CAS
IH IL
t t t
AR
t t
RAD RAH ASC
RAL CAH
ASR
t
t
V ADDR V V V
IH ROW IL
t
COLUM N
RCS
t
ROW
RCH
WE
IH IL
t t t t
AA
N O TE1
t
RAC CAC CLZ
V A IL D D A T A
O FF1
V I/O V
IO H IO L
OPEN
OPEN
t
OAC
t
O FF2
OE
V V
IH IL
EARLY WRITE CYCLE
t t RC RAS t RP
RAS
V V
IH IL
t t CRP t RCD t t CSH RSH CAS
CAS
V V
IH IL
t ASR t RAH t RAD
t
AR t t ASC t RAL CAH
ADDR
V V
IH IL
ROW
COLUM N
t t t t W CS t CW RW W W t W L L
ROW
CR CH P
WE
V V
IH IL
t t DS
DHR t DH
I/O
V V V V
IO H IO L
V A L ID
DATA
OE
IH IL
D O N 'T
CARE
U N D E F IN E D
Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last.
TM Technology Inc. reserves the right P. 7 to change products or specifications without notice.
Publication Date: APR. 2002 Revision:E
tm
TE CH
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES)
t
T2316162A
RW C RAS
t
t
RP
V IH RAS V IL
t
t t
CSH RSH CAS
t
CRP
t
RCD
t
CRP
CAS
V IH V IL
t t
t
AR
t t
RAD RAH ASC
RAL CAH
ASR
t
t
ADDR
V IH V IL
ROW
t
COLUM N
t
ROW
RW D CW D AW D
t t
CW L RW L
t
RCS
t t
WP
V IH WE V IL
t t t
AA
RAC CAC C LZ
V A IL D D V A IL D D
IN
t
DS
t
DH
t
I/O
V IO H V IO L
t
OUT
t
OAC
O FF2
t
OEH
OE
V IH V IL
EDO-PAGE-MODE READ CYCLE
t
RA SC
t
RP
RAS
V V
IH IL
t t
CSH
t
t
PC
t
t
t
RSH
CRP
t
CRP
t
RCD
CAS
t
CP
CAS
t
CP
t
CAS
CPN
V CAS V
IH IL
t t t
AR
t t
RAD A SC
t
RAL
A SR
t
RAH
CAH
t
A SC
t
CAH
t
A SC
t
CAH
ADDR
V V
IH IL
ROW
COLUM N
COLUM N
COLUM N
t
ROW
RRH
t
RCS
t
RCH
WE
V V
IH IL
t t t t
t
AA
t t t
t
AA
AA
t
RAC CAC COH
ACP
t
ACP CAC
NOTE1
CAC
t
CLZ
CLZ
V A IL D DATA
t
O FF1
O PEN
V I/O V V V
IO H
O PEN
IO L
V A IL D DATA
V A IL D DATA
t
t
OEHC
OAC
t t
t
OAC
t
t
O FF2
O FF2
OE
IH IL
OES
OES
t
OEP
D O N 'T C A R E
U N D E F IN E D
Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last. 2. tPC can be measured from falling edge of CAS to falling edge of CAS , or from rising edge of CAS to rising edge of RAS . Both measurements must meet the tPC specification. TM Technology Inc. reserves the right P. 8 to change products or specifications without notice. Publication Date: APR. 2002 Revision:E
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TE CH
EDO-PAGE-MODE EARLY-WRITE CYCLE
t RA SC
T2316162A
tR P
RAS
V IH V IL
tC S H tC R P tR C D tC A S ,tC LC H tP C tC P tC A S ,tC LC H tC P tR S H tC A S ,tC LC H tC P N
C A S L ,C A S H
V IH V IL
tA R tR A D tA S R tR A H tA S C tC A H tA S C tC A H tA S C tR A L tC A H
ADDR
V IH V IL
ROW
C O LU M N
tW C S tC W L tW C H tW P
C O LU M N tC W L tW C S tW C H tW P
C O LU M N tC W L tW C S tW C H tW P
ROW
WE
V IH V IL
tW C R tD H R tD H tR W L tD S tD H tD S tD H
tD S
I/O
V IO H V IO L V IH V IL
V A L ID D A T A
V A L ID D A T A
V A L ID D A T A
OE
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE CYCLES)
t RA SC tR P
R A S V IH V IL
tC S H tC R P tR C D tC A S , tC L C H tC P tP C M tC A S , tC L C H tC P tR S H tC A S , tC L C H tC P N
C A S L ,C A S H
V IH V IL
tA R tR A D tR A H tR A L tA S C tC A H tA S C tC A H tA S C tC A H
tA S R
A D D R V IH V IL
RO W
C O LU M N tR W D
tR C S tC W L tW P tA W D tC W D
C O LU M N
C O LU M N
RO W
tR W L tC W L tW P
tC W L tW P tA W D tC W D
tA W D tC W D
W E V IH V IL
tA A tR A C tC A C tC L Z tD H tD S tA A tA C P tC A C tC L Z
VALID D O UT VAL ID D IN VALID D O UT VAL ID D IN
tA A tD H tD S tA C P tC A C tC L Z
VAL ID D O UT VAL ID D IN
tD H tD S
I/O V IO H V IO L
O PEN
O PEN
tO F F 2 tO A C tO A C
tO F F 2 tO A C
tO F F 2 tO E H
OE
V IH V IL
DO N'T CARE UNDEF INED
Note: 1. tPC can be measured from falling edge to falling edge of CAS , or from rising edge to rising edge of CAS . Both measurements must meet the tPC specification. TM Technology Inc. reserves the right to change products or specifications without notice. P. 9 Publication Date: APR. 2002 Revision:E
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V R A S V IH IL
TE CH
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY-WRITE)
tR A S C
T2316162A
tR P
tC S H tC R P tR C D tP C tC A S tP C tC P tC A S tC P tR S H tC A S tC P
C A S V IH V IL
tA R tR A D tA S R tR A H tA S C tC A H tA S C tC A H tA S C tC A H RO W tR A L
A D D R V IH V IL
RO W
C O L U M N (A ) tR C S
C O L U M N (B ) tR C H
C O L U M N (N ) tW C S tW C H
W E V IH V IL
tA A tR A C tC A C tA C P
tA A tW H Z tC A C tC O H V A L ID D A T A (A ) tO A C V A L ID D A T A (B ) tD S tD H
V I/O V IO H IO L
O PEN
V A L ID D A T A IN
O E V IH V IL
RAS ONLY REFRESH CYCLE (ADDR=A0-A8 ; OE , WE =DON`T CARE)
tR C tR A S tR P
R A S V IH V IL
tC R P tR P C
C A S L ,C A S H
V IH V IL
tA S R tR A H RO W RO W
A D D R V IH V IL I/O V O H VOL
O PEN
DON'T CARE UNDEFINED
TM Technology Inc. reserves the right to change products or specifications without notice.
P. 10
Publication Date: APR. 2002 Revision:E
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RAS
TE CH
CBR REFRESH CYCLE (A0-A8 ; OE =DON`T CARE)
T2316162A
tR P
tR A S
tR P
tR A S
V IH V IL
tR P C tC P N tC S R tC H R tR P C tC S R tC H R
C A S H ,C A S L V IH V IL I/O W E V IH V IL
O PEN
HIDDEN REFRESH CYCLE ( WE =HIGH ; OE =LOW)
(R E A D ) tR A S (R E F R E S H ) tR A S
tR P
R A S V IH V IL
tC R P tR C D tR S H tC H R
C A S L ,C A S H
V IH V IL
tA R tR A D tA S R tR A H ROW tA S C tR A L tC A H
A D D R V IH V IL
C O LU M N tA A tR A C tC A C tC L Z N O TE1 tO F F 1
I/O
VOH VOL
O PEN tO A C
V A L ID D A T A tO F F 2
O PEN
O E V IH V IL
tO R D
DON'T CARE UNDEFINED
Note: 1. tOFF1 is referenced from the rising edge of RAS or CAS , whichever occurs last.
TM Technology Inc. reserves the right P. 11 to change products or specifications without notice.
Publication Date: APR. 2002 Revision:E
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TE CH
T2316162A
PACKAGE DIMENSIONS 42-LEAD SOJ DRAM (400 mil)
SYMBOL A A1 A2 B b c D E e E1 L y
DIMENSIONS IN INCHES 0.128~0.148 0.025(MIN) 0.105~0.115 0.026~0.032 0.015~0.020 0.007~0.013 1.070~1.080 0.395~0.405 0.050 0.435~0.445 0.082(MIN) 0.004(MAX)
DIMENSIONS IN MM 3.251~3.759 0.635(MIN) 2.657~2.920 0.660~0.813 0.381~0.508 0.178~0.330 27.178~27.432 10.033~10.287 1.270 11.049~11.303 2.083(MIN) 0.102(MAX)
TM Technology Inc. reserves the right P. 12 to change products or specifications without notice.
Publication Date: APR. 2002 Revision:E
tm
TE CH
T2316162A
PACKAGE DIMENSIONS 44/50L LEAD TSOPII DRAM (400 mil)
"A"
SYMBOL A A1 A2 b c D E e E1 L L1
DIMENSIONS IN INCHES 0.047 0.002~0.006 0.037~0.041 0.012~0.018 0.005~0.008 0.820~0.830 0.455~0.471 0.031 0.395~0.405 0.016~0.024 0.031 0~5
DIMENSIONS IN MM 1.200(MAX) 0.050~0.150 0.950~1.050 0.300~0.450 0.120~0.210 20.820~21.080 11.560~11.960 0.800 10.030~10.290 0.400~0.600 0.800 0~5
TM Technology Inc. reserves the right P. 13 to change products or specifications without notice.
Publication Date: APR. 2002 Revision:E

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