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DATA SHEET
MOS INTEGRATED CIRCUIT
PD178004, 178006, 178016, 178018
8-BIT SINGLE-CHIP MICROCONTROLLER
The PD178004, 178006, 178016 and 178018 are 8-bit single-chip CMOS microcontrollers that incorporate hardware for digital tuning systems. The CPU uses the 78K/0 architecture and high-speed access to internal memory and control of peripheral hardware are easy to implement. Also, the instructions used are the high-speed 78K/0 instructions, suitable for system control. The rich assortment of peripheral hardware includes an input/output port, 8-bit timer, A/D converter, serial interface, power-ON clear circuits, as well as a pre-scaler for digital tuning, a PLL frequency synthesizer and a frequency counter. The PD178P018, one-time PROM or EPROM versions which can be operated in the same supply voltage range as for the mask ROM versions, and various development tools, are also available. For more information on functions, refer to the following User's Manuals. Be sure to read them when designing.
PD178018 Subseries User's Manual: U11410E 78K/0 Series User's Manual Instruction: IEU-1372
FEATURES
* Internal high-capacity ROM and RAM
Items Product Name Program Memory ROM 32 Kbytes 48 Kbytes 2048 bytes 60 Kbytes Internal High-Speed RAM 1024 bytes Data Memory Buffer RAM 32 bytes Internal Expanded RAM Not provided
PD178004 PD178006 PD178016 PD178018
* Instruction Cycle: 0.44 s (4.5-MHz crystal oscillator used) * Large array of on-chip peripheral hardware General-purpose input/output port, A/D converter, serial interface, timer, frequency counter, power-ON clear circuits. * On-chip hardware for a PLL frequency synthesizer. Dual modulus pre-scaler, programmable divider, phase comparator, charge pump. * Vector Interrupts: 17 * Supply Voltage: VDD = 4.5 to 5.5 V (during PLL operation) VDD = 3.5 to 5.5 V (during CPU operation, when the system clock is fX/2 or lower) VDD = 4.5 to 5.5 V (during CPU operation, when the system clock is fX)
The information in this document is subject to change without notice. Document No. U11800EJ2V1DS00 (2nd Edition) Date Published March 1997 N Printed in Japan The mark
* shows major revised points.
(c)
1997
PD178004, 178006, 178016, 178018
APPLICATIONS Car stereo, home stereo systems. ORDERING INFORMATION Part Number Package 80-pin plastic QFP (14 x 14 mm, 0.65-mm pitch) 80-pin plastic QFP (14 x 14 mm, 0.65-mm pitch) 80-pin plastic QFP (14 x 14 mm, 0.65-mm pitch) 80-pin plastic QFP (14 x 14 mm, 0.65-mm pitch)
PD178004GC-xxx-3B9 PD178006GC-xxx-3B9 PD178016GC-xxx-3B9 PD178018GC-xxx-3B9
Remark
xxx denotes the ROM code number. Also, the ROM code number becomes Exx when the I2C bus is used.
PD178018 SUBSERIES EXPANSION
80 pins
PD178P018
PROM : 60 KB
RAM : 3 KB
80 pins
PD178018
ROM : 60 KB
RAM : 3 KB
PD178018 subseries
80 pins
PD178016
ROM : 48 KB
RAM : 3 KB
80 pins
PD178006
ROM : 48 KB
RAM : 1 KB
80 pins
PD178004
ROM : 32 KB
RAM : 1 KB
2
PD178004, 178006, 178016, 178018
OUTLINE OF FUNCTION
(1/2) Product name Item Internal memory ROM (ROM configuration) Internal high-speed RAM Buffer RAM Internal expansion RAM General-purpose register Instruction cycle Instruction set 32 Kbytes (mask ROM) 1024 bytes 32 bytes None 2048 bytes 48 Kbytes (mask ROM) 60 Kbytes (mask ROM)
PD178004
PD178006
PD178016
PD178018
8 bits x 32 registers (8 bits x 8 registers x 4 banks) With variable instruction execution time function 0.44 s/0.88 s/1.78 s/3.56 s/7.11 s/14.22 s (with 4.5-MHz crystal resonator) * * * * 16-bit operation Multiplication/division (8 bits x 8 bits, 16 bits / 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. : 62 pins : 1 pin : 54 pins : 4 pins : 3 pins
I/O port
Total CMOS input CMOS I/O N-ch open-drain I/O N-ch open-drain output
A/D converter Serial interface
8-bit resolution x 6 channels * 3-wire/SBI/2-wire/I2C busNote mode selectable : 1 channel * 3-wire serial I/O mode (with automatic transfer/receive function of up to 32 byte) : 1 channel * * * * Basic timer (timer carry FF (10 Hz)) : 8-bit timer/event counter : 8-bit timer (D/A converter: PWM output) : Watchdog timer : 1 2 1 1 channel channels channel channel
Timer
Buzzer (BEEP) output Vectored interrupt Maskable interrupt Non-maskable interrupt Software interrupt Test input PLL frequency synthesizer Division mode
1.5 kHz, 3 kHz, 6 kHz Internal: 8, external: 7 Internal: 1 Internal: 1 Internal: 1 Two types * Direct division mode (VCOL pin) * Pulse swallow mode (VCOH and VCOL pins) 12 types selectable by program (1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 25, 50 kHz) Error out output: 2 Unlock detectable by program * Frequency measurement * AMIFC pin: for 450-kHz count * FMIFC pin: for 450-kHz/10.7-MHz count
Reference frequency Charge pump Phase comparator Frequency counter
D/A converter (PWM output)
8-/9-bit resolution x 3 channels (shared by 8-bit timer)
Note
When using the I2C bus mode (including when this mode is implemented by program without using the peripheral hardware), consult your local NEC sales representative when you place an order for mask.
3
PD178004, 178006, 178016, 178018
(2/2) Product name Item Standby function * HALT mode * STOP mode * Reset by RESET pin * Internal reset by watchdog timer * Reset by power-ON clear circuit (3-value detection) * Detection of less than 4.5 VNote (CPU clock: fX) * Detection of less than 3.5 VNote (CPU clock: fX/2 or less and on power application) * Detection of less than 2.5 VNote (in STOP mode) * VDD = 4.5 to 5.5 V (with PLL operating) * VDD = 3.5 to 5.5 V (with CPU operating, CPU clock: fX/2 or less) * VDD = 4.5 to 5.5 V (with CPU operating, CPU clock: fX) * 80-pin plastic QFP (14 x 14 mm, 0.65-mm pitch)
PD178004
PD178006
PD178016
PD178018
Reset
Power supply voltage
Package
Note
These voltage values are maximum values. The reset is actually executed at a voltage lower than these values.
4
PD178004, 178006, 178016, 178018
TABLE OF CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ................................................................................................ 6 2. BLOCK DIAGRAM ........................................................................................................................... 8 3. PIN FUNCTION LIST ........................................................................................................................ 9 3.1 PORT PINS ................................................................................................................................ 9 3.2 PINS OTHER THAN PORT PINS ............................................................................................ 10 3.3 INPUT/OUTPUT CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS ..... 11 4. MEMORY SPACE ........................................................................................................................... 14 5. PERIPHERAL HARDWARE FUNCTION FEATURES ................................................................... 15 5.1 PORTS ..................................................................................................................................... 15 5.2 CLOCK GENERATOR ............................................................................................................. 16 5.3 TIMER ...................................................................................................................................... 16 5.4 BUZZER OUTPUT CONTROL CIRCUIT ................................................................................. 18 5.5 A/D CONVERTER .................................................................................................................... 19 5.6 SERIAL INTERFACES ............................................................................................................ 19 5.7 PLL FREQUENCY SYNTHESIZER ......................................................................................... 21 5.8 FREQUENCY COUNTER ........................................................................................................ 22 6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS ..................................................................... 23 6.1 INTERRUPT FUNCTIONS ....................................................................................................... 23 6.2 TEST FUNCTIONS .................................................................................................................. 26 7. STANDBY FUNCTION ................................................................................................................... 27 8. RESET FUNCTION ......................................................................................................................... 27 9. INSTRUCTION SET ........................................................................................................................ 28 10. ELECTRICAL SPECIFICATIONS................................................................................................... 30 11. PACKAGE DRAWINGS ................................................................................................................. 46 12. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 47 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................. 48 APPENDIX B. RELATED DOCUMENTS ............................................................................................ 50
5
PD178004, 178006, 178016, 178018
1. PIN CONFIGURATION (TOP VIEW)
* 80-PIN PLASTIC QFP (14 x 14 mm, 0.65 mm pitch)
PD178004GC-xxx-3B9, 178006GC-xxx-3B9 PD178016GC-xxx-3B9, 178018GC-xxx-3B9
P10/ANI0 P11/ANI1 P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P132/PWM0 P133/PWM1 P134/PWM2 P40 P41 P42
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 1 59 2 58 3 57 4 56 5 55 6 54 7 53 8 52 9 51 10 50 11 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
RESET VDD REGOSC X1 X2 GND REGCPU P06/INTP6 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0 P125 P124 P123 P122 P121 P120
P37 P36/BEEP P35 P34/TI2 P33/TI1 P32 P31 P30 P67 P66 P65 P64 P63 P62 P61 P60 P57 P56 P55 P54
Cautions 1. Connect the Internally Connected (IC) pin to GND directly. 2. Connect VDDPORT and VDDPLL pins to VDD. 3. Connect the GNDPORT and GNDPLL pins to GND. 4. Connect each of the REGOSC and REGCPU pins to GND via a 0.1-F capacitor.
6
GNDPORT VDDPORT P43 P44 P45 P46 P47 AMIFC FMIFC VDDPLL VCOH VCOL GNDPLL EO0 EO1 IC P50 P51 P52 P53
PD178004, 178006, 178016, 178018
AMIFC AN10-AN15 BEEP BUSY EO0, EO1 FMIFC GND GNDPLL GNDPORT : AM Intermediate Frequency Counter Input : A/D Converter Input : Buzzer Output : Busy Output : Error Out Output : FM Intermediate Frequency Counter Input : Ground : PLL Ground : Port Ground P132-P134 : Port 13
PWM0-PWM2 : PWM Output REGCPU : Regulator for CPU Power Supply REGOSC RESET SB0, SB1 SCK0, SCK1 SCL SDA0, SDA1 SI0, SI1 SO0, SO1 STB TI1, TI2 : Regulator for Oscillator Circuit : Reset Input : Serial Data Bus Input/Output : Serial Clock Input/Output : Serial Clock Input/Output : Serial Data Input/Output : Serial Data Input : Serial Data Output : Strobe Output : Timer Clock Input
IC : Internally Connected INTP0-INTP6 : Interrupt Inputs P00-P06 P10-P15 P20-P27 P30-P37 P40-P47 P50-P57 P60-P67 P120-P125 : Port 0 : Port 1 : Port 2 : Port 3 : Port 4 : Port 5 : Port 6 : Port 12
VCOL, VCOH : Local Oscillator Input VDD : Power Supply VDDPLL VDDPORT X1, X2 : PLL Power Supply : Port Power Supply : Crystal Oscillator Connection
7
PD178004, 178006, 178016, 178018
2. BLOCK DIAGRAM
TI1/P33
8-bit TIMER/ EVENT COUNTER 1 8-bit TIMER/ EVENT COUNTER 2
PORT 0
P00 6 6 P01-P06 P10-P15
TI2/P34
PORT 1
8-bit TIMER 3
PORT 2
8
P20-P27
WATCHDOG TIMER
PORT 3
8
P30-P37
BASIC TIMER SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SCK0/SCL/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 ANI0/P10ANI5/P15 INTP0/P00INTP6/P06 78K/0 CPU CORE ROM
PORT 4
8
P40-P47
SERIAL INTERFACE 0
PORT 5
8
P50-P57
PORT 6 SERIAL INTERFACE 1
8
P60-P67
PORT 12
6
P120-P125
RAM 6 A/D CONVERTER
PORT 13 D/A CONVERTER (PWM)
3
P132-P134
3
PWM0/P132PWM2/P134
7
INTERRUPT CONTROL FREQUENCY COUNTER AMIFC FMIFC
BEEP/P36 RESET X1 X2 VDDPORT GNDPORT VDD
BUZZER OUTPUT RESET SYSTEM CONTROL CPU PERIPHERAL
PLL
EO0 EO1 VCOL VCOH
PLL VOLTAGE REGULATOR VOLTAGE REGULATOR VOSC VCPU
VDDPLL GNDPLL
REGOSC REGCPU GND
IC
Remark The internal ROM and RAM capacities depend on the version.
8
PD178004, 178006, 178016, 178018
3. PIN FUNCTION LIST 3.1 PORT PINS
Pin Name P00 P01-P06 P10-P15 I/O Input I/O I/O Port 0. 7-bit input/output port. Function Input only After Reset Alternate Function Input INTP0 INTP1-INTP6 ANI0-ANI5
Input/output mode can be specified bit-wise. Input Input
Port 1. 6-bit input/output port. Input/output mode can be specified bit-wise. Port 2. 8-bit input/output port. Input/output mode can be specified bit-wise.
P20 P21 P22 P23 P24 P25 P26 P27 P30-P32 P33 P34 P35 P36 P37 P40-P47
I/O
Input
SI1 SO1 SCK1 STB BUSY SI0/SB0/SDA0 SO0/SB1/SDA1 SCK0/SCL
I/O
Port 3. 8-bit input/output port. Input/output mode can be specified bit-wise.
Input TI1 TI2
--
-- BEEP -- I/O Port 4. 8-bit input/output port. Input/output mode can be specified in 8-bit units. Test input flag (KRIF) is set to 1 by falling edge detection. Port 5. 8-bit input/output port. Input/output mode can be specified bit-wise. Port 6. 8-bit input/output port. Input/output mode can be specified bit-wise. Middle voltage N-ch open drain input/output port. LEDs can be driven directly. Input --
P50-P57
I/O
Input
--
P60-P63 P64-P67
I/O
Input
--
P120-P125 I/O
Port 12. 6-bit input/output port. Input/output mode can be specified bit-wise. Port 13. 3-bit output port. N-ch open-drain output port.
Input
--
P132-P134 Output
--
PWM0-PWM2
9
PD178004, 178006, 178016, 178018
3.2 PINS OTHER THAN PORT PINS
Pin Name I/O Function External maskable interrupt inputs with specifiable valid edges (rising edge, falling edge, both rising and falling edges). SI0 SI1 SO0 SO1 SB0 SB1 SDA0 SDA1 SCK0 SCK1 SCL STB BUSY TI1 TI2 BEEP ANI0-ANI5 Output Input Output Input Input Serial interface automatic transmit/receive strobe output Serial interface automatic transmit/receive busy input External count clock input to 8-bit timer (TM1) External count clock input to 8-bit timer (TM2) Buzzer output A/D converter analog input PWM output Error out output from charge pump of the PLL frequency synthesizer Inputs PLL local band frequency (In HF, MF mode) Inputs PLL local band frequency (In VHF mode) Inputs AM intermediate frequency counter Inputs FM intermediate frequency counter System reset input System clock oscillation resonator connection Input Input -- -- -- -- -- -- -- -- -- Oscillation regulator. Connected to GND via a 0.1-F capacitor. CPU power supply regulator. Connected to GND via a 0.1-F capacitor. Positive power supply Ground Positive power supply for port block Ground for port block Positive power supply for PLL Ground for PLL Internally connected. Connected to GND or GNDPORT. -- -- -- -- -- -- -- -- -- Input Input Input I/O Serial interface serial clock input/output Input I/O Serial interface serial data input/output Input Output Serial interface serial data output Input Input Serial interface serial data input Input P25/SB0/SDA0 P20 P26/SB1/SDA1 P21 P25/SI0/SDA0 P26/SO0/SDA1 P25/SI0/SB0 P26/SO0/SB1 P27/SCL P22 P27/SCK0 P23 P24 P33 P34 P36 P10-P15 P132-P134 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- After Reset Alternate Function Input P00-P06
INTP0-INTP6 Input
PWM0-PWM2 Output EO0, EO1 VCOL VCOH AMIFC FMIFC RESET X1 X2 REGOSC REGCPU VDD GND VDDPORT GNDPORT VDDPLL GNDPLL IC Output Input Input Input Input Input Input -- -- -- -- -- -- -- -- -- --
10
PD178004, 178006, 178016, 178018
3.3 INPUT/OUTPUT CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
Table 3-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 3-1 for the configuration of the input/output circuit of each type. Table 3-1. I/O Circuit Type of Each Circuit
Pin Name P00/INTP0 P01/INTP1-P06/INTP6 P10/ANI0-P15/ANI5 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P30-P32 P33/TI1, P34/TI2 P35 P36/BEEP P37 P40-P47 P50-P57 P60-P63 P64-P67 P120-P125 P132/PWM0-P134/PWM2 EO0 EO1 VCOL, VCOH AMIFC, FMIFC IC -- -- Connected to GND or GNDPORT directly 19 DTS-EO1 DTS-EO2 DTS-AMP Input Set to disabled status by software and open Output Set to low-level output by software and open Open 5-G 5 13 5 5 8 5 I/O Circuit Type 2 8 11-A 8 5 8 5 8 10 I/O Input I/O Recommended Connections of Unused Pins Connected to GND or GNDPORT Set in general-purpose input port mode by software and individually connected to VDD, VDDPORT, GND, or GNDPORT via resistor.
11
PD178004, 178006, 178016, 178018
Figure 3-1. Pin Input/Output Circuit of List (1/2)
Type 2
Type 8
VDD IN data P-ch IN/OUT output disable Schmitt-Triggered Input with Hysteresis Characteristics N-ch
Type 5
Type 10
VDD data P-ch IN/OUT output disable N-ch open drain output disable data
VDD P-ch IN/OUT N-ch
input enable
Type 5-G
Type 11-A
VDD data P-ch IN/OUT output disable N-ch
VDD data P-ch IN/OUT output disable comparator + _ N-ch VREF (Threshold voltage) input enable N-ch P-ch
Remark All VDD and GND in the above figures are the positive power supply and ground potential of the ports, and should be read as VDDPORT and GNDPORT, respectively.
12
PD178004, 178006, 178016, 178018
Figure 3-1. Pin Input/Output Circuit of List (2/2)
Type 13 IN/OUT data output disable N-ch
Type DTS-EO2
VDDPLL
DW
P-ch OUT
UP
N-ch
Middle-Voltage Input Buffer
GNDPLL Type DTS-AMP
Type 19
VDDPLL OUT N-ch IN
Type DTS-EO1
VDDPLL DW P-ch OUT UP N-ch GNDPLL
Remark All VDD and GND in the above figures are the positive power supply and ground potential of the ports, and should be read as VDDPORT and GNDPORT, respectively.
13
PD178004, 178006, 178016, 178018
4. MEMORY SPACE
Figure 4-1 shows the PD178004, 178006, 178016 and 178018 memory map. Figure 4-1. Memory Map
FFFFH Special Function Registers (SFR) 256 x 8 bits FF00H FEFFH FEE0H FEDFH
General-Purpose Registers 32 x 8 bits
FABFH Use Prohibited F800H F7FFH Internal Expanded RAM 2048 x 8 bits F000H EFFFH Use ProhibitedNote 2
Note 1
Internal High-Speed RAM 1024 x 8 bits FB00H FAFFH Use Prohibited Data Memory Space FAE0H FADFH Buffer RAM 32 x 8 bits FAC0H FABFH
nnnnH+1 nnnnH Program Area 1000H 0FFFH CALLF Entry Area 0800H 07FFH Program Area 0080H 007FH
Use Prohibited
nnnnH + 1 nnnnH Program Memory Space 0000H 0040H 003FH
CALLT Table Area
Internal ROM
Note 3
Vectored Table Area 0000H
Notes 1. Available only for PD178016 and 178018 2. The PD178018 does not contain this use prohibited area. 3. The internal ROM capacity depends on the version (see the table below).
Corresponding Product Name Internal ROM Last Address nnnnH 7FFFH BFFFH EFFFH
PD178004 PD178006, 178016 PD178018
14
PD178004, 178006, 178016, 178018
5. PERIPHERAL HARDWARE FUNCTION FEATURES 5.1 PORTS
The following 3 types of I/O ports are available. * CMOS input (P00) : 1
* CMOS input/output (P01 to P06, port 1 to port 5, P64 to P67, port 12) : 54 * N-channel open-drain input/output (P60 to P63) :4 * N-ch open drain output (Port 13) Total Table 5-1. Port Functions :3 : 62
Name Port 0
Pin Name P00 P01 to P06 Dedicated input port pins
Function
Input/output port pins. Input/output specifiable bit-wise. Input/output port pins. Input/output specifiable bit-wise. Input/output port pins. Input/output specifiable bit-wise. Input/output port pins. Input/output specifiable bit-wise. Input/output port pins. Input/output specifiable in 8-bit units. Test flag (KRIF) is set to 1 by falling edge detection. Input/output port pins. Input/output specifiable bit-wise. N-channel open-drain input/output port pins. Input/output specifiable bit-wise. LED direct drive capability. Input/output port pins. Input/output specifiable bit-wise. Input/output port pins. Input/output specifiable bit-wise. N-ch open drain output port.
Port 1 Port 2 Port 3 Port 4 Port 5 Port 6
P10 to P15 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P63 P64 to P67
Port 12 Port 13
P120 to P125 P132 to P134
15
PD178004, 178006, 178016, 178018
5.2 CLOCK GENERATOR
The instruction execution time can be changed as follows. 0.44 s/0.88 s/1.78 s/3.56 s/7.11 s/14.22 s (@ 4.5-MHz crystal oscillator with system clock.) Figure 5-1. Clock Generator Block Diagram
Prescaler X1 X2
Clock to the PLL frequency synthesizer, basic timer and buzzer output control circuit.
System Clock Oscillator
fX Selector Scaler fXX Prescaler fXX fXX fXX 2 22 23 fXX 24 Selector Standby Control Circuit
Clock to peripheral hardware other than the above.
STOP
fX 2
Wait Control Circuit
CPU Clock (fCPU)
To INTP0 Sampling Clock
5.3 TIMER
The PD178004, 178006, 178016 and 178018 incorporate 5 channels of the timer. * Basic timer : 1 channel * 8-bit timer/event counter * 8-bit timer (D/A converter) * Watchdog timer Note
Note
: 2 channel : 1 channel : 1 channel
Used is shared with the 8/9-bit resolution x 3-channel D/A converter (PWM output). FIGURE 5-2. Basic Timer Block Diagram
4.5 MHz
Divider
INTTMC
16
PD178004, 178006, 178016, 178018
Figure 5-3. 8-Bit Timer/Event Counter Block Diagram
Internal Bus INTTM1 8-Bit Compare Register (CR10)
8-Bit Compare Register (CR20) Selector Match INTTM2
Match fxx/2-fxx/2 9 fx/2 11 TI1/P33 Selector 8-Bit Timer Register 1 (TM1) Selector Clear 8-Bit Timer Register 2 (TM2) Clear Selector Selector
fxx/2-fxx/2 9 fx/2 11 TI2/P34
Internal Bus
Figure 5-4. 8-Bit Timer (D/A Converter) Block Diagram
Internal bus INTPWM PWM data register 2Note (PWMR2) 4.5 MHz Clock generation block PWM duty setting block PWM data register 1 (PWMR1) PWM data register 0 (PWMR0) PWM mode select register PWM PWM PWM 0SE 1SE 2SE
Comparator
Comparator
Comparator
Output select block Output select block
P132/PWM0
Clear circuit
P133/PWM1
fPWM
b8
9-bit binary counter
b0
Output select block
P134/PWM2
PWM PWM PWM PWM PWM BIT CK0 MD ST RES PWM control register Internal bus
Note
The PWM data register 2 (PWMR2) is multiplexed with the PWM timer register (PWMTMR).
17
PD178004, 178006, 178016, 178018
Figure 5-5. Watchdog Timer Block Diagram
f xx 23
Prescaler
f xx 24
f xx 25
f xx 26
f xx 27
f xx 28
f xx 29
f xx 2 11
INTWDT Maskable Interrupt Request Selector 8-Bit Counter Control Circuit Reset INTWDT Non-Maskable Interrupt Request
5.4 BUZZER OUTPUT CONTROL CIRCUIT
The clock with the following frequency can be output as a buzzer output. * 1.5 kHz/3 kHz/6 kHz (@ 4.5-MHz crystal oscillator with system clock) Figure 5-6. Buzzer Output Control Circuit Block Diagram
3 kHz 6 kHz
Selector
1.5 kHz
BEEP/P36
3
TCL27 TCL26 TCL25 Timer Clock Select Register 2
P36 Output Latch
PM36 Port Mode Register 3
Internal Bus
18
PD178004, 178006, 178016, 178018
5.5 A/D CONVERTER
An A/D converter of 8-bit resolution x 6 channels is incorporated. The following two types of the A/D conversion operation start-up methods are available. * Hardware start * Software start Figure 5-7. A/D Converter Block Diagram
Resistor String ANI0/P10 ANI1/P11 ANI2/P12 ANI3/P13 ANI4/P14 ANI5/P15 Succesive Approximation Register (SAR) GND Selector Sample & Hold Circuit Voltage Comparator Tap Selector VDD
INTP3/P03
Edge Detection Circuit
Control Circuit
INTAD INTP3
A/D Conversion Result Register (ADCR)
Internal Bus
5.6 SERIAL INTERFACES
2 channels of the clocked serial interface are incorporated. * Serifal interface channel 0 * Serifal interface channel 1 Table 5-2. Types and Functions of Serial Interface
Function 3-wire serial I/O mode 3-wire serial I/O mode with automatic transmission/ reception function SBI (serial bus interface) mode 2-wire serial I/O mode I2C Bus Mode (MSB first) (MSB first) (MSB first) Serial Interface Channel 0 (MSB/LSB first switchable) Serial Interface Channel 1 (MSB/LSB first switchable) (MSB/LSB first switchable)
--
-- -- --
19
PD178004, 178006, 178016, 178018
Figure 5-8. Serial Interface Channel 0 Block Diagram
Internal Bus
SI0/SB0/SDA0/P25 Selector SO0/SB1/SDA1/P26 Serial I/O Shift Register 0 (SIO0) Output Latch
Selector
Bus Release/Command/ Acknowledge Detection Circuit Serial Clock Counter
Busy/Acknowledge Output Circuit
SCK0/SCL/P27
Interrupt Request Signal Generator
INTCSI0
fXX/2-fXX/28 Serial Clock Control Circuit Selector
Figure 5-9. Serial Interface Channel 1 Block Diagram
Internal Bus
Automatic Data Transmit/ Receive Address Pointer (ADTP)
Buffer RAM
Automatic Data Transmit/Receive Interval Specification Register (ADTI) Match
SI1/P20
Serial I/O Shift Register 1 (SIO1)
SO1/P21 5-Bit Counter STB/P23 Handshake Control Circuit
BUSY/P24
SCK1/P22
Serial Counter
Interrupt Request Signal Generator
INTCSI1
f XX/2-f XX/28 Serial Clock Control Circuit Selector
20
PD178004, 178006, 178016, 178018
5.7 PLL FREQUENCY SYNTHESIZER
Figure 5-10. PLL Frequency Synthesizer Block Diagram
Internal Bus PLL Mode Select Register PLL PLL MD1 MD0 2 VCOH Mixer VCOL Input Select Block Programmable Divider PLL Data Register (PLLRL, PLLRH, PLLR0) 2 fN Phase Comparator ( -DET) Charge Pump EO0 EO1 PLL NS0 PWM Data Transfer Register
fr
Voltage Control Generator
Note
4.5 MHz
Reference Frequency Generator
Unlock FF
4
Note
Low pass Filter
PLL PLL PLL PLL RF3 RF2 RF1 RF0 PLL Reference Mode Register PLL Unlock FF Judge Register Internal Bus
PLL UL0 EO Select Register
EOC ON0
Note
External circuit
21
PD178004, 178006, 178016, 178018
5.8 FREQUENCY COUNTER
Figure 5-11. Frequency Counter Block Diagram
2
Gate Time Control Block
FMIFC Input Select Block AMIFC
Start/Stop Control Block
IF Counter Register (IFC) Block
2
IFC IFC IFC IFC MD1 MD0 CK1 CK0 IF Counter Mode Select Register
IFC JG0 IF Counter Gate Judge Register Internal Bus
IFC IFC ST RES IF Counter Control Register
22
PD178004, 178006, 178016, 178018
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS 6.1 INTERRUPT FUNCTIONS
There are 17 interrupt functions of three different kinds, as shown below. * Non-maskable interrupt : 1 * Maskable interrupt * Software interrupt : 15 :1 Table 6-1. Interrupt Source List
Note 1
Interrupt Type Nonmaskable Maskable
Default Priority --
Interrupt Source Name INTWDT Trigger Watchdog timer overflow (watchdog timer mode 1 selected) Watchdog timer overflow (interval timer mode selected) Pin input edge detection
Internal/ External Internal
Basic Vector Table Configuration Address TypeNote 2 0004H (A)
0
INTWDT
(B)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 Software --
INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTCSI0 INTCSI1 INTTMC INTPWM INTTM1
External
0006H 0008H 000AH 000CH 000EH 0010H 0012H
(C) (D)
End of serial interface channel 0 transfer End of serial interface channel 1 transfer Generation of match signal of basic timer Generation of match signal of 8-bit timer Generation of match signal of 8-bit timer/ event counter 1 Generation of match signal of 8-bit timer/ event counter 2 End of conversion by A/D converter BRK instruction execution
Internal
0014H 0016H 0018H 001AH 001CH
(B)
INTTM2 INTAD BRK
001EH 0020H Internal 003EH (E)
Notes 1. The default priority is a priority order when two or more maskable interrupts are generated simultaneously. 0 is the highest order and 14, the lowest. 2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1, respectively.
23
PD178004, 178006, 178016, 178018
Figure 6-1. Interrupt Function Basic Configuration(1/2) (A) Internal non-maskable interrupt
Internal Bus
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
(B) Internal maskable interrupt
Internal Bus
MK
IE
PR
ISP
Interrupt Request
IF
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
(C) External maskable interrupt (INTP0)
Internal Bus
Sampling Clock Select Register (SCS)
External Interrupt Mode Register (INTM0)
MK
IE
PR
ISP
Interrupt Request
Sampling Clock
Edge Detection Circuit
IF
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
24
PD178004, 178006, 178016, 178018
Figure 6-1. Interrupt Function Basic Configuration(2/2) (D) External maskable interrupt (except INTP0)
Internal Bus
External Interrupt Mode Register (INTM0, INTM1)
MK
IE
PR
ISP
Interrupt Request
Edge Detection Circuit
IF
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
(E) Software interrupt
Internal Bus
Interrupt Request
Priority Control Circuit
Vector Table Address Generator
IF
: Interrupt request flag
IE : Interrupt enable flag ISP : In-service priority flag MK : Interrupt mask flag PR : Priority specification flag
25
PD178004, 178006, 178016, 178018
6.2 TEST FUNCTIONS
There is a test function as shown in Table 6-2. Table 6-2. Test Input Source List
Test Input Source Internal/External Name INTPT4 Trigger Port 4 falling edge detection External
Figure 6-2. Test Function Basic Configuration
Internal Bus
MK
Test Input
IF
Standby Release Signal
IF : Test input flag MK : Test mask flag
26
PD178004, 178006, 178016, 178018
7. STANDBY FUNCTION
There are the following two standby functions to reduce the system power consumption. * HALT mode : The CPU operating clock is stopped. The average consumption current can be reduced by intermittent operation in combination with the normal operating mode. * STOP mode : The system clock oscillation is stopped. All operations by the system clock are stopped and current consumption can be considerably reduced. Figure 7-1. Stand-by Function
System Clock Operation STOP Instruction Interrupt Request HALT Mode (Clock supply to CPU is stopped, oscillation continued) HALT Instruction
Interrupt Request
STOP Mode (System clock oscillation stopped)
8. RESET FUNCTION
There are the following three reset methods. * External reset input by RESET pin * Internal reset by watchdog timer runaway time detection * Internal reset by Power-On Clear (POC).
27
PD178004, 178006, 178016, 178018
9. INSTRUCTION SET
(1) 8-bit instructions MOV, XCH, ADD ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second Operand First Operand A #byte A r
[HL + byte]
Note
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL + B] [HL + C]
$addr16
1
None
ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV
MOV XCH
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP
ROR ROL RORC ROLC
r
MOV
MOV ADD ADDC SUB SUBC AND OR XOR CMP
INC DEC
B,C sfr saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP !addr16 PSW [DE] [HL] [HL + byte] [HL + B] [HL + C] X C MOV MOV MOV MOV MOV MOV MOV
DBNZ
DBNZ
INC DEC
PUSH POP ROR4 ROL4
MULU DIVUW
Note
Except r = A
28
PD178004, 178006, 178016, 178018
(2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand First Operand AX #word ADDW SUBW CMPW MOVW MOVW Note AX rpNote MOVW XCHW sfrp MOVW saddrp MOVW !addr16 MOVW SP MOVW None
rp
INCW DECW PUSH POP
sfrp saddrp !addr16 SP
MOVW MOVW MOVW
MOVW MOVW MOVW MOVW
Note
Only when rp = BC, DE or HL
(3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second Operand First Operand A.bit A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY MOV1 $addr16 BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR BT BF BTCLR None SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 NOT1
sfr.bit
MOV1
saddr.bit
MOV1
PSW.bit
MOV1
[HL].bit
MOV1
CY
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
MOV1 AND1 OR1 XOR1
(4) Call instruction/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second Operand First Operand Basic instruction Compound instruction BR AX !addr16 CALL BR !addr11 CALLF [addr5] CALLT $addr16 BR, BC, BNC BZ, BNZ BT, BF BTCLR DBNZ
(5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
29
PD178004, 178006, 178016, 178018
10. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25C)
Parameter Symbol Test Conditions Rating -0.3 to + 7.0 Excluding P60 to P63 P60 to P63 N-ch Open-drain -0.3 to VDD + 0.3 -0.3 to +16 -0.3 to VDD + 0.3 P132 to P134 N-ch Open-drain 16 Unit V V V V V
Power supply voltage VDD Input voltage VI1 VI2 Output voltage Output withstand voltage VO VBDS
Analog input voltage VAN Output current high IOH
P10 to P15 1 pin
Analog input pin
-0.3 to VDD + 0.3 -10 -15
V mA mA
P01 to P06, P30 to P37, P56, P57, P60 to P67, P120 to P125 total P10 to P15, P20 to P27, P40 to P47, P50 to P55, P132 to P134 total Output current low IOL Note 1 pin Peak value Effective value Operating ambient temperature Storage temperature TA
-15
mA
15 7.5 -40 to +85
mA mA C C
Tstg
-65 to +150
Note
Effective value should be calculated as follows: [Effective value] = [Peak value] x duty
Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter even momentarily. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. RECOMMENDED SUPPLY VOLTAGE RANGES (TA = -40 to +85C)
Parameter Symbol Test Conditions During CPU operation and PLL operation. While the CPU is operating and the PLL is stopped. Cycle Time: TCY 0.89 s While the CPU is operating and the PLL is stopped. Cycle Time: TCY = 0.44 s MIN. 4.5 3.5 TYP. MAX. 5.5 5.5 Unit V V
Power supply voltage VDD1 VDD2
VDD3
4.5
5.5
V
Remark TCY: Cycle Time (Minimum instruction execution time)
30
PD178004, 178006, 178016, 178018
DC CHARACTERISTICS (TA = -40 to +85C, VDD = 3.5 to 5.5 V) (1/3)
Parameter Input voltage high Symbol VIH1 P10 P30 P40 P64 to to to to P15, P32, P47, P67, Test Conditions P21, P23, P35 to P37, P50 to P57, P120 to P125 MIN. 0.7 VDD TYP. MAX. VDD Unit V
*
Input voltage low
VIH2
P00 to P06, P20, P22, P24 to P27, P33, P34, RESET P60 to P63 (N-ch Open-drain) P10 P30 P40 P64 to to to to P15, P32, P47, P67, P21, P23, P35 to P37, P50 to P57, P120 to P125
0.85 VDD
VDD
V
VIH3
0.7 VDD
15
V
VIL1
0
0.3 VDD
V
*
VIL2
P00 to P06, P20, P22, P24 to P27, P33, P34, RESET 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 4.5 V VDD 5.5 V IOH = -1 mA 3.5 V VDD < 4.5 V IOH = -100 A
0
0.15 VDD
V
VIL3
P60 to P63 (N-ch Open-drain)
0 0 VDD - 1.0
0.3 VDD 0.2 VDD
V V V
Output voltage high VOH1
VDD - 0.5
V
Output voltage low
VOL1
P50 to P57, P60 to P63
VDD = 4.5 to 5.5 V, IOH = 15 mA VDD = 4.5 to 5.5 V, IOL = 1.6 mA
0.4
2.0
V
P01 to P06, P10 to P15, P20 to P27, P30 to P37, P40 to P47, P64 to P67, P120 to P125, P132 to P134 VOL2 SB0, SB1, SCK0
0.4
V
VDD = 4.5 to 5.5 V, open-drain pulled-up (R = 1 K)
0.2 VDD
V
Remark The characteristics of an alternate function pin and a port pin are the same unless specified otherwise.
31
PD178004, 178006, 178016, 178018
DC CHARACTERISTICS (TA = -40 to +85C, VDD = 3.5 to 5.5 V)
Parameter Input leakage current high Symbol ILIH1 P00 to P06, P20 to P27, P40 to P47, P64 to P67, RESET P60 to P63 P00 to P06, P20 to P27, P40 to P47, P64 to P67, RESET P60 to P63 P132 to P134 VOUT = 15 V P10 to P15, P30 to P37, P50 to P57, P120 to P125, Test Conditions P10 to P15, P30 to P37, P50 to P57, P120 to P125, VIN = VDD MIN. TYP. MAX. 3
(2/3)
Unit
A
ILIH2 Input leakage current low ILIL1
VIN = 15 V VIN = 0 V
80 -3
A A
ILIL2 Output leakage current high Output leakage current low Output off leak current ILOH
-3Note 3
A A A A
ILOL
P132 to P134
VOUT = 0 V
-3 1
ILOF
EO0, EO1
VOUT = VDD, VOUT = 0 V
Note
When an input instruction is executed, the low-level input leakage current for P60 to P63 becomes -200 A (MAX.) only in one clock cycle (at no wait). It remains at -3 A (MAX.) for other than an input instruction.
Remark The characteristics of an alternate function pin and a port pin are the same unless specified otherwise.
* REFERENCE CHARACTERISTICS (TA = 25C, VDD = 5 V)
Par1ameter Symbol EO0 EO1 (EOCON0 = 1) EO1 (EOCON0 = 0) Output current low IOL1 EO0 EO1 (EOCON0 = 1) EO1 (EOCON0 = 0) VOUT = 1 V Test Conditions VOUT = VDD-1 V MIN. TYP. -4 -6 -2 6 8 3 MAX. Output current high IOH1
(1/2)
Unit mA mA mA mA mA mA
32
PD178004, 178006, 178016, 178018
DC CHARACTERISTICS (TA = -40 to +85C, VDD = 3.5 to 5.5 V)
Parameter Power SupplyNote 1 Current Symbol IDD1 Test Conditions While the CPU is operating and the PLL is stopped fX = 4.5 MHz operation While the CPU is operating and the PLL is stopped HALT Mode Pin X1 sine wave input VIN = VDD. fX = 4.5 MHz operation When the crystal is oscillating TCY = 0.89 sNote 2 TCY = 0.44 sNote 3 VDD = 4.5 to 5.5 V TCY = 0.89 sNote 2 MIN. TYP. 2.5 MAX. 15
(3/3)
Unit mA
IDD2 IDD3
4.0 0.7
27 1.5
mA mA
* *
Data Hold Power Supply Voltage
IDD4
TCY = 0.44 sNote 3 VDD = 4.5 to 5.5 V TCY = 0.44 s TCY = 0.89 s
1.0
2.0
mA
VDR1 VDR2 VDR3
4.5 3.5 2.6
5.5 5.5 5.5
V V V
When the crystal oscillator is stopped When power off by Power On Clear is detected While the crystal oscillator is stopped TA = 25C, VDD = 5V
Data Hold
IDR1
2 2
4 30
A A
Power Supply Current IDR2
Notes 1. The port current is not included. 2. When the Processor Clock Control register (PCC) is set at 00H, and the Oscillation Mode Select register (OSMS) is set at 00H. 3. When PCC is set at 00H and OSMS is set at 01H. Remarks 1. TCY: Cycle Time (Minimum instruction execution time) 2. fx: System clock oscillator frequency.
*
REFERENCE CHARACTERISTICS (TA = 25C, VDD = 5 V)
Parameter Power Supply Current Symbol IDD5 Test Conditions During CPU operation and PLL operation. VCOH pin sine wave input fIN = 130 MHz, VIN = 0.15 Vp-p TCY = 0.44 s
Note
(2/2)
MIN. TYP. 7 MAX. Unit mA
Note
When the Processor Clock Control register (PCC) is set at 00H, and the Oscillation Mode Select register (OSMS) is set at 01H.
Remark TCY: Cycle Time (Minimum instruction execution time)
33
PD178004, 178006, 178016, 178018
AC CHARACTERISTICS (1) BASIC OPERATION (TA = -40 to +85C, VDD = 3.5 to 5.5 V)
Parameter Cycle time (Minimum instruction execution time) TI1, TI2 input frequency TI1, TI2 input high/ low-level width tTIH, tTIL fTI Symbol TCY fXX = fX/2 fXX = fX
Note 1
Test Conditions , fX = 4.5 MHz operation 4.5 VDD 5.5 V 3.5 VDD < 4.5 V
MIN. 0.89 0.44 0.89 0 0 111 1.8 8/fsam
Note 3
TYP.
MAX. 14.22 7.11 7.11 4.5 275
Unit
s s s
MHz kHz ns
Note 2
,
fX = 4.5 MHz operation 4.5 VDD 5.5 V 3.5 V VDD 4.5 V 4.5 VDD 5.5 V 3.5 V VDD 4.5 V INTP0 INTP1-INTP6
s s s s
Interrupt input high/ TINTH, low-level width RESET low level width TINTL tRSL
10 10
Notes 1. When oscillation mode selection (OSMS) register is set at 00H. 2. When OSMS is set at 01H. 3. In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register (SCS), selection of fsam is possible between fXX/2N, fXX/32, fXX/64 and fXX/128 (when N = 0 to 4). Remarks 1. fXX: System clock frequency (fX or fX/2) 2. fX: System clock oscillation frequency TCY vs VDD (At FXX = FX/2 system clock operation) TCY vs VDD (At FXX = FX system clock operation)
60
60
10 Cycle Time TCY [s] Operation Guaranteed Range 2.0 1.0 0.5 0.4 Cycle Time TCY [s]
10
2.0 1.0 0.5 0.4
Operation Guaranteed Range
0 1 2 3 4 5 6 Power Supply Voltage VDD [V]
0 1 2 3 4 5 6 Power Supply Voltage VDD [V]
34
PD178004, 178006, 178016, 178018
(2) SERIAL INTERFACE (TA = -40 to +85C, VDD = 3.5 to 5.5 V) (a) Serial interface channel 0 (i) 3-wire serial I/O mode (SCK0 ... internal clock output)
Parameter SCK0 cycle time Symbol tKCY1 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SCK0 high-/low-level width tKH1, tKL1 SI0 setup time (to SCK0) tSIK1 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SI0 hold time (from SCK0) tKSI1 C = 100 pFNote MIN. 800 1600 tKCY1/2 - 50 tKCY1/2 - 100 100 150 400 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SO0 output delay time from SCK0 tKSO1
Note
C is the load capacitance of SO0 output line. (ii) 3-wire serial I/O mode (SCK0 ... external clock input)
Parameter Symbol tKCY2 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V MIN. 800 1600 400 800 100 400 C = 100 pFNote 300 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SCK0 cycle time
SCK0 high-/low-level width
tKH2, tKL2
4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V
SI0 setup time (to SCK0) SI0 hold time (from SCK0)
tSIK2 tKSI2
SO0 output delay time from SCK0 tKSO2 SCK0 at rising or falling edge time tR2, tF2
Note
C is the load capacitance of SO0 output line.
35
PD178004, 178006, 178016, 178018
(iii) SBI mode (SCK0 ... internal clock output)
Parameter SCK0 cycle time Symbol tKCY3 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SCK0 high-/low-level width tKH3, tKL3 SB0, SB1 setup time (to SCK0) tSIK3 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width tKSB tSBK tSBH tSBL tKSI3 tKSO3 R = 1 k C = 100 pF
Note
MIN. 800 3200 tKCY3/2 - 50 tKCY3/2 - 150 100 300 tKCY3/2
TYP.
MAX.
Unit ns ns ns ns ns ns ns
4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V
0 0 tKCY3 tKCY3 tKCY3 tKCY3
250 1000
ns ns ns ns ns ns
Note R and C are the load resistance and load capacitance of SB0 and SB1 output line. (iv) SBI mode (SCK0 ... external clock input)
Parameter SCK0 cycle time Symbol tKCY4 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SCK0 high-/low-level width tKH4, tKL4 SB0, SB1 setup time (to SCK0) tSIK4 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 SB0, SB1 from SCK0 SCK0 from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width tKSB tSBK tSBH tSBL tKSI4 tKSO4 R = 1 k C = 100 pF
Note
MIN. 800 3200 400 1600 100 300 tKCY4/2
TYP.
MAX.
Unit ns ns ns ns ns ns ns
4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V
0 0 tKCY4 tKCY4 tKCY4 tKCY4
300 1000
ns ns ns ns ns ns
SCK0 at rising or falling edge time tR4, tF4
1000
ns
Note
R and C are the load resistance and load capacitance of SB0 and SB1 output line.
36
PD178004, 178006, 178016, 178018
(v) 2-wire serial I/O mode (SCK0 ... internal clock output)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width Symbol tKCY5 tKH5 tKL5 Test Conditions R = 1 k C = 100 pFNote MIN. 1600 tKCY5/2 - 160 4.5 V VDD 5.5 V tKCY5/2 - 50 3.5 V VDD < 4.5 V tKCY5/2 - 100 SB0, SB1 setup time (to SCK0) tSIK5 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 300 350 400 SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0 tKSI5 tKSO5 600 0 300 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns
Note
R and C are the load resistance and load capacitance of SCK0, SB0 and SB1 output line. (vi) 2-wire serial I/O mode (SCK0 ... external clock input)
Parameter Symbol tKCY6 tKH6 tKL6 tSIK6 tKSI6 tKSO6 R = 1 k 4.5 V VDD 5.5 V Test Conditions MIN. 1600 650 800 100 tKCY6/2 0 0 300 500 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, SB1 setup time (to SCK0) SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from SCK0
C = 100 pFNote 3.5 V VDD < 4.5 V
SCK0 at rising or falling edge time tR6, tF6
Note
R and C are the load resistance and load capacitance of SB0 and SB1 output line.
37
PD178004, 178006, 178016, 178018
(vii) I 2C Bus mode (SCL ... internal clock output)
Parameter SCL cycle time SCL high-level width SCL low-level width SDA0, SDA1 setup time (to SCL) SDA0, SDA1 hold time (from SCL) SDA0, SDA1 output delay time (from SCL) SDA0, SDA1 from SCL or SDA0, SDA1 from SCL SCL from SDA0, SDA1 SDA0, SDA1 high-level width tKSB Symbol tKCY7 tKH7 tKL7 tSIK7 tKSI7 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V Test Conditions R = 1 k C = 100 pFNote MIN. 10 tKCY7 - 160 tKCY7 - 50 200 0 TYP. MAX. Unit
s
ns ns ns ns
tKSO7
0 0 200
300 500
ns ns ns
tSBK tSBH
400 500
ns ns
Note
R and C are the load resistance and load capacitance of SCL, SDA0 and SDA1 output line. (viii) I 2 C Bus mode (SCL ... external clock input)
Parameter Symbol tKCY8 tKH8, tKL8 tSIK8 tKSI8 4.5 V VDD 5.5 V
Note
Test Conditions
MIN. 1000 400 200 0
TYP.
MAX.
Unit ns ns ns ns
SCL cycle time SCL high-/low-level width SDA0, SDA1 setup time (to SCL) SDA0, SDA1 hold time (from SCL) SDA0, SDA1 output delay time from SCL SDA0, SDA1 from SCL or SDA0, SDA1 from SCL SCL from SDA0, SDA1 SDA0, SDA1 high-level width SCL at rising or falling edge time
tKSO8
R = 1 k C = 100 pF
0 0 200
300 500
ns ns ns
3.5 V VDD < 4.5 V
tKSB
tSBK tSBH tR8, tF8
400 500 1000
ns ns ns
Note
R and C are the load resistance and load capacitance of SDA0 and SDA1 output line.
38
PD178004, 178006, 178016, 178018
(b) Serial interface channel 1 (i) 3-wire serial I/O mode (SCK1 ... internal clock output)
Parameter SCK1 cycle time Symbol tKCY9 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SCK1 high/low-level width tKH9, tKL9 SI1 setup time (to SCK1) tSIK9 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SI1 hold time (from SCK1) SO1 output delay time (from SCK1) tKSI9 tKSO9 C = 100 pF
Note
MIN. 800 1600 tKCY9/2 - 50 tKCY9/2 - 100 100 150 400
TYP.
MAX.
Unit ns ns ns ns ns ns ns
300
ns
Note
C is the load capacitance of SO1 output line. (ii) 3-wire serial I/O mode (SCK1 ... external clock input)
Parameter Symbol tKCY10 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V MIN. 800 1600 400 800 100 400 C = 100 pFNote 300 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SCK1 cycle time
SCK1 high/low-level width
tKH10, tKL10
4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V
SI1 setup time (to SCK1) SI1 hold time (from SCK1) SO1 output delay time (from SCK1)
tSIK10 tKSI10 tKSO10
SCK1 at rising or falling edge time tR10, tF10
Note
C is the load capacitance of SO1 output line.
39
PD178004, 178006, 178016, 178018
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... internal clock output)
Parameter SCK1 cycle time Symbol tKCY11 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SCK1 high/low-level width tKH11, tKL11 SI1 setup time (to SCK1) tSIK11 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V SI1 hold time (from SCK1) SO1 output delay time (from SCK1) STB from SCK1 Strobe signal high-level width Busy signal setup time (to busy signal detection timing) Busy signal hold time (from busy signal detection timing) SCK1 from busy inactive tSPS tKSI11 tKSO11 tSBD tSBW tBYS 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V C = 100 pFNote tKCY11/2 - 100 tKCY11/ - 30 100 MIN. 800 1600 tKCY11/2 - 50 tKCY11/2 - 100 100 150 400 300 tKCY11/2 + 100 tKCY11 + 30 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns
tBYH
100 150 2tKCY11
ns ns ns
Note
C is the load capacitance of SO1 output line. (iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... external clock input)
Parameter Symbol tKCY12 Test Conditions 4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V MIN. 800 1600 400 800 100 400 C = 100 pFNote 300 1000 TYP. MAX. Unit ns ns ns ns ns ns ns ns
SCK1 cycle time
SCK1 high/low-level width
tKH12, tKL12
4.5 V VDD 5.5 V 3.5 V VDD < 4.5 V
SI1 setup time (to SCK1) SI1 hold time (from SCK1) SO1 output delay time (from SCK1)
tSIK12 tKSI12 tKSO12
SCK1 at rising or falling edge time tR12, tF12
Note
C is the load capacitance of SO1 output line.
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PD178004, 178006, 178016, 178018
AC TIMING TEST POINT (EXCLUDING X1 INPUT)
0.8 VDD 0.2 VDD
Test Points
0.8 VDD 0.2 VDD
TI Timing
1/fTI
tTIL
tTIH
TI1, TI2
Interrupt Input Timing
tINTL tINTH
INTP0-INTP6
RESET Input Timing
tRSL
RESET
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PD178004, 178006, 178016, 178018
SERIAL TRANSFER TIMING 3-Wire Serial I/O Mode:
tKCYm tKLm tRn SCK0, SCK1 tSIKm tKSIm tKHm tFn
SI0, SI1 tKSOm
Input Data
SO0, SI1
Output Data
Remark m = 1, 2, 9, 10 n = 2, 10 SBI Mode (Bus Release Signal Transfer):
tKCY3,4 tKL3,4 tR4 SCK0 tKSB tSBL tSBH tSBK tSIK3,4 tKSI3, 4 tKH3,4 tF4
SB0, SB1 tKSO3,4
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PD178004, 178006, 178016, 178018
SBI Mode (Command Signal Transfer):
tKCY3,4 tKL3,4 tR4 tKH3,4 tF4
SCK0 tSIK3,4 tKSB tSBK tKSI3,4
SB0, SB1 tKSO3,4
2-Wire Serial I/O Mode:
tKCY5,6 tKL5,6 tR6 SCK0 tSIK5,6 tKSO5,6 SB0, SB1 tKSI5,6 tKH5,6 tF6
I 2C Bus Mode:
tF8 SCL tKL7, 8
tR8
tKCY7, 8 tSIK7, 8 tKSO7, 8 tKSB tSBK tKSB
tKSI7, 8
tKH7, 8
SDA0, SDA1 tSBH tSBK
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PD178004, 178006, 178016, 178018
3-Wire Serial I/O Mode with Automatic Transmit/Receive Function:
SO1
D2
D1
D0
D7
SI1
D2 tSIK11,12 tKSO11,12
D1
D0 tKSI11,12 tKH11,12 tF12
D7
SCK1 tR12 tKL11,12 STB tKCY11,12 tSBD tSBW
3-Wire Serial I/O Mode with Automatic Transmit/Receive Function (Busy Processing):
SCK1
7
8
9Note
10Note tBYS
10+nNote tBYH tSPS
1
BUSY (Active high)
Note
The signal is not actually driven low here; it is shown as such to indicate the timing.
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PD178004, 178006, 178016, 178018
*
A/D CONVERTER CHARATERISTICS (TA = -40 to +85C, VDD = 4.5 to 5.5 V)
Parameter Resolution Conversion total error Conversion time Sampling time Analog input voltage tCONV tSAMP VIAN 22.2 15/fXX 0 VDD Symbol Test Conditions MIN. 8 TYP. 8 MAX. 8 3.0 44.4 Unit bit LSB
s s
V
*
Remarks 1. fXX: System clock frequency (fX/2) 2. fX: System clock oscillation frequency PLL CHARACTERISTICS (TA = -40 to +85C, VDD = 4.5 to 5.5 V)
Parameter Operating Frequency Symbol fIN1 fIN2 fIN3 Test Conditions VCOL Pin MF Mode Sine wave input VIN = 0.1 Vp-p VCOL Pin HF Mode Sine wave input VIN = 0.2 Vp-p VCOH Pin VHF Mode Sine wave input VIN = 0.15 Vp-p MIN. 0.5 9 60 TYP. MAX. 3 55 160 Unit MHz MHz MHz
*
Parameter Operating Frequency
IFC CHARACTERISTICS (TA = -40 to +85C, VDD = 4.5 to 5.5 V)
Symbol fIN4 Test Conditions AMIFC Pin AMIF Count Mode Sine wave input VIN = 0.1 Vp-pNote FMIFC Pin FMIF Count Mode Sine wave input VIN = 0.1 Vp-pNote FMIFC Pin AMIF Count Mode Sine wave input VIN = 0.1 Vp-pNote MIN. 0.4 TYP. MAX. 0.5 Unit MHz
fIN5
10
11
MHz
fIN6
0.4
0.5
MHz
Note
The condition of a sine wave input of VIN = 0.1 Vp-p is the standard value for operation of this device during stand-alone operation, so in consideration of the effect of noise, it is recommended that operation be at an input amplitude condition of VIN = 0.15 Vp-p.
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PD178004, 178006, 178016, 178018
11. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14 x 14)
A B
60 61
41 40 detail of lead end
D
C
S
80 1
21 20
F
G
H
IM
J K
P
N
L S80GC-65-3B9-3
NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q S
MILLIMETERS 17.2 0.4 14.0 0.2 14.0 0.2 17.2 0.4 0.8 0.8 0.30 0.10 0.13 0.65 (T.P.) 1.6 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.7 0.1 0.1 3.0 MAX.
M
INCHES 0.677 0.016 0.551+0.009 -0.008 0.551+0.009 -0.008 0.677 0.016 0.031 0.031 0.012+0.004 -0.005 0.005 0.026 (T.P.) 0.063 0.008 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.106 0.004 0.004 0.119 MAX.
46
55
Q
PD178004, 178006, 178016, 178018
12. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document "Semiconductor Device Mounting Technology Manual" (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 12-1. Surface Mounting Type Soldering Conditions
PD178004GC-xxx-3B9 : 80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch) PD178006GC-xxx-3B9 : 80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch) PD178016GC-xxx-3B9 : 80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch) PD178018GC-xxx-3B9 : 80-pin plastic QFP (14 x 14 mm, 0.65 mm pitch)
Recommended Condition Symbol IR35-00-3
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235C, Duration: 30 sec. max. (at 210C or above), Number of times: Three times max. Package peak temperature: 215C, Duration: 40 sec. max. (at 200C or above), Number of times: Three times max. Solder bath temperature : 260C max., Duration : 10 sec. max., Number of times : once, Preheating temperature : 120C max. (package surface temperature) Pin temperature: 300C max. Duration: 3 sec. max. (per pin row)
VPS
VP15-00-3
Wave soldering
WS60-00-1
Partial heating
--
Caution Do not use different soldering method together (except for partial heating).
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PD178004, 178006, 178016, 178018
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD178018 subseries. Language Processing Software
RA78K/0Notes 1, 2, 3, 4 CC78K/0
Notes 1, 2, 3, 4 Notes 1, 2, 3, 4 Notes 1, 2, 3, 4
78K/0 series common assembler package 78K/0 series common C compiler package
DF178018
PD178018 subseries common device file
78K/0 series common C compiler library source file
CC78K/0-L
PROM Writing Tools
PG-1500 PG-178P018GC PA-178P018KK-T PG-1500 controllerNotes 1, 2 PG-1500 control program PROM programmer Programmer adapters connected to a PG-1500
Debugging Tools
IE-78000-R In-circuit emulator common to 78K/0 series In-circuit emulator common to 78K/0 series (for the integration debugger) Break board common to 78K/0 series Emulation board common to PD178018 subseries Emulation probe common to PD78234 subseries Socket for mounting on target system board created for 80-pin plastic QFP (GC-3B9 type) Jig used when removing the PD178P018KK-T from the EV-9200GC-80. 78K/0 series common system simulator Integration debugger for IE-78000-R-A IE-78000-R screen debugger
*
IE-78000-R-A IE-78000-R-BK IE-178018-R-EM EP-78230GC-R EV-9200GC-80 EV-9900 SM78K0 ID78K0
Notes 5, 6, 7
Notes 4, 5, 6, 7 Notes 1, 2 Notes 1, 2, 4, 5, 6, 7
SD78K/0
DF178018
PD178018 subseries device file
Real-Time OS
RX78K/0Notes 1, 2, 3, 4 MX78K0
Notes 1, 2, 3, 4
78K/0 series real-time OS 78K/0 series OS
Notes 1. PC-9800 series (MS-DOSTM) based 2. IBM PC/ATTM and compatible (PC DOSTM/IBM-DOSTM/MS-DOS) based 3. HP9000 series 300TM based 4. HP9000 series 700TM (HP-UXTM) based, SPARCstationTM (SunOSTM) based, EWS-4800 series (EWS-UX/V) based 5. PC-9800 series (MS-DOS + WindowsTM) based 6. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based 7. NEWSTM (NEWS-OSTM) based
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PD178004, 178006, 178016, 178018
Fuzzy Inference Development Support System
FE9000Note 1/FE9200Note 2 FT9080 FI78K0
Note 1
Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger
/FT9085
Note 3
Notes 1, 3 Notes 1, 3
FD78K0
Notes 1. PC-9800 series (MS-DOS) based 2. IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS + Windows) based 3. IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS) based Remarks 1. Please refer to the 78K/0 Series Selection Guide (U11126E) for information on third party development tools. 2. The RA78K/0, CC78K/0, SD78K/0, ID78K/0, SM78K/0 and RX78K/0 are used in combination with the DF178018.
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PD178004, 178006, 178016, 178018
APPENDIX B. RELATED DOCUMENTS
Device Documents
Title Document No. (Japanese) U11410J IEU-849 U10904J U10903J Document No. (English) U11410E IEU-1372 -- -- -- U10121E
PD178018 Subseries User's Manual
78K/0 Series User's Manual--Instruction 78K/0 Series Instruction Set 78K/0 Series Instruction Table
PD178018 Subseries Special Function Register Table
78K/0 Series Application Note Basics (II)
To be prepared
U10121J
Development Tool Documents (User's Manual)
Title RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K Series C Compiler Operation Language CC78K/0 C Compiler Operation Language CC78K/0 C Compiler Application Notes CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS) Based PG-1500 Controller IBM PC Series (PC DOS) Based IE-78000-R IE-78000-R-A IE-78000-R-BK IE-178018-R-EM EP-78230 SM78K0 System Simulator Windows Based SM78K Series System Simulator Reference External Parts User open Interface Specifications Reference Reference Guide Introduction Reference SD78K/0 Screen Debugger IBM PC/AT (PC DOS) Based Introduction Reference Programming Know-how Document No. (Japanese) EEU-809 EEU-815 EEU-817 EEU-656 EEU-655 U11517J U11518J EEA-618 EEU-777 EEU-651 EEU-704 EEU-5008 EEU-810 U10057J EEU-867 U10668J EEU-985 U10181J U10092J Document No. (English) EEU-1399 EEU-1404 EEU-1402 EEU-1280 EEU-1284 U11517E U11518E EEA-1208 -- EEU-1335 EEU-1291 U10540E U11376E U10057E EEU-1427 U10668E EEU-1515 U10181E U10092E
ID78K0 Integrated Debugger EWS Based ID78K0 Integrated Debugger PC Based
U11151J U11539J U11649J EEU-852 U10952J EEU-5024 U11279J
U11151E U11539E U11649E -- -- EEU-1414 EEU-1413
*
ID78K0 Integrated Debugger Windows Based SD78K/0 Screen Debugger PC-9800 Series (MS-DOS) Based
Caution The contents of the above documents are subject to change without notice. Please ensure that the latest versions are used in design work, etc.
50
PD178004, 178006, 178016, 178018
Related Documents for Embedded Software (User's Manual)
Title 78K/0 Series Realtime OS Basics Installation Technical 78K/0 Series OS MX78K0 Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System--Translator 78K/0 Series Fuzzy Inference Development Support System--Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System --Fuzzy Inference Debugger EEU-858 EEU-921 EEU-1441 EEU-1458 Basics Document No. (Japanese) U11537J U11536J U11538J EEU-5010 EEU-829 EEU-862 Document No. (English) -- -- -- -- EEU-1438 EEU-1444
Other Documents
Title IC Package Manual Semiconductor Device Mounting Technology Manual Quality Guides on NEC Semiconductor Devices NEC Semiconductor Device Reliability and Quality Control Electrostatic Discharge (ESD) Test Semiconductor Device Quality Assurance Guide Microcomputer-related Product Guide (Products by other Manufacturers) Document No. (Japanese) C10943X C10535J C11531J C10983J MEM-539 C11893J U11416J C10535E C11531E C10983E -- MEI-1202 -- Document No. (English)
Caution The contents of the above documents are subject to change without notice. Ensure that the latest versions are used in design work, etc.
51
PD178004, 178006, 178016, 178018
[MEMO]
52
PD178004, 178006, 178016, 178018
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
53
PD178004, 178006, 178016, 178018
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96. 8
54
PD178004, 178006, 178016, 178018
[MEMO]
55
PD178004, 178006, 178016, 178018
Purchase of NEC I 2 C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I 2C Standard Specification as defined by Philips.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation. HP9000 Series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or reexport of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5
56

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