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74F273 Octal D-Type Flip-Flop
April 1988 Revised August 1999
74F273 Octal D-Type Flip-Flop
General Description
The 74F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
Features
s Ideal buffer for MOS microprocessor or memory s Eight edge-triggered D-type flip-flops s Buffered common clock s Buffered, asynchronous Master Reset s See 74F377 for clock enable version s See 74F373 for transparent latch version s See 74F374 for 3-STATE version
Ordering Code:
Order Number 74F273SC 74F273SJ 74F273PC Package Number M20B M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
(c) 1999 Fairchild Semiconductor Corporation
DS009511
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74F273
Unit Loading/Fan Out
U.L. Pin Names D0-D7 MR CP Q0-Q7 Data Inputs Master Reset (Active LOW) Clock Pulse Input (Active Rising Edge) Data Outputs Description HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 Input IIH/IIL Output IOH/IOL 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA -1 mA/20 mA
Mode Select-Function Table
Inputs Operating Mode MR Reset (Clear) Load "1" Load "0" L H H CP Dn X h l Output Qn L H L

X
H = HIGH Voltage Level steady state h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition L = LOW Voltage Level steady state I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X = Immaterial = LOW-to-HIGH clock transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74F273
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (min) twice the rated IOL (mA) 4000V -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI ICEX VID IOD IIL IOS ICCH ICCL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Short-Circuit Current Power Supply Current -60 4.75 3.75 -0.6 -150 44 56 10% VCC 5% VCC 10% VCC 5% VCC 2.5 2.7 0.5 0.5 5.0 7.0 50 Min 2.0 0.8 -1.2 Typ Max Units V V V V V A A A V A mA mA mA Min Min Min Max Max Max 0.0 0.0 Max Max Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA IOL = 20 mA VIN = 2.7V VIN = 7.0V VOUT = VCC IID = 1.9 A All other pins grounded VIOD = 150 mV All other pins grounded VIN = 0.5V VOUT = 0V CP = Dn = MR = HIGH
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74F273
AC Electrical Characteristics
TA = +25C Symbol Parameter Min fMAX tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay Clock to Output Propagation Delay MR to Output 160 3.0 4.0 4.5 7.0 9.00 9.5 VCC = +5.0V CL = 50 pF Typ Max TA = -55C to +125C VCC = 5.0V CL = 50 pF Min 95 2.5 3.0 3.0 9.5 11.0 11.0 Max TA = 0C to +70C VCC = 5.0V CL = 50 pF Min 130 2.5 3.5 4.0 7.5 9.0 10.0 Max MHz ns ns Units
AC Operating Requirements
TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tW(L) tW(H) tW(L) tREC Setup Time, HIGH or LOW Data to CP Hold Time, HIGH or LOW Data to CP MR Pulse Width, LOW CP Pulse Width HIGH or LOW Recovery Time, MR to CP 3.0 3.5 0.5 1.0 6.0 6.0 6.0 3.0 Max TA = -55C to +125C VCC = 5.0V Min 3.5 4.0 1.0 1.0 4.0 5.0 5.0 4.5 Max TA = 0C to +70C VCC = 5.0V Min 3.0 3.5 0.5 1.0 6.0 6.0 6.0 3.5 ns ns ns ns Max Units
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74F273
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74F273 Octal D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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