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74HC73
Dual JK flip-flop with reset; negative-edge trigger
Rev. 03 -- 12 November 2004 Product data sheet
1. General description
The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. The 74HC is a dual negative-edge triggered JK flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
2. Features
s Low-power dissipation s Complies with JEDEC standard no. 7A s ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. s Multiple package options s Specified from -40 C to +80 C and from -40 C to +125 C.
Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
3. Quick reference data
Table 1: Quick reference data GND = 0 V; Tamb = 25 C; tr = tf = 6 ns. Symbol tPHL, tPLH Parameter propagation delay nCP to nQ nCP to nQ nR to nQ, nQ fmax CI CPD
[1]
Conditions CL = 15 pF; VCC = 5 V
Min -
Typ 16 16 15 77 3.5 30
Max -
Unit ns ns ns MHz pF pF
maximum clock frequency input capacitance power dissipation capacitance per flip-flop
CL = 15 pF; VCC = 5 V
-
VI = GND to VCC
[1]
-
CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of outputs.
4. Ordering information
Table 2: Ordering information Package Temperature range Name 74HC73N 74HC73D 74HC73DB 74HC73PW -40 C to +125 C -40 C to +125 C -40 C to +125 C -40 C to +125 C DIP14 SO14 SSOP14 Description plastic dual in-line package; 14 leads (300 mil) plastic shrink small outline package; 14 leads; body width 5.3 mm Version SOT27-1 SOT337-1 SOT402-1 Type number
plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm
9397 750 13815
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Product data sheet
Rev. 03 -- 12 November 2004
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Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
5. Functional diagram
14 1J
J FF1 CP
Q
1Q 12
1 1CP
3 1K
K R
Q
1Q 13
2 1R
7 2J
J FF2 CP
Q
2Q 9
5 2CP
10 2K
K R
Q
2Q 8
6 2R
001aab981
Fig 1. Functional diagram
4 14 7 1J 2J J FF CP K R 1R 2R 26 Q 1Q 13 2Q 8 7 5 10 6
001aab979
1J
1Q 12 Q 2Q 9
1 3 2
12
C1
1K R 13
1 1CP 5 2CP 3 10 1K 2K
1J
9
C1
1K R
001aab980
8
Fig 2. Logic symbol
Fig 3. IEC logic symbol
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Product data sheet
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Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
C K
C
C
C
Q J C R C C C Q
CP
C C
001aab982
Fig 4. Logic diagram (one flip-flop)
6. Pinning information
6.1 Pinning
1CP 1R 1K VCC 2CP 2R 2J
1 2 3 4 5 6 7
001aab978
14 1J 13 1Q 12 1Q
73
11 GND 10 2K 9 8 2Q 2Q
Fig 5. Pin configuration
6.2 Pin description
Table 3: Symbol 1CP 1R 1K VCC 2CP 2R 2J 2Q 2Q 2K
9397 750 13815
Pin description Pin 1 2 3 4 5 6 7 8 9 10 Description clock input for flip-flop 1 (HIGH-to-LOW, edge-triggered) asynchronous reset input for flip-flop 1 (active LOW) synchronous K input for flip-flop 1 positive supply voltage clock input for flip-flop 2 (HIGH-to-LOW, edge-triggered) asynchronous reset input for flip-flop 2 (active LOW) synchronous J input for flip-flop 2 complement flip-flop 2 output true flip-flop 2 output synchronous K input for flip-flop 2
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Product data sheet
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Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
Pin description ...continued Pin 11 12 13 14 Description ground (0 V) true flip-flop 1 output complement flip-flop 1 output synchronous J input for flip-flop 1
Table 3: Symbol GND 1Q 1Q 1J
7. Functional description
7.1 Function table
Table 4: Input nR L H nCP X nJ X h l h l
[1]
Function table [1] Output nK X h h l l nQ L q L H q nQ H q H L q asynchronous reset toggle load 0 (reset) load 1 (set) hold (no change) Operating mode
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition; q = state of referenced output one set-up time prior to the HIGH-to-LOW CP transition; X = don't care; = HIGH-to-LOW CP transition.
8. Limiting values
Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC, IGND Tstg Ptot Parameter supply voltage input diode current output diode current output source or sink current VCC or GND current storage temperature power dissipation DIP14 package SO14, SSOP14 and TSSOP14 packages
[1] [2]
9397 750 13815
Conditions VI < -0.5 V or VI > VCC + 0.5 V VO < -0.5 V or VO > VCC + 0.5 V VO = -0.5 V to VCC + 0.5 V
Min -0.5 -65
[1] [2]
Max +7 20 20 25 50 +150 750 500
Unit V mA mA mA mA C mW mW
-
Above 70 C: Ptot derates linearly with 12 mW/K. Above 70 C: Ptot derates linearly with 8 mW/K.
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Product data sheet
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Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
9. Recommended operating conditions
Table 6: Symbol VCC VI VO tr, tf Recommended operating conditions Parameter supply voltage input voltage output voltage input rise and fall times except for nCP ambient temperature VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Conditions Min 2.0 0 0 -40 Typ 5.0 6.0 Max 6.0 VCC VCC 1000 500 400 +125 Unit V V V ns ns ns C
Tamb
10. Static characteristics
Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 25 C VIH HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level output voltage VI = VIH or VIL IO = -20 A; VCC = 2.0 V IO = -20 A; VCC = 4.5 V IO = -20 A; VCC = 6.0 V IO = -4 mA; VCC = 4.5 V IO = -5.2 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 4 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V ILI ICC CI input leakage current quiescent supply current input capacitance VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V 0 0 0 0.15 0.16 3.5 0.1 0.1 0.1 0.26 0.26 0.1 4.0 V V V V V A A pF 1.9 4.4 5.9 3.98 5.48 2.0 4.5 6.0 4.32 5.81 V V V V V 1.5 3.15 4.2 1.2 2.4 3.2 0.8 2.1 2.8 0.5 1.35 1.8 V V V V V V Conditions Min Typ Max Unit
9397 750 13815
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Product data sheet
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Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
Table 7: Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = -40 C to +85 C VIH HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level output voltage VI = VIH or VIL IO = -20 A; VCC = 2.0 V IO = -20 A; VCC = 4.5 V IO = -20 A; VCC = 6.0 V IO = -4 mA; VCC = 4.5 V IO = -5.2 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 4 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V ILI ICC input leakage current quiescent supply current VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V 0.1 0.1 0.1 0.33 0.33 1.0 40.0 V V V V V A A 1.9 4.4 5.9 3.84 5.34 V V V V V 1.5 3.15 4.2 0.5 1.35 1.8 V V V V V V Conditions Min Typ Max Unit
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Product data sheet
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Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
Table 7: Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = -40 C to +125 C VIH HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level output voltage VI = VIH or VIL IO = -20 A; VCC = 2.0 V IO = -20 A; VCC = 4.5 V IO = -20 A; VCC = 6.0 V IO = -4 mA; VCC = 4.5 V IO = -5.2 mA; VCC = 6.0 V VOL LOW-level output voltage VI = VIH or VIL IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 4 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V ILI ICC input leakage current quiescent supply current VI = VCC or GND; VCC = 6.0 V VI = VCC or GND; IO = 0 A; VCC = 6.0 V 0.1 0.1 0.1 0.4 0.4 1.0 80.0 V V V V V A A 1.9 4.4 5.9 3.7 5.2 V V V V V 1.5 3.15 4.2 0.5 1.35 1.8 V V V V V V Conditions Min Typ Max Unit
9397 750 13815
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Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
11. Dynamic characteristics
Table 8: Dynamic characteristics GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 8. Symbol Parameter Conditions see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 5.0 V; CL = 15 pF propagation delay nCP to nQ see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 5.0 V; CL = 15 pF propagation delay nR to nQ, nQ see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 5.0 V; CL = 15 pF tTHL, tTLH output transition time see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tW nCP clock pulse width HIGH or LOW see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V nR reset pulse width HIGH or LOW see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V trem removal time nR to nCP see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tsu set-up time nJ, nK to nCP see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 80 16 14 22 8 6 ns ns ns 80 16 14 22 8 6 ns ns ns 80 16 14 22 8 6 ns ns ns 80 16 14 22 8 6 ns ns ns 19 7 6 75 15 13 ns ns ns 50 18 14 15 145 29 25 ns ns ns ns 52 19 15 16 160 32 27 ns ns ns ns 52 19 15 16 160 32 27 ns ns ns ns Min Typ Max Unit Tamb = 25 C tPHL, tPLH propagation delay nCP to nQ
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Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
Table 8: Dynamic characteristics ...continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 8. Symbol th Parameter hold time nJ, nK to nCP Conditions see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V fmax maximum clock frequency see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VCC = 5.0 V; CL = 15 pF CPD power dissipation capacitance per flip-flop VI = GND to VCC
[1]
Min 3 3 3 6.0 30 35 -
Typ -8 -3 -2 23 70 83 77 30
Max -
Unit ns ns ns MHz MHz MHz MHz pF
Tamb = -40 C to +85 C tPHL, tPLH propagation delay nCP to nQ see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V propagation delay nCP to nQ see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V propagation delay nR to nQ, nQ see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tTHL, tTLH output transition time see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tW nCP clock pulse width HIGH or LOW see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V nR reset pulse width HIGH or LOW see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V trem removal time nR to nCP see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
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100 20 17 100 20 17 100 20 17
-
200 40 34 200 40 34 180 36 31 95 19 16 -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Product data sheet
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Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
Table 8: Dynamic characteristics ...continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 8. Symbol tsu Parameter set-up time nJ, nK to nCP Conditions see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V th hold time nJ, nK to nCP see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V fmax maximum clock frequency see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Tamb = -40 C to +125 C tPHL, tPLH propagation delay nCP to nQ see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V propagation delay nCP to nQ see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V propagation delay nR to nQ, nQ see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tTHL, tTLH output transition time see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tW nCP clock pulse width HIGH or LOW see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V nR reset pulse width HIGH or LOW see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 120 24 20 ns ns ns 120 24 20 ns ns ns 110 22 19 ns ns ns 220 44 38 ns ns ns 240 48 41 ns ns ns 240 48 41 ns ns ns 4.8 24 28 MHz MHz MHz 3 3 3 ns ns ns 100 20 17 ns ns ns Min Typ Max Unit
9397 750 13815
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Product data sheet
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Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
Table 8: Dynamic characteristics ...continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 8. Symbol trem Parameter removal time nR to nCP Conditions see Figure 7 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tsu set-up time nJ, nK to nCP see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V th hold time nJ, nK to nCP see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V fmax maximum clock frequency see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
[1] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of outputs.
Min 120 24 20 120 24 20 3 3 3 4.0 20 24
Typ -
Max -
Unit ns ns ns ns ns ns ns ns ns MHz MHz MHz
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74HC73
Dual JK flip-flop with reset; negative-edge trigger
12. Waveforms
nJ, nK input
VM th 1/f max VM th
tsu
tsu
nCP input
tW tPHL tPLH
nQ output
VM
tTHL nQ output VM
tTLH
tTLH tPLH
tTHL tPHL
001aab983
The shaded areas indicate when the input is permitted to change for predictable output performance. VM = 0.5 x VI.
Fig 6. Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the J and K to nCP set-up and hold times, the output transition times and the maximum clock frequency
nCP input trem tW nR input VM tPHL nQ output tPLH nQ input
VM
001aab984
VM = 0.5 x VI.
Fig 7. Waveforms showing the reset (nR) input to output (nQ, nQ) propagation delays and the reset pulse width and the nR to nCP removal time
9397 750 13815
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Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
VCC PULSE GENERATOR VI D.U.T. RT CL
mna101
VO
Test data is given in Table 9. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance.
Fig 8. Load circuitry for switching times Table 9: Supply VCC 2.0 V 4.5 V 6.0 V 5.0 V Test data Input VI VCC VCC VCC VCC tr, tf 6 ns 6 ns 6 ns 6 ns Load CL 50 pF 50 pF 50 pF 15 pF
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74HC73
Dual JK flip-flop with reset; negative-edge trigger
13. Package outline
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 14 8 MH wM (e 1)
pin 1 index E
1
7
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.13 0.068 0.044 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT27-1 REFERENCES IEC 050G04 JEDEC MO-001 JEITA SC-501-14 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-13
Fig 9. Package outline SOT27-1 (DIP14)
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Product data sheet
Rev. 03 -- 12 November 2004
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Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A X
c y HE vMA
Z 14 8
Q A2 pin 1 index Lp 1 e bp 7 wM L detail X A1 (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.010 0.057 inches 0.069 0.004 0.049
0.019 0.0100 0.35 0.014 0.0075 0.34
0.244 0.039 0.041 0.228 0.016
0.028 0.004 0.012
8 o 0
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 10. Package outline SOT108-1 (SO14)
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Product data sheet
Rev. 03 -- 12 November 2004
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Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
D
E
A X
c y HE vM A
Z 14 8
Q A2 A1 pin 1 index Lp L 1 bp 7 wM detail X (A 3) A
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.4 0.9 8 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 11. Package outline SOT337-1 (SSOP14)
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Product data sheet
Rev. 03 -- 12 November 2004
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Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c y HE vMA
Z
14
8
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
7
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 o 0
o
Fig 12. Package outline SOT402-1 (TSSOP14)
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74HC73
Dual JK flip-flop with reset; negative-edge trigger
14. Revision history
Table 10: Revision history Release date 20041112 Data sheet status Product data sheet Change notice Doc. number 9397 750 13815 Supersedes 74HC_HCT73_CNV_2 Document ID 74HC73_3 Modifications:
* * *
The format of this data sheet has been redesigned to comply with the current presentation and information standard of Philips Semiconductors. Removed type number 74HCT73. Inserted family specification. Product specification Product specification 74HC_HCT73_1 -
74HC_HCT73_CNV_2 74HC_HCT73_1
19970911 19901201
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Product data sheet
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Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
15. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
17. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
18. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 13815
(c) Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 -- 12 November 2004
20 of 21
Philips Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
19. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 20 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information . . . . . . . . . . . . . . . . . . . . 20
(c) Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 12 November 2004 Document number: 9397 750 13815
Published in The Netherlands

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