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CXP5076/5078
CMOS 4-bit Single Chip Microcomputer For the availability of this product, please contact the sales office.
Description CXP5076/5078 is a CMOS 4-bit microcomputer which consists of 4-bit CPU, ROM, RAM, I/O port, 8-bit timer, 8-bit timer/counter, 18-bit time base timer, 8-bit serial I/O, vector interruption, power on reset function, liquid crystal displayer (LCD) controller/driver, D/A conversion 14-bit PWM output port, a remote control reception circuit with noise eliminating circuit, 3-bit A/D converters, a 32kHz timer/event counter and a power supply voltage detection reset function. They are integrated into a single chip with the standby function, etc. which are to be operated at a low power consumption. Features * Instruction cycle 80 pin QFP (Plastic)
* * * * *
* * * * * * * * * * * * * *
1.9s/4.19MHz 122 s/32kHz (Possible to select with the program) ROM capacity 8192 x 8 bits (CXP5078) 6144 x 8 bits (CXP5076) RAM capacity 448 x 4 bits (Including stack, display area) 43 general purpose I/O ports 8 high current output ports LCD controller/driver (Possible to direct drive) -- Possible to select with the program the segment output of 16 to 32 -- Possible to select with the program the duty of static, 1/2, 1/3 and 1/4 -- Possible to select with the program the bias of 1/2, 1/3 14-bit PWM output for D/A conversion Remote control reception circuit 3-bit A/D converter (8 channels per circuit) 32kHz timer/event counter Power supply voltage detection reset function Low voltage operation (2.5V) ..... when operating in 122s/32kHz Rich wake-up function 8-bit/4-bit variable serial I/O Arithmetic and logical operations possible between the entire ROM area, I/O area and the accumulator by means of the memory mapped I/O 8-bit timer, 8-bit timer/event counter and 18-bit time base timer, independently controlled 2 kinds of power down modes of sleep and stop Power on reset circuit (mask option) Provided with 80 pin plastic QFP Provided with 80 pin piggyback QFP (CXP5070)
Structure Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E88037A78-PS
CXP5076/5078
Block Diagram
(Common with A/D converter analog input)
(Common with segment output S27 to S24)
(Common with segment output S31 to S28)
(Common with segment output S19 to S16)
(Common with segment output S23 to S20)
4 PORT H
(Input and output is possible by bit unit)
(Input and output is possible by port unit) 4 PORT E 4 PORT F
4 PORT A PORT B PORT C
4 PORT D
4 PORT G
Resister
ALU Accumulator
Program counter (13)
Data memory 448 x 4 bits Stack
Flag Timer (8) Sub time (8) Timer/Counter (8) Serial I/O (8) Program memory 8192 x 8 bits (CXP5078) 8144 x 8 bits (CXP5076)
Data memory Interrupt control
PWM (14)
Instruction control
Time base timer (18) A/D Converter LCD controller/ driver VL VLC1 VLC2 VLC3 Remote control receiving 32kHz timer/ event counter Port X 16 16 4 Port Y EXTAL XTAL TEX TX
Clock control
PY1/PWM
PX0/SC
VDD
VSS
INT
COM0 to COM3
PY2/WP
SEG0 to SEG15
SEG16 to SEG31
PX1/SO
PX2/SI
PY3/EC
(Common with serial I/O)
(Common with port C, port D, port G, port H)
-2-
RMC
VREF
PY0
RST
(Input and output is possible by port unit) (Common with A/D converter analog input)
4 PORT I
CXP5076/5078
Pin Configuration (Top View)
PG0/SEG19
PH3/SEG20
PH0/SEG23
PC3/SEG24
PC2/SEG25
PC1/SEG26
PH1/SEG22
PH2/SEG21
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PG1/SEG18 PG2/SEG17 PG3/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 VLC1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PD1/SEG30 PD0/SEG31 PY3/EC PY2/WP PY1/PWM PY0 PE3 PE2 PE1 PE0 PF3 PF2 PF1 PF0 PA3 PA2 PA1 PA0 PX2/SI PX1/SO PX0/SC NC PB3/AD7 PB2/AD6
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
AD0/PI0
AD1/PI1
AD2/PI2
AD3/PI3
VLC3
EXTAL
VLC2
XTAL
RST
INT
PC0/SEG27
PD3/SEG28 AD4/PB0
Note) Do not make any connections to NC pins.
-3-
AD5/PB1
RMC
VDD
NC
VL
PD2/SEG29
VREF
TEX
NC
TX
VSS
CXP5076/5078
Pin Description Symbol VDD VSS Name Supply voltage Grounding voltage I/O -- -- Equivalent Circuit Description Positive voltage supply pin GND pin Clock oscillation circuit input pin. Connect the crystal oscillator or ceramic resonator between the EXTAL and XTAL. When using as the external clock input, connect the clock oscillation source to the EXTAL pin and open the XTAL pin. Clock oscillation circuit output pin
P
P
EXTAL
Clock input
I
EXTAL NP XTAL N
XTAL
Clock output
O
RST
Reset
I/O
Serves as the incorporated power-on reset circuit output pin. N When inputting a reset signal from the outside, provide 2 instruction cycles or Output pull-up resistor (P-ch Tr) longer of an "L" level (0V). N-ch Tr output Schmitt inverter input Serves the interrupt input pin. Permits the selection with a program of the edge and the level modes. Remote control receiver input pin Schmitt inverter input Doubles as a serial interface (8 bits) input pin and as bit "2" (input) of port X.
Data Output Select Disable Standby (Only during tri-state output)
Mask option E
INT
External interrupt Remote control input Port X2 Serial input
I
RMC PX2/SI
I I
(Note 2)
PX1/SO
Port X1 Serial output
P
I/O
N
Doubles as a serial interface (8 bits) output pin and as bit "1" (input) of port X. (SO output possible to inhibit with the program.)
See Note 2) for the output circuit format. Inverter input
-4-
CXP5076/5078
Symbol
Name
I/O
Equivalent Circuit
Data Output Select Disable Standby (Only during tri-state output)
Description
(Note 2)
PX0/SC
Port X0 Serial clock
I/O
Doubles as shift clock input/output pin for the serial interface and as bit "0" (input) of port X.
See Note 2) for the output circuit format. Schmitt inverter input PY3/EC Port Y3 Event count input Port Y2 Wake-up input Port Y1 PWM generator output Port Y0 I Doubles as event counter (8 bits) input pin and as bit "3" (input) of port Y. Doubles as wake-up input pin to release the standby state and as bit "2" (input) of port Y. Doubles as PWM generator (14 bits) output pin and as bit "1" (output) of port Y. Output pin for bit "0" of port Y. This 4-bit input/output port permits its each individual bit to be programmed to serve either as input or output. For the output format, a tri-state and pullup resistor possible to be programmed, and it is also used as the standby resetting pin. This 4-bit input/output port has the functions that are equivalent to those of port A. It is also used for A/D converter input. This 4-bit input/output port permits its each individual port to be programmed to serve either as input or output. For the output format, a tri-state and pullup resistor possible to be programmed. This 4-bit input/output port has the functions that are equivalent to those of port E. This 4-bit input/output port has the functions that are equivalent to those of port E. It is also used for A/D converter input.
PY2/WP
I
Schmitt inverter input
Data
PY1/PWM
O
Output Select Disable
(Note 1)
PY0
O
See Note 1) for the output circuit format.
PA0 to PA3
Port A
I/O
Data Output Select Disable Standby
(Note 2)
PB0/AD4 to PB3/AD7
Port B Analog voltage input
I/O
(Only during tri-state output)
P
PE0 to PE3 PF0 to PF3 PI0/AD0 to PI3/AD3
Port E
I/O
N
Port F
I/O
See Note 2) for the output circuit format. Inverter input
Port I Analog voltage input
I/O
-5-
CXP5076/5078
Symbol PD3/ SEG31 to PD0/ SEG28 PC3/ SEG27 to PC0/ SEG24 PH3/ SEG23 to PH0/ SEG20 PG3/ SEG19 to PG0/ SEG16
Name Port D Segment output
I/O
Equivalent Circuit
Description Doubles as a 4-bit output port (For the output format, the inverter and pull-up resistor possible to be programmed.) and as the segment signal output pin for LCD. Doubles as a 4-bit output port (The output format is equivalent to port D.) and as the segment signal output pin for LCD. Doubles as a 4-bit output port (The output format is equivalent to port D.) and as the segment signal output pin for LCD. (Possible to designate in bit units.) Doubles as a 4-bit output port (The output format is equivalent to port D.) and as the segment signal output pin for LCD.
O
P Segment N
Port C Segment output
O
The transfer gate input signal is controlled based on 1/2, 1/3 bias method in advance.
Data Output Select Standby LCD/PORT select Port C, D, G, H (Note 3)
Port H Segment output
O
Port G Segment output
See Note 3) for the output circuit format. O
P
N
SEG0 to SEG15
Segment output
O The transfer gate input signal is controlled based on 1/2, 1/3 bias methods in advance.
Segment signal output pin for LCD
P
COM0 to COM3
Common output
O
N
Common signal output pin for LCD
Transfer gate output VLC1 to VLC3 VL
Power supply for LCD Cut-off output
--
Bias power supply pin for LCD Control pin which cuts off the current input to the bias resistor for the external LCD during standby.
O
N
-6-
CXP5076/5078
Symbol
Name
I/O
Equivalent Circuit
Description
WP
Wake-up input
I Schmitt inverter input
Mask option
It is the input pin to release the standby mode, and release by "1".
TEX
32kHz T/C clock input
I
TEX P
NP
N
Input pin for 32kHz timer clock generation circuit. Connect the 32.768kHz crystal oscillator between TEX and TX. When using as the event clock input, connect the clock oscillation source to the TEX pin, open the TX pin. Output of clock generation circuit Reference voltage input for power supply voltage resetting circuit. Connect the zener diode normally.
TX
32kHz T/C clock output Reference voltage input
O
TX
VREF
I
For all output ports, the output states of ports during standby possible to be programmed to the state holding before standby or the change to the high impedance. When the pull-up resistor output is selected, it becomes a pulled-up state even it is input port. During standby, it is impossible to change to the high impedance of PY0 and PY1 in the inverter output state. To change to the high impedance, select the pull-up resistor output, and then set to the high level output ("1" state).
-7-
CXP5076/5078
Note 1) Possible to select out of the following two ways for the output circuit format. (port units: programmable) (a) Inverter output (b) Pull-up resistor output
Standby Output Select Data P P P
N
Note 2) Possible to select out of the following two ways for the output circuit format. (port units: programmable) (a) Tri-state output (b) Pull-up resistor output
Standby Output Select P P Disable P Data N
Note 3) Possible to select out of the following two ways for the output circuit format. (port units: programmable) (a) Inverter output (b) Pull-up resistor output
LCD/PORT Select Standby Output Select P P Data N P
As the output pull-up resistor is CMOS pull-up output of about 10k, the pull-up resistor becomes OFF state during "L" output. -8-
CXP5076/5078
Absolute Maximum Ratings Item Power supply voltage LCD bias voltage Input voltage Output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage tamperature Allowable power dissipation Symbol VDD VCL1, VCL2, VCL3 VIN VOUT IOH IOH IOL IOLC IOL Topr Tstg PD Rating -0.3 to +7.0 -0.3 to +7.01 -0.3 to +7.01 -0.3 to +7.01 -5 -50 15 20 100 -20 to +75 -55 to +150 600 Unit V V V V mA mA mA mA mA C C mW
(Ta = -20 to +75C, VSS = 0V) Remarks
General purpose port2: per pin Entire pins total General purpose port2: per pin High current port3: per pin Entire pins total
1 VLC1, VLC2, VLC3, VIN and VOUT should not exceed VDD + 0.3V. 2 Specifies the output current of the general purpose I/O port PA to PI, SO, SC, PY0 and PY1. 3 The high current operation transistors are the N-ch transistors of the PC and PD ports. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operation conditions. Exceeding those conditions may adversely affect the reliability of the LSI. Recommended Operating Condition Item Symbol Min. 4.5 Power supply voltage VDD 2.5 LCD bias voltage VCL1, VCL2, VCL3 VIH High level input voltage VIHS VIHEX VIL Low level input voltage Operating temperature VILS VILEX Topr VSS 0.7VDD 0.8VDD 0 0 -0.3 -20 5.5 VDD VDD VDD 0.3VDD 0.2VDD 0.4 +75 V V V V V V V V C Hysteresis input2 EXTAL pin3 Hysteresis input2 EXTAL pin3 Max. 5.5 Unit V Remarks Guaranteed range of operation by EXTAL clock Guaranteed range of operation by TEX clock, guaranteed range of data hold during STOP. Liquid crystal power supply range1 (Vss = 0V)
VDD - 0.4 VDD + 0.3
1 The optimum value is determined by the characteristics of the liquid crystal display element used. 2 The TEX pin when the counter mode is selected by each of INT, RMC, PX0, PX2, PY2, PY3, RST pins and mask option. 3 Specified only during external clock input. -9-
CXP5076/5078
Electrical Characteristics DC characteristics Item Symbol Pin Condition
(Ta = -20 to +75C, Vss = 0V) Min. Typ. Max. Unit 4.0 3.5 4.0 2.4 0.4 0.6 1.5 0.5 -0.5 0.1 -0.1 -1.5 40 -40 10 -10 10 V V V V V V V A A A A A VDD = 4.5V, IOH = -0.5mA2 VDD = 4.5V, IOH = -1.0mA2 VDD = 4.5V, IOH = -10A3 VDD = 4.5V, IOH = -200A3 VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V
High level output voltage
VOH
Low level output voltage
VOL IIHE IILE IIHT IILT IILR IIL
PA to PI1 PX0, PX1 PY0, PY1 VL (VOL only) RST (VOL only) PC1, PD1
EXTAL TEX4
Input current
High impedance I/O leakage IIZ current Common output RCOM impedance Segment output impedance RSEG
RST5 VDD = 5.5V, VIL = 0.4V PA6, PB6, PE6, PF6, PI6, PX06, PX16, PX28, PY07, PY17, PY28, PY38, VDD = 5.5V, VI = 0, 5.5V INT8, RMC8, 5, TEX4 RST COM0 to COM3 SEG0 to SEG15 SEG16 to SEG311 VDD = 5V VLC1 = 3.75V VLC2 = 2.5V VLC3 = 1.25V Entire output pins open
-400 A
10
A
3 5
5 15
k k
IDD1
Crystal oscillation (C1 = C2 = 22pF) of VDD = 5.5V, 4.19MHz Crystal oscillation (C1 = C2 = 47pF) of VDD = 3V, 32kHz Sleep mode VDD VDD = 5.5V, 4.19MHz oscillation VDD = 3V, 32kHz oscillation Stop mode VDD = 3V, 32kHz with T/C VDD = 5.5V, 32kHz without T/C (For mask option select counter, Pin is fixed.) Other than VLC1 to VLC3, COM0 to COM3, Clock 1MHz SEG0 to SEG15, 0V other than the measured pins SEG16 to SEG311, VSS, VDD pins - 10 -
7
20
mA
IDD2
50
250
A
Supply current
IDDSP1 IDDSP2 IDDS1
5 40 7
12 200 40
mA A A
IDDS2
10
A
Input capacity
CIN
10
20
pF
CXP5076/5078
1 The PC, PD, PG and PH show when the combined pins are selected as the port, and SEG16 to SEG31 show when the combined pins are selected as the segment output. 2 It is when the respective pins of PA to PI, PX0 and PX1 select the tri-state output circuit, and PY0 and PY1 are when the inverter output circuit is selected. 3 It is when the respective pins of PA to PI, PX0, PX1, PY0 and PY1 select the pull-up resistor. 4 The TEX pin specifies the input current when the crystal oscillation is selected by the mask option, and specifies the leakage current when the schmitt input is selected. 5 The RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. 6 The respective pins of PA, PB, PE, PF, PI, PX0 and PX1 specify the input current when the pull-up resistor is selected, and specify the leakage current when the port state during using the tri-state output circuit or standby is selected at high impedance. 7 The respective pins of PY0 and PY1 specify the input current when the pull-up resistor is selected, and specify the leakage current when the port state during standby is selected at high impedance. 8 The respective pins of PX2, PY2, PY3, INT and RMC only specify the leakage current.
AC characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rising and falling times System clock frequency Event count clock input pulse width Event count clock input rising and falling times Event count input clock input pulse width Event count input clock rising and falling times Symbol fc tXL tXH tCR tCF fCS tEL tEH tER tEF tTL tTH tTR tTF Pin XTAL EXTAL
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Condition Fig. 1, Fig. 2 Min. 1 90 200 32.768 tsys1 + 0.05 20 10 20 Typ. Max. Unit 5 MHz ns ns kHz s ms s ms
EXTAL TEX2 TX EC EC TEX3 TEX3
Fig. 1, Fig. 2 (External clock drive) VDD = 2.5 to 5.5V Fig. 3 Fig. 4 Fig. 4 Fig. 4 Fig. 4
1 tsys in the EXTAL input clock is 8/fc. tsys in the TEX input clock is 4/fcs. 2 Specified when the crystal oscillation mode is selected by the mask option. 3 Specified when the counter mode is selected by the mask option. Note) When adjusting the frequency accurately, there may be cases in which they may differ from Fig. 2.
- 11 -
CXP5076/5078
1/fc
VDD - 0.4V EXTAL 0.4V
tXH
tCF
tXL
tCR
Fig. 1. Clock timing
Crystal oscillation Ceramic oscillation
External clock
EXTAL
XTAL
EXTAL
XTAL
C1
C2
OPEN
Fig. 2. Clock applying condition
Crystal oscillation
TEX
TX
C1
C2
Fig. 3. 32kHz clock applying condition
0.8VDD EC TEX 0.2VDD
tEH tTH
tEF tTF
tEL tTL
tER tTR
Fig. 4. Event count clock timing
- 12 -
CXP5076/5078
(2) Serial transfer Item Symbol SC Pin
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Condition Input mode Output mode Input mode SC Output mode1 Output mode2 SC input mode SC output mode SC input mode SC output mode Min. tsys/4 + 1.42 2tsys tsys/8 + 0.7 tsys - 0.1 tsys - 1.6 0.1 0.2 tsys/8 + 0.5 0.1 tsys/8 + 0.5 tsys/8 + 1.6 tsys/8 + 0.5 Max. Unit s s s s s s s s s s s s
Serial transfer clock (SC) tKCY cycle time Serial transfer clock (SC) tKH high and low level widths tKL Serial data input setup time (against SC ) Serial data input hold time (against SC ) High data output delay time from SC falling3 High data output delay time from SC falling4 Low data output delay time from SC falling
tSIK tKSI tKSO tKSO tKSO
SI SI SO SO SO
Notes) 1. tsys in the EXTAL input clock is 8/fc. (It is impossible to use in TEX input clock.) 2. The load of data output delay is 50pF + 1TTL. 1 It is specified when PX0/SC pin is selected to the tri-state output by the program. 2 It is specified when PX0/SC pin is selected to the pull-up resistance by the program. As the tsys receives restriction by this item, take notice that it limits the upper limit of the system clock frequency fc. 3 This item is specified when PX1/SO pin is selected to the tri-state output by the program. 4 This item is specified when PX1/SO pin is selected to the pull-up resistance by the program.
tKCY tKL tKH
0.8VDD SC 0.2VDD
tSIK
tKSI
0.8VDD SI Input data 0.2VDD
tKSO
0.8VDD SO 0.2VDD Output data
Fig. 5. Serial transfer timing - 13 -
CXP5076/5078
(3) A/D converter Analog input voltage 0.0 to 0.33V 0.82 to 1.29V 1.78 to 2.21V 2.69 to 3.06V 3.56 to 4.06V 4.62 to 5.0V AD0 to AD7 VDD = 5V Pin Condition
(Ta = -20 to +75C, Vss = 0V) Digital conversion value 000 001 010 011 100 101
Note) The digital conversion value are the values when ABH address of the RAM file 1 in the program are read.
(4) Power Supply Voltage Detection Reset Function Item Power supply voltage detection reset function of operation voltage range Power supply voltage drop detection function Symbol VLPOP Pin VDD Condition Voltage range allowing system operation (32kHz system operation below VDD = 4.5V)
(Ta = -20 to + 75C, Vss = 0V) Min. 2.5 Typ. Max. 5.5 Unit V
VPOP
VDD
When VREF pin voltage is 3.3V Flag set when voltage drops System reset when voltage rises
3.8
4.0
4.2
V
The graph in Fig. 6 shows the relationship between the power supply voltage VDD and reference voltage VREF of the power supply voltage detection reset function. Note) The graph in Fig. 6 serves as guide to the function operation area obtained using average devices. Individual adjustment is needed when Zener diodes, etc., are connected to the VREF pin.
VDD [V] 5.5
2.5
0
1.6
5.0
VREF [V]
Fig. 6. Power supply voltage detection reset function chart
- 14 -
CXP5076/5078
(5) Others Item External interruption high and low level widths Reset input low level width Wake-up input high level width Symbol tI1H, tI1L tRSL tWPH Pin INT RST WP PA0 to PA3
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Condition During edge detection mode Min. tsys + 0.05 2tsys1 Stop mode Sleep mode Stop mode Sleep mode 500 tsys + 0.05 500 tsys + 0.05 Max. Unit s s ns s ns s
Wake-up input low level width
tWPL
Note) tsys in the EXTAL input clock is 8/fc. tsys in the TEX input clock is 4/fcs. 1 For resetting when operating in TEX input clock, hold the low level more than the oscillation stabilizing time of EXTAL input clock.
tI1L tI1H
0.8VDD INT (Rising edge) 0.2VDD
tI1H
tI1L
0.8VDD INT (Falling edge) 0.2VDD
Fig. 7. Interruption input timing
tRSL
RST 0.2VDD
Fig. 8. Reset input timing
tWPH
WP
0.8VDD
Fig. 9. Wake-up input timing
tWPL
PA0 to PA3 0.2VDD
Fig. 10. Wake-up input timing - 15 -
CXP5076/5078
Power on reset Item Power supply rising time Power supply cut-off time Symbol tR tOFF Pin VDD Condition Power on reset
(Ta = -20 to +75C, Vss = 0V) Min. 0.05 1 Max. 50 Unit ms ms
Repetitive power on reset
Specifies only when power on reset function is selected.
4.5V VDD 0.2V tR The power supply should rise smoothly. tOFF 0.2V
Fig. 11. Power on reset
- 16 -
CXP5076/5078
Notes on Application See Fig. 11, Additive capacity calculation chart, when using the crystal oscillator and select the appropriate capacity.
Ta = -20 to +75C, VDD = 4.5 to 5.5V
C - Additive capacity [pF]
200 EXTAL XTAL 150 C1 100 C1 = C2 = C C2
50
0.1
1
5 10 100 f - Crystal oscillation frequency [MHz]
Fig. 12. Crystal oscillation circuit additive capacity calculation chart Note) The above chart shows a range in which the average quartz resonator has a relatively fast oscillation rising edge and stable characteristics. The capacity should be selected to correspond to the appropriate constant for each quartz resonator, should the frequency of the quartz resonator be accurately adjusted. Fig. 13 shows an example of a circuit which can accurately adjust the frequency. Used here a trimmer capacitor.
VDD
EXTAL
XTAL Rd
C1
C2
Fig. 13. Frequency adjustment circuit When using the A/D converter as the key input, it is recommended that the circuit structure shown in Fig. 14 be used.
VDD AD 4.7k 1.2k 1.8k 3.3k 8.2k
SW1 VSS
SW2
SW3
SW4
SW5
(Resistance is all E12 series)
Fig. 14. Recommended example of key circuit by A/D converter - 17 -
CXP5076/5078
Package Outline
Unit: mm
80PIN QFP (PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1 64 41 + 0.1 0.15 - 0.05 0.15
65
40
+ 0.4 14.0 - 0.1
17.9 0.4
A 80 25 + 0.2 0.1 - 0.05
0.8 0.12 M
+ 0.15 0.35 - 0.1
+ 0.35 2.75 - 0.15
0 to 10 DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.6g LEAD TREATMENT LEAD MATERIAL PACKAGE MASS
SONY CODE EIAJ CODE JEDEC CODE
QFP-80P-L01 QFP080-P-1420
- 18 -
0.8 0.2
1
24
16.3

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