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CXP824P40A
CMOS 8-bit Single Chip Microcomputer
Description The CXP824P40A is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, capture timer counter, fluorescent display tube, controller/driver, remote control reception circuit, CTL duty detection circuit, 14-bit PWM output and highspeed output circuit besides the basic configurations of 8-bit CPU, PROM, RAM, and I/O port. The CXP824P40A also provides sleep/stop function that enables lower power consumption. CXP824P40A is the PROM-incorporated version of the CXP82440A with built-in mask ROM. This provides the additional feature of being able to write directly into the program. Thus, it is most suitable for evaluation use during system development and for small-quantity production. 100 pin QFP (Plastic)
Structure Silicon gate CMOS IC
Features * Wide-range instruction system (213 instructions) to cover various types of data -- 16-bit arithmetic/multiplication and division/boolean bit operation instructions * Minimum instruction cycle 400ns at 10MHz operation 122s at 32kHz operation * Incorporated PROM capacity 40K bytes * Incorporated RAM capacity 1120 bytes (including fluorescent display area) * Peripheral functions -- A/D converter 8-bit, 8-channel, successive approximation method (Conversion time of 32s/10MHz) -- Serial interface Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel 8-bit clock sync type, 1 channel -- Timers 8-bit timer, 8-bit timer/counter, 19-bit time base timer 16-bit capture timer/counter, 32kHz timer/counter -- Fluorescent display tube controller/driver Maximum of 384 segments display possible 1 to 16-digit dynamic display Dimmer function High voltage drive output (40V) On-chip pull-down resistor (Mask option) Hardware key scan function (Maximum of 16 x 8 key matrix compatible) -- Remote control receiving circuit Incorporated noise elimination circuit 8-bit measurement counter with on-chip 6-stage FIFO -- PWM output 14 bits, 1 channel -- CTL duty detection circuit -- High-speed output circuit RTG 4 pins * Interruption 19 factors, 15 vectors, multi-interruption possible * Standby mode SLEEP/STOP * Package 100-pin plastic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E94Z17-PP
Block Diagram
AVREF
AVSS
PE0/EC0/INT0 PE1/EC1/INT1 PE2/INT2 PE3/INT3/NMI
T0 to T7
8
PORT A
PA0/AN0 to PA7/AN7 SPC 700 CPU CORE 7 CLOCK GEN./ SYSTEM CONTROL 8
8
A/D CONVERTER
TEX TX EXTAL XTAL RST VDD Vpp VSS
PA0 to PA7
PORT B
T15/S24 to T8/S31 RAM
8
PD0/S0 to PI7/S23 VFDP PROM 40K BYTES RAM 1120 BYTES
24
FDP CONTROLLER/ DRIVER
PB0 to PB6 PB7
PE0/INT0/EC0 2
8 BIT TIMER/COUNTER 0
8 BIT TIMER 1 2
PORT G
PB6/SI1 PB7/SO1 PB5/SCK1
SERIAL INTERFACE UNIT 1
PORT F
PB1/CS0 PB3/SI0 PB4/SO0 PB2/SCK0 FIFO 222 PRESCALER/ TIME BASE TIMER
SERIAL INTERFACE UNIT 0
PORT E
PE7/TO PB0/CINT PE1/INT2/EC1 2
16 BIT CAPTURE TIMER/COUNTER 2
REALTIME PULSE GENERATOR CH0 4 CH1
PORT H
PE7/ADJ
PG0/RTO0 to PG3/RTO3
PORT I
-2-
FIFO
PE4/RMC
REMOCON
PORT D
PE5/CTL PE7/DDO
INTERRUPT CONTROLLER
CTL DUTY DET
PORT C
PE6/PWM
14 BIT PWM GENERATOR
8
PC0 to PC7
8
PD0 to PD7
6 2
PE0 to PE5 PE6 to PE7
32kHz TIMER/COUNTER
8
PF0 to PF7
8
PG0 to PG7
8
PH0 to PH7
8
PI0 to PI7
CXP824P40A
CXP824P40A
Pin Assignment (Top View)
PE0/EC0/INT0
PG3/RTO3
PG2/RTO2
PG1/RTO1
PG0/RTO0
PG7
PG6
PG5
PG4
Vss
VFDP
Vpp
VDD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PE1/EC1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC PE5/CTL PE6/PWM PE7/TO/DDO/ADJ PB0/CINT PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0/KR0 PC1/KR1 PC2/KR2 PC3/KR3 PC4/KR4 PC5/KR5 PC6/KR6 PC7/KR7 PH0 PH1 PH2 PH3 PH4 PH5 PH6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 T7 T8/S31 T9/S30 T10/S29 T11/S28 T12/S27 T13/S26 T14/S25 T15/S24 PI7/S23 PI6/S22 PI5/S21 PI4/S20 PI3/S19 PI2/S18 PI1/S17 PI0/S16 PF7/S15 PF6/S14 PF5/S13 PF4/S12 PF3/S11 PF2/S10 PF1/S9 PF0/S8 PD7/S7 PD6/S6 PD5/S5 PD4/S4 PD3/S3
T0
T1
T2
T3
T4
T5 PD1/S1
Note) 1. Vpp (Pin 90) must be connected to VDD. 2. Vss (Pins 41 and 91) are both connected to GND. -3-
PA0/AN0
PA1/AN1
PA2/AN2
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7
PD0/S0
PD2/S2
EXTAL
AVREF
XTAL
AVss
RST
PH7
TEX
Vss
TX
T6
CXP824P40A
Pin Description Pin code PA0/AN0 to PA7/AN7 PB0/CINT PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0/KR0 to PC7/KR7 PD0/S0 to PD7/S7 PE0/INT0/ EC0 PE1/INT1/ EC1 PE2/INT2 PE3/INT3/ NMI PE4/RMC PE5/CTL PE6/PWM PE7/TO/ DDO/ADJ PF0/S8 to PF7/S15 PG0/RTO0 to PG3/RTO3 PG4 to PG7 I/O (Port A) 8-bit I/O port. I/O can be set in single bit units. (8 pins) Functions
I/O/ Analog input
Analog inputs to A/D converter. (8 pins)
I/O/Input I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input Output/Output (Port B) 8-bit I/O port. I/O for lower 7 bits can be set in a unit of single bits. Uppermost bit (PB7) is for output only. (8 pins)
Capture input to 16-bit timer/counter. Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1). (Port C) 8-bit I/O port. I/O can be set in a unit of single Serves as key return inputs when operating bits. Capable of driving key scan with FDP segment signal. 12mA sync current. (8 pins) (Port D) 8-bit output port. (8 pins) FDP segment signal outputs.
I/O/Input
Output/Output
Input/Input/Input Input/Input/Input Input/Input Input/Input/Input Input/Input Input/Input Output/Output Output/Output/ Output/Output (Port F) 8-bit output port. (8 pins) (Port E) 8-bit port. Lower 6 bits are for inputs; upper 2 bits are for outputs. (8 pins) Inputs for external interruption request. (4 pins)
External event inputs for timer/counter. (2 pins)
Non-maskable interruption request input.
Remote control reception circuit input. Input for CTL duty direction circuit. 14-bit PWM output. Output for the 16-bit timer/counter rectangular waves, CTU duty detection, and 32kHz oscillation frequency demultiplication. FDP segment signal outputs.
Output/Output
I/O/Output
I/O
(Port G) Outputs for real-time pulse generator (RTG). 8-bit I/O port. I/O can Functions as high-precision, real-time pulse be set in a unit of single output port. bits. Data for the lower (4 pins) 4 bits are gated with the contents of RTO or OR-gate output. (8 pins)
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CXP824P40A
Pin code PH0 to PH7 PI0/S16 to PI7/S23 T8/S31 to T15/S24 T0 to T7 VFDP EXTAL XTAL TEX TX RST AVREF AVSS VDD Vpp VSS Input I/O
I/O
Functions (Port H) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) (Port I) 8-bit output ports. (8 pins) FDP segment signal outputs.
Output/Output
Output/Output Output
Outputs for FDP timing (digit) signals/segment signals. FDP timing signal outputs. FDP voltage supply when incorporated resistor is set by mask option. Crystal connectors system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. Crystal connectors for 32kHz timer/counter clock oscillation. Set 32kHz crystal oscillator between TEX and TX. For usage as event input, attach clock source to TEX, and open TX. Low-level active, system reset. Reference voltage input for A/D converter. A/D converter GND. Vcc supply. VCC supply for incorporated PROM writing. Connect to VDD during normal operation. GND.
Output Input Output Input Input
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CXP824P40A
I/O Circuit Format for Pins Pin Port A Circuit format When reset
Port A data
PA0/AN0 to PA7/AN7
Data bus
Port A direction "0" when reset
IP
Input multiplexer
Hi-Z
RD (Port A) Port A input selection "0" when reset Input protection circuit A/D converter
8 pins Port B
Port B data
PB0/CINT PB1/CS0 PB3/SI0 PB6/SI1
Data bus
Port B direction "0" when reset
IP
Hi-Z
Schmitt input
RD (Port B)
4 pins Port B
CINT CS0 SI0 SI1
SCK OUT Output enable Port B output selection
PB2/SCK0 PB5/SCK1
"0" when reset Port B data Port B direction "0" when reset Data bus RD (Port B) SCK in Schmitt input IP
Hi-Z
2 pins
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CXP824P40A
Pin Port B
SO Ouput enable Port B output selection
Circuit format
When reset
PB4/SO0
"0" when reset Port B data Port B direction "0" when reset Data bus IP
Hi-Z
1 pin Port B
RD (Port B)
Internal reset signal SO Output enable
PB7/SO1
Port B output selection "1" when reset Port B data "1" when reset Data bus Pull-up transistor approx. 200k RD (Port B)
High level
1 pin Port C
Port C data
PC0/KR0 to PC7/KR7
Port C direction "0" when reset Data bus RD (Port C)
IP
Hi-Z
8 pins Port E PE0/EC0/INT0 PE1/EC1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC PE4/CTL 6 pins
Key input signal
High current drive of 12mA possible
Schmitt input IP
EC0/INT0 EC1/INT1 INT2 INT3/NMI RMC CTL Data bus RD (Port E)
Hi-Z
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CXP824P40A
Pin Port E
PWM Port E output selection
Circuit format
When reset
PE6/PWM
"0" when reset Port E data "1" when reset Data bus
High level
1 pin
RD (Port E)
Port E
Output enable TO DDO ADJ16K ADJ2K 0 1 MPX 2 3
PE7/TO/ DDO/ADJ
Port E output selection Port E output selection "00" when reset Port E output selection "0" when reset Port E data "1" when reset Data bus ADJ signal is a frequency demultiplication output for 32kHz oscillation frequency adjustment. ADJ2 can be used for buzzer output.
High level
1 pin
RD (Port E)
Port G
RTO data "0" when reset
PG0/RTO0 to PG3/RTO3
Port G data
Hi-Z
Port G direction "0" when reset Data bus IP
4 pins Port G Port H PG4 to PG7 PH0 to PH7
RD (Port G)
Port G or Port H data
Port G or Port H direction "0" when reset Data bus RD (Port G or Port H)
IP
Hi-Z
12 pins
-8-
CXP824P40A
Pin PD0/S0 to PD7/S7 PF0/S8 to PF7/S15 PI0/S16 to PI7/S23
Data bus
Circuit format Port D Port F Port I
Segment output data High voltage drive transistor
When reset
Output selection control signal ("0" when reset) OP Pull-down resistor
Data for Port D, F, or I "0" when reset
Mask option
Hi-Z or Low level (when PD resistance is added)
VFDP
24 pins
RD (Port D, F, or I)
T15/S24 to T8/S31 T0 to T7
High voltage drive transistor Segment output data Output selection control signal ("0" when reset) OP Pull-down resistor Mask option
Hi-Z or Low level (when PD resistance is added)
16 pins
VFDP
EXTAL XTAL
EXTAL
IP
IP
* Diagram shows circuit composition during oscillation. * Feedback resistor is removed during stop.
Oscillation
XTAL
2 pins
TEX TX
TEX
IP
IP
* Diagram shows circuit composition during oscillation.
Oscillation
TX * When the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed, and TEX and TX become "Low" level and "High" level respectively.
2 pins
Pull-up resistor
RST
OP Mask option IP
1 pin
Schmitt input
Hi-Z or High level (when pull-up resistance is added)
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CXP824P40A
Absolute Maximum Ratings Item Symbol VDD Supply voltage Vpp AVss Input voltage Output voltage Display output voltage VIN VOUT VOD IOH High level output current IODH1 IODH2 High level total output current Low level output current IOH IODH IOL IOLC Rating -0.3 to +7.0 -0.3 to +13.0 -0.3 to +0.3 -0.3 to +7.01 -0.3 to +7.01 VDD - 40 to VDD + 0.3 -5 -15 -35 -40 -100 15 20 100 -20 to +75 -55 to +150 600 Unit V V V V V V mA mA mA mA mA mA mA mA C C mW Incorporated PROM
(Vss = 0V reference) Remarks
As P channel transistor is open drain, VDD is reference. All pins excluding outputs2 (value per pin) Display outputs S0 to S23 (value per pin) Display outputs T0 to T7, and T8/S31 to T15/S24 (value per pin) Total for all pins excluding display outputs Total for all display outputs Port 1 High current Port 13 Total for all output pins
Low level total output current IOL Operating temperature Storage temperature Topr Tstg
Allowable power dissipation PD
1) VIN and VOUT must not exceed VDD + 0.3V. 2) Specifies output current of general-purpose I/O ports. 3) The high current drive transistor is the N-CH transistor of Port C (PC). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI.
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CXP824P40A
Recommended Operating Conditions Item Symbol Min. 4.5 3.5 2.7 2.5 Vpp VIH High level input voltage VIHS VIHEX VIL Low level input voltage Operating temperature VILS VILEX Topr Max. 5.5 5.5 5.5 5.5 Unit V V V V V V V V V V V C
(Vss = 0V reference) Remarks High-speed mode Guaranteed operation range Low-speed mode Guaranteed operation range Guaranteed operation range with TEX clock Guaranteed data hold range during STOP 4 1 Hysteresis input2 EXTAL3 1 Hysteresis input2 EXTAL3
Supply voltage
VDD
Vpp = VDD 0.7VDD 0.8VDD VDD VDD
VDD - 0.4 VDD + 0.3 0 0 -0.3 -10 0.3VDD 0.2VDD 0.4 +75
1) Value for each pin of normal input port (PA, PB4, PC, PG, PH). 2) Value of the following pins: RST, CINT, CS0, SCK0, SCK1, SI0, SI1, EC0/INT0, EC1/INT1, INT2, INT3/NMI, RMC, CTL. 3) Specifies only during external clock input. 4) Vpp and VDD should be set a same voltage.
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CXP824P40A
Electrical Characteristics DC Characteristics Item High level output current Low level output current Symbol VOH Pins PA, PB, PC, PE6, PE7, PG, PH PC IIHE IILE Input current IIHT IILT IILR Display output current EXTAL Conditions VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V TEX RST S0 to S23 IOH S24/T15 to S31/T8, T0 to T7 S24/T15 to S31/T8, T0 to T7 S24/T15 to S31/T8, T0 to T7 PA to PC, PE, PG, PH VDD = 4.5V VOH = VDD - 2.5V VDD = 5.5V VIL = 0.4V 0.5 -0.5 0.1 -0.1 -1.5 -8 -20 (Ta = -10 to +75C, Vss = 0V reference) Min. 4.0 3.5 0.4 0.6 1.5 40 -40 10 -10 -400 Typ. Max. Unit V V V V V A A A A A mA mA
VOL
Open drain output leakage current ILOL (P-CH Tr off state) Pull-down resistance I/O leakage current RL
VDD = 5.5V VOL = VDD - 35V VFDP = VDD - 35V VDD = 5V VFDP = VDD - 35V VDD = 5.5V VI = 0, 5.5V
-20
A
60
100
270
k
IIZ
10
A
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CXP824P40A
Item
Symbol IDD1
Pins
Conditions High speed mode operation (1/2 frequency demultiplier clock) VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF)
Min.
Typ.
Max.
Unit
20
40
mA
IDD2 Power supply current VDD
VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) SLEEP mode VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF)
STOP mode VDD = 5.5V, 10MHz crystal oscillation; and termination of 32kHz oscillation
450
1100
A
IDDS1
1.2
8
mA
IDDS2
9
30
A
IDDS3 Pins other than S0 to S31, T0 to T7, PB7, PE6, AVREF, AVSS, VFDP, VDD, VSS
30
A
Input capacity
CIN
Clock 1MHz 0V for all pins excluding measured pins
10
20
pF
When all pins are open. The leakage carrent is not specified because PB7 is dedicated for output.
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CXP824P40A
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time System clock frequency Event count input pulse width Event count input rise time, fall time Symbol fC Pin XTAL EXTAL EXTAL EXTAL EC0, EC1 EC0, EC1 TEX TX TEX TEX
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Conditions Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 VDD = 2.7 to 5.5V Fig. 2 (32kHz clock application condition) Fig. 3 Fig. 3 10 20 Min. 1 37.5 200 Typ. Max. 10 Unit MHz ns ns ns 20 ms
tXL tXH tCR tCF tEH tEL tER tEF
fC
tsys + 50
32.768
kHz
tTL tTH tTR tTF
s ms
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control clock register (address: 00FEH). tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Fig. 1. Clock timing
1/fc
VDD - 0.4V EXTAL 0.4V tXH tCF tXL tCR 32kHz clock application condition Crystal oscillation
Fig. 2. Clock application conditions
Crystal oscillation Ceramic oscillation External clock
EXTAL
XTAL
EXTAL
XTAL
TEX
TX
C1
C2
74HC04
C1
C2
Fig. 3. Event count clock timing
TEX EC0 EC1
0.8VDD 0.2VDD
tEH tTH
tEF tTF
tEL tTL
tER tTR
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CXP824P40A
(2) Serial transfer (CH0) Item CS0 SCK0 delay time CS0 SCK0 float delay time CS0 SO0 delay time CS0 SO0 float delay time CS0 High level width SCK0 cycle time SCK0 High, Low level width SI0 input set-up time (for SCK0 ) SI0 input hold time (for SCK0 ) SCK0 SO0 delay time Note 1) Symbol Pin SCK0
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
tDCSK
tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200
2tsys + 200 16000/fc
tDCSKF SCK0 tDCSO
SO0
tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO
SCK0
SCK0
tsys + 100
8000/fc - 50 100 200
SI0
SI0
tsys + 200
100
SO0
tsys + 200
100
ns ns
tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control clock register (address: 00FEH). tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
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CXP824P40A
Fig. 4. Serial transfer CH0 timing
tWHCS
CS0
0.8VDD
0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 0.2VDD
0.8VDD
tSIK
tKSI
0.8VDD SI0 Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 Ouput data 0.2VDD
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CXP824P40A
Serial transfer (CH1) Item SCK1 cycle time SCK1 High, Low level width SI1 input set-up time (for SCK1 ) SI1 input hold time (for SCK1 ) SCK1 SO1 delay time Symbol Pin SCK1
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Input mode Ouput mode SCK1 Input mode Ouput mode SI1 SCK1 input mode SCK1 ouput mode SI1 SCK1 input mode SCK1 ouput mode SO1 SCK1 input mode SCK1 ouput mode Min. 1000 16000/fc 400 8000/fc - 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL.
Fig. 5. Serial transfer CH1 timing
tKCY tKL tKH
0.8VDD SCK1 0.2VDD
tSIK
tKSI
0.8VDD SI1 Input data 0.2VDD
tKSO
0.8VDD SO1 0.2VDD Output data
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CXP824P40A
(3) A/D converter characteristics (Ta = -10 to +75C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference) Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Reference input voltage Analog input voltage VZT1 VFT2 Ta = 25C VDD = 5.0V VSS = AVSS = 0V -10 4910 160/fADC3 12/fADC3 AVREF
AN0 to AN7
Symbol
Pin
Condition
Min.
Typ.
Max. 8 3
Unit Bits LSB mV mV s s
10 4970
70 5030
tCONV tSAMP
VREF VIAN IREF
VDD - 0.5 0 Operation mode 0.6
VDD AVREF 1.0 10
V V mA A
AVREF current IREFS
AVREF
SLEEP mode STOP mode 32kHz operation mode
Fig. 6. Definition of A/D converter terms
FFH FEH
Linearity error 01H 00H VZT Analog input VFT
1) VZT: Value at which the digital transfer value changes from 00H to 01H and vice versa. 2) VFT: Value at which the digital transfer value changes from FEH to FFH and vice versa. 3) fADC indicates the below values due to ADC operation clock selection (ADCS: Bit 6 of address 00F9H). During PS2 selection, fADC = fc/2 During PS1 selection, fADC = fc
Digital conversion value
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CXP824P40A
(4) Interruption, reset input Item External interruption High, Low level width Reset input Low level width
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pin INT0 INT1 INT2 NMI/INT3 RST Condition Min. Max. Unit
tIH tIL tRSL
1
s
32/fc
s
Fig. 7. Interruption input timing
tIH tIL
0.8VDD INT0 INT1 INT2 NMI/INT3 (NMI specifies only for the falling edge) 0.2VDD tIL tIH
Fig. 8. RST input timing
tRSL
RST 0.2VDD
(5) Others Item CLK input High, Low level width Symbol Pin CTL
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Min. Max. Unit ns
tCTH tCTL
tsys = 2000/fc
tsys + 200
Fig. 9. Other timing
tCTH tCTL
0.8VDD CTL 0.2VDD
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CXP824P40A
Appendix Fig. 10. Recommended oscillation circuit
(i) Main clock
(ii) Main clock
(iii) Sub clock
EXTAL
XTAL Rd
EXTAL
XTAL Rd
EXTAL TEX
XTAL TX Rd C2
C1
C2 C1 C2
C1
Manufacturer
Model CSA4.19MG CSA8.00MTZ
fc (MHz) 4.19 8.00 10.00
C1 (pF)
C2 (pF)
Rd ()
Circuit example
(i) 30 30 0 (ii)
MURATA MFG CO., LTD.
CSA10.0MTZ CST4.19MGW CST8.00MTW CST10.0MTW
4.19 8.00 10.00 4.19
RIVER ELETEC CO., LTD
HC-49/U03
8.00 10.00 4.19
12
12
0 (i)
KINSEKI LTD.
HC-49/U (-S)
8.00 10.00
27 20 50
27 0 20 22 1M (iii)
P3
32.768kHz
Those marked with an asterisk () signify types with built-in ground capacitance (C1, C2).
Mask option table Option Package ROM capacitance Reset pin pull-up resistance High voltage drive pin pull-up resistor Mask product 100-pin plastic QFP 32K bytes/40K bytes Existent/non-existent Existent/non-existent CXP824P40Q-1100-pin plastic QFP PROM 40K bytes Existent Non-existent (S0/PD0 to S23/PI7) Existent (T0 to T15/S24)
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CXP824P40A
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
+ 0.1 0.15 - 0.05
23.9 0.4 + 0.4 20.0 - 0.1
+ 0.4 14.0 - 0.01 17.9 0.4
15.8 0.4
A
0.65 0.12 M
+ 0.35 2.75 - 0.15
0.15
0 to 15 DETAIL A
0.8 0.2
(16.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.4g
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