View HCPL3180_86602.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Agilent HCPL-3180 2 Amp Output Current, High Speed IGBT/MOSFET Gate Drive Optocoupler
Data Sheet
Features * 2 A minimum peak output current * 250 KHz maximum switching speed * High speed response: 200 ns max Propagation delay over temperature range * 10 KV/us minimum common mode rejection (CMR) at VCM=1500 V * Under voltage lockout protection (UVLO) with hysteresis * Wide operating temperature range: -40 C to +100 C * Wide VCC operating range: 10 V to 20 V * 20 ns typ pulse width distortion * Safety Approvals: UL approval pending 3750 VRMS for 1 minute. CSA approval DIN EN 60747-5-2 approval pending Applications * Plasma Display Panel (PDP) * Distributed power architecture (DPA) * Switch mode rectifier (SMR) * High performance DC/DC convertor * High performance switch mode power supply (SMPS) * High performance uninterruptible power supply (UPS) * Isolated IGBT/Power MOSFET gate drive
Description This family of devices consists of a GaAsP LED. The LED is optically coupled to an integrated circuit with a power stage. These optocouplers are ideally suited for high frequency driving of power IGBT and MOSFETs used in Plasma Display Panels, high performance DC/DC convertors and motor control invertor applications. Ordering Information Specify part number followed by option number (if desired): Example : HCPL-3180-XXX
N/C ANODE CATHODE N/C
1 2 3 4
8 7 6
VCC VO VO
5 VEE
Functional Diagram
No option = Standard DIP package, 50 per tube. 300 = Gull Wing Surface Mount Option, 50 per tube. 500 = Tape and Reel Packaging Option. 060 = DIN EN 60747-5-2 Option, VIORM=630 Vpeak (pending approval)
A 0.1 uF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/ or degradation which may be induced by ESD.
HCPL-3180 Standard DIP Package
HCPL-3180 Gull Wing Surface Mount Option 300
2
Solder Reflow Temperature Profile
300
PREHEATING RATE 3C + 1C/-0.5C/SEC. REFLOW HEATING RATE 2.5C 0.5C/SEC. PEAK TEMP. 245C PEAK TEMP. 240C
200
PEAK TEMP. 230C
TEMPERATURE (C)
2.5C 0.5C/SEC. 160C 150C 140C 3C + 1C/-0.5C 30 SEC. 30 SEC.
SOLDERING TIME 200C
100
PREHEATING TIME 150C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE
ROOM TEMPERATURE
0
0
50
100 TIME (SECONDS)
150
200
250
Regulatory Information The HCPL-3180 is pending approval by the following organizations: DIN EN 60747-5-2 Pending approval under DIN EN-60747-5-2 with VIORM = 630 VPEAK UL Approval under UL 1577, component recognition program up to VISO = 2500 VRMS. Pending 3750 VRMS. CSA Approval under CSA Component.
3
DIN EN 60747-5-2 Insulation Characteristics (HCPL-3180 Option 060)
Description
Installation classification per DIN EN 0110 1997-04 for rated mains voltage 150 Vrms for rated mains voltage 300 Vrms for rated mains voltage 600 Vrms Climatic Classification Pollution Degree (DIN EN 0110 1997 -04) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b* VIORM x 1.875=VPR, 100% Production Test withtm=1 sec, Partial discharge < 5 pC Input to Output Test Voltage, Method a* VIORM x 1.5=VPR, Type and Sample Test, tm=60 sec,Partial discharge < 5 pC Highest Allowable Overvoltage (Transient Overvoltage tini = 10 sec) Safety-limiting values - maximum values allowed in the event of a failure. Case Temperature Input Current** Output Power** Insulation Resistance at TS, VIO = 500 V TS IS, INPUT PS, OUTPUT RS 175 230 600 >109 C mA mW W VIORM VPR VPR VIOTM I - IV I - III I - II 55/100/21 2 630 1181 Vpeak Vpeak
Symbol
HCPL-3180
Unit
945
Vpeak
6000
Vpeak
*
Refer to the optocoupler section of the Isolation and Control Components Designer's Catalog, under Product Safety Regulations section, (DIN) for a detailed description of Method A and Method B partial discharge test profiles. ** Refer to the following figure for dependence of PS and I S on ambient temperature.
S S, INPUT CURRENT - I
800 700 600 500 400 300 200 100 0 0 25 50 75 100 125 150 175 200 P S (mW) IS (mA)
OUTPUT POWER - P
T S - CASE TEMPERATURE - C
4
Insulation and Safety Related Specifications
Parameter
Minimum External Air Gap (Clearance)
Symbol
L(101)
HCPL-3180 Units
7.1 mm
Conditions
Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance path along body. Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. DIN IEC 112/VDE 0303 Part 1
Minimum External Tracking (Creepage)
L(102)
7.4
mm
Minimum Internal Plastic Gap (Internal Clearance)
0.08
mm
Tracking Resistance (Comparative Tracking Index) Isolation Group
CTI
>175
V
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
Absolute Maximum Ratings
Parameter
Storage Temperature Junction Temperature Average Input Current Peak Transient Input Current (<1s pulse width, 300 pps) Reverse Input Voltage "High" Peak Output Current "Low" Peak Output Current Supply Voltage Output Voltage Output Power Dissipation Total Power Dissipation Lead Solder Temperature Solder Reflow Temperature Profile
Symbol
TS Tj IF(AVG) IF(TRAN) VR IOH(PEAK) IOL(PEAK) VCC - VEE VO(PEAK) PO PT
Min
-55 -40
Max
+125 +125 25 1.0 5 2.5 2.5
Units
C C mA A V A A V V mW mW
Note
1
2 2
-0.5 0
25 VCC 250 295
3 4
+260 C for 10 sec., 1.6 mm below seating plane See Package Outline Drawings section
Recommended Operating Conditions
Parameter
Power Supply Input Current (ON) Input Voltage (OFF) Operating Temperature
Symbol
VCC - VEE IF(ON) VF(OFF) TA
Min
10 10 - 3.0 - 40
Max
20 16 0.8 100
Units
V mA V C
Note
5
Electrical Specifications (DC) Over recommended operating conditions unless otherwise specified.
Parameter
High Level Output Current
Symbol
IOH
Min
0.5 2.0
Typ
Max
Units
A A A A V
Test Conditions
VO = (VCC -4 V) VO = (VCC -10 V) VO = (VEE+2.5 V) VO = (VEE + 10 V) IO = -100 mA IO = 100 mA Output Open IF = 10 to 16 mA Output Open VIF = -3.0 to 0.8 V IO = 0 mA VO > 5 V IF - 10 mA
Fig
2, 3 17 5, 6 18 1, 3 19 4, 6 20 7, 8
Note
5 2 5 2 6, 7
Low Level Output Current
IOL
0.5 2.0
High Level Output Voltage
VOH VOL ICCH ICCL
VCC - 4 0.5
Low Level Output Voltage
V
High Level Supply Current
3.0
6.0
mA
Low Level Supply Current
3.0
6.0
mA
9, 15, 21
Threshold Input Current Low to High
IFLH VFHL VF D VF/ VUVLO+ VUVLO
8.0
mA
Threshold Input Voltage High to Low Input Forward Voltage Temperature Coefficient of Forward Voltage UVLO Threshold
0.8 1.2 TA 1.5 -1.6 7.9 7.4 0.5 5 60 1.8
V V mV/C V V V V pF
16
VO > 5 V IF = 10 mA
22, 34
UVLO Hysteresis Input Reverse Breakdown Voltage Input Capacitance
UVLOHYST BVR CIN
IR = 10 uA f = 1 MHz, VF = 0 V
6
Switching Specifications (AC) Over recommended operating conditions unless otherwise specified.
Parameter
Propagation Delay Time to High Output Level
Symbol
tPLH
Min
50
Typ
150
Max
200
Units
ns
Test Conditions
IF = 10 mA Rg = 10 W f = 250 kHz Duty Cycle = 50% Cg = 10 nF
Fig
10, 11, 12, 13, 14, 23
Note
16
Propagation Delay Time to Low Output Level
tPHL
50
150
200
ns
Pulse Width Distortion Propagation Delay Difference Between Any Two Parts Rise Time
PWD PDD (tPHL - tPLH) tr tf tUVLO ON tUVLO OFF |CMH| 10 -90
20
65 90
ns ms 35, 36 CL = 1 nF Rg = 0 W 23
12 17
25
ns
Fall Time UVLO Turn On Delay UVLO Turn Off Delay Output High Level Common Mode Transient Immunity
25 2.0 0.3
ns us us kV/s TA = +25 C If = 10 to 16 mA VCM = 1.5 kV VCC = 20 V TA = +25 C Vf = 0 V VCM = 1.5 kV VCC = 20 V VCM = 1.5 kV 24 13, 14 22
Output Low Level Common Mode Transient Immunity
|CML|
10
kV/s
13, 15
Package Characteristics
Parameter
Input-Output Momentary Withstand Voltage
Symbol
VISO RI-O CI-O
Min
2500
Typ
Max
Units
Vrms
Test Conditions
TA = +25 C, RH < 50% VI-O = 500 V Freq = 1 MHz
Fig
Note
8, 9
Input-Output Resistance Input-Output Capacitance
1011 1
W pF
9
Notes: 1. Derate linearly above +70 C free air temperature at a rate of 0.3 mA/C. 2. Maximum pulse width = 10 us, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak minimum = 2.0 A. See Application section for additional details on limiting I OL peak. 3. Derate linearly above +70 C, free air temperature at the rate of 4.8 mW/C. 4. Derate linearly above +70 C, free air temperature at the rate of 5.4 mW/C. The maximum LED junction temperature should not exceed +125 C. 5. Maximum pulse width = 50 us, maximum duty cycle = 0.5%. 6. In this test, VOH is measured with a dc load current. When driving capacitive load VOH will approach V CC as I OH approaches zero amps. 7. Maximum pulse width = 1 ms, maximum duty cycle = 20%. 8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage > 3000 Vrms for 1 second (leakage detection current limit I I-O < 5 uA). 9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. 10. tPHL propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level of the rising edge of the V O signal 11. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions 12. PWD is defined as |t PHL - t PLH | for any given device. 13. Pin 1 and 4 need to be connected to LED common.
7
14. Common mode transient immunity in the high state is the maximum tolerable dV CM/dt of the common mode pulse VCM to assure that the output will remain in the high state (i.e. V O > 10.0 V). 15. Common mode transient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e. V O < 1.0 V). 16. tPHL propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level of the rising edge of the V O signal 17. The difference between tPHL and tPLH between any two HCPL-3180 parts under same test conditions.
(VOH-VCC) - HIGH OUTPUT VOLTAGE DROP - V
0 -0.5 -1 -1.5 -2 -2.5 -3 -40 -20 0 20 TA 40 60 80 100
-1 (VOH-VCC) - OUTPUT HIGH VOLTAGE DROP - V
IF=10 to 16mA IOUT=-100mA VCC=10 to 20V VEE=0V
-2
100 C -40 C 25 C
-3
-4 I F=10mA to 16mA VCC=10 to 20 V VEE=0V 0 1 2 3 4
-5
-6 IOH - OUTPUT HIGH CURRENT - A
Figure 1. VOH Vs Temperature
Figure 3. VOH Vs IOH
2.5 IOH - OUTPUT HIGH CURRENT -A 2 1.5 1 0.5 0 -40 10 TA 60 IF= 10 to 16mA VOUT=(VCC -4) VCC =10 to 20V VEE=0V
0.3 VOL - OUTPUT LOW VOLTAGE - V 0.25 0.2 0.15 0.1 0.05 0 -40 -20 0 20 40 60 80 100 TA - TEMPERATURE - C VF(OFF) = -3.0 TO 0.8V IOUT = 100mA VCC = 10 to 20V VEE = 0
Figure 2. I OH Vs Temperature
Figure 4. VOL Vs Temperature
8
3 IOL - OUTPUT LOW CURRENT-A 2.5 2 1.5 1 0.5 0 -40 -20 0 20 TA
Figure 5. IOL Vs Temperature
3.5 ICC - SUPPLY CURRENT - mA
VF(OFF) = -3.0 TO 0.8V VOUT = 2.5V VCC = 10 to 20V VEE = 0
3.3 3.1 2.9 2.7 2.5 IF=10mA for ICCH IF=0mA for I CC L TA=25C VEE=0V 10 12 14 16 18
ICCL ICCH
40
60
80
100
20
VCC - SUPPLY VOLTAGE - V
Figure 8. ICC Vs V CC
4 VOL - OUTPUT LOW VOLTAGE - V VF(OFF) = -3 to 0.8V VCC=10 to 20 V VEE=0V
IFLH - LOW TO HIGH CURRENT THRESHOLD mA 5 4 3 2 1 0 -40 -20 0 20 40 60 80 100 TA - TEMPERATURE - C
Figure 9. IFLH Vs Temperature
3
VCC= 10 to 20V VEE= 0V Output= Open
2
1
25 C 0C 100 C 0 0.5 1 1.5 2 2.5
0 IOL - OUTPUT LOW CURRENT - A
Figure 6. VOL Vs IOL
4 ICC - SUPPLY CURRENT - mA 3.5 3 2.5 2 1.5 1 0.5 0 -40 -20 0 20 40 60 80 100 VCC=20V VEE=0V I F=10mA for ICCH I F=0mA for I CC L
250 TP - PROPAGATION DELAY - nS IF=10mA TA=25C Rg=10ohm Cg=10nF Duty Cycle=50% f=250KHZ
200
150
ICCH ICCL
100 TPLH TPHL 50 10 15 20 25 VCC- SUPPLY VOLTAGE -V
TA - TEMPERATURE - oC
Figure 7. I CC Vs Temperature
Figure 10. Propagation Delay Vs VCC
9
250 TP - PROPAGATION DELAY - nS
250 TP - PROPAGATION DELAY -nS
VCC =20V, VEE=0V Rg=10 ohm, Cg=10nF Duty Cycle = 50% f=250KHz TA=25C
200
200
I F=10mA TA=25C Rg=10ohm Duty Cycle=50% f=250KHZ
150
150
100 TPLH TPHL 50 6 8 10 12 14 16 IF - FORWARD LED CURRENT - mA
100 Tplh Tphl 50 5 10 15 20 25 Cg - LOAD CAPACITANCE - nF
Figure 11. Propagation Delay Vs IF
Figure 14. Propagation Delay Vs Cg
250 TP - PROPAGATION DELAY - nS
20 VO - OUTPUT VOLTAGE - V
TPHL TPLH IF=10mA VCC=20V, VEE=0V Rg=10 ohm, Cg=10nF Duty Cycle = 50% f=250KHz
200
15
150
10
100
5
50 -40 -20 0 20 40 60 80 100 TA - TEMPERATURE - C
Figure 12. Propagation Delay Vs Temperature
0 0 1 2 3 4 5 IF - FORWARD LED CURRENT - mA
Figure 15. Transfer Characteristics
250 TP PROPAGATION DELAY - nS IF=10mA TA=25C Cg=10nF Duty Cycle=50% f=250KHZ
1000 100
T A = 25C IF
IF - FORWARD CURRENT - mA
200
10 1.0 0.1 0.01
150
+ VF -
100 TPLH TPHL 50 10 20 30 40 50 Rg - SERIES LOAD RESISTANCE - ohm
0.001
1.10
1.20
1.30
1.40
1.50
1.60
V F - FORWARD VOLTAGE - VOLTS
Figure 13. Propagation Delay Vs Rg Figure 16. Input Current Vs Forward Voltage
10
1
8 4V/10V + + VCC=10 to 20V
2 IF=10mA to 16mA 3
7 0,1 F 6 IoH
4
5
Shield
Figure 17. IOH Test Circuit
1
8 VCC=10 to 20V + -
2
7 0,1 F
IoL
3
6 + 2.5V/10V
4
5
Shield
Figure 18. IOL Test Circuit
1
8 VCC=10 to 20V + -
2 IF=10mA to 16mA 3
7 0,1 F 6 VOH 100mA 5
4
Shield
Figure 19. VOH Test Circuit
11
1
8 + -
2
7 100mA 0,1 F
3
6
VOL
4
5
Shield
Figure 20. VOL Test Circuit
1
8 VCC=10 to 20V + -
2
7 0,1 F
IF
3
6
VO > 5V
4
5
Shield
Figure 21. IFLH Test Circuit
1
8 VCC + -
2 IF=10mA 3
7 0,1 F 6 +VO > 5V
4
5
Shield
Figure 22. UVLO Test Circuit
12
If= 10 to 16mA
1 500 + 250KHz 50% Duty Cycle 3 2
8 Vcc=+20V + 7 0,1 F 6 10 10nF Vout If Tr Tf
90% 50% 10%
GND
4
5 Shield Tplh Tphl
Figure 23. TPLH, TPHL, Tr and Tf Test Circuit and Waveform
IF VCM 1 8 Vcc =+20V 5V + 2 7 0,1 F 3 6 Switching at A IF=10mA 5 Shield VO Switching at B IF=0mA VOL dt 0V dv/dt= Vcm/dt
+ -
VO
VO
VOH
4
+ Vcm =1500V
Figure 24. CMR Test Circuit and Waveform
13
Applications Information Eliminating Negative IGBT Gate Drive To keep the IGBT firmly off, the HCPL-3180 has a very low maximum VOL specification of 0.4 V. The HCPL-3180 realizes the very low VOL by using a DMOS transistor with 1 W (typical) on resistance in its pull down circuit. When the HCPL3180 is in the low state, the IGBT gate is shorted to the emitter by Rg + 1 W. Minimizing Rg and the lead inductance from the HCPL-3180 to the IGBT gate and emitter (possibly by mounting HCPL-3180 on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive in many applications as shown in Figure 25. Care should be taken with such a PC board design to avoid routing the IGBT collector or emitter traces close to the HCPL-3180 input as this can result in unwanted coupling of transient signals into the input of HCPL-3180 and degrade performance. (If the IGBT drain must be routed near the HCPL-3180 input, then the LED should be reverse biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the HCPL3180)
+5 V 1 270 GND 2
Selecting the Gate Resistor (Rg) for HCPL-3180 Step 1: Calculate Rg minimum from the IOL peak specification. The IGBT and Rg in Figure 25 can be analyzed as a simple RC circuit with a voltage supplied by the HCPL-3180.
Rg VCC - VOL I OLPEAK 20 - 3 = 2 = 8.5
case) = 16 mA, Rg ~ 10 W, Max Duty Cycle = 80%, Qg = 100 nC, f = 200 kHz and TAMAX = +75 C:
PE = 16mA * 1.8V * 0.8 = 23mW PO = 4.5mA * 20V + 0.85J * 200kHz PO (MAX ) @ 75C = 260mW 226mW = 250mW - ( 5C * 4.8mW / C )
The value of 4.5 mA for ICC in the previous equation was obtained by derating the ICC max of 6 mA to ICC max at +75 C. Since PO for this case is greater than the PO(max), Rg must be increased to reduce the HCPL3180 power dissipation.
Po ( SwitchingM Ax ) = P0 ( Max ) - PO ( Bias ) = 226mW - 90mW = 136mW E SW(Max) = PO(Sitching Max) / f = 136mW / 200 KHz = 0.68W
The VOL value of 3 V in the previous equation is the VOL at the peak current of 2 A. (See Figure 6). Step 2: Check the HCPL-3180 power dissipation and increase Rg if necessary. The HCPL-3180 total power dissipation (PT) is equal to the sum of the emitter power (PE) and the output power (PO).
PT = PE + PO PE = I F * VF * DutyCycle PO = PO(BIAS) + PO(SWITCHING) = I CC * VCC + ESW Rg ; Qg * f = (I CC ) * VCC + ESW Rg ; Q g * f
(
(
)
)
For Qg = 100 nC a Value of Esw = 0.68 UW gives a Rg = 15 ohm
For the circuit in Figure 25 with the circuit in with IF (worst
+HVDC 8 VCC=+15V + 7 Rg 0,1 F 3 6
74XXX Open Collector 4 5 Shield
GND - HVDC
Figure 25. Recommended LED Drive and Application Circuit for HCPL-3180
14
2 1.8 1.6 1.4 1.2 ESW(uJ) 1 0.8 0.6 0.4 0.2 0 0 10 20 30 40 50 Rg(ohm)
Figure 27. Energy Dissipated in the HCPL-3180 for each IGBT
LD = 442 C/W
Qg = 100nC
T JE
T JD DC = 126 C/W TC CA = 83 C/W*
LC = 467 C/W
TA
Figure 28. Thermal Model
Thermal Model (Discussion applies to HCPL-3180) The steady state thermal model for the HCPL-3180 is shown in Figure 28. The thermal resistance values given in this model can be used to calculate the temperatures at each node for a given operating condition. As shown by the model, all heat generated flows through QCA which raises the case temperature TC accordingly. The value of QCA depends on the conditions of the board design and is, therefore, determined by the designer. The value of QCA = +83 C/W was obtained from thermal measurements using a 2.5 x 2.5 inch PC board, with small traces (no ground plane), a single HCPL- 3180 soldered into the center of the board and still air. The absolute maximum power dissipation derating specifications assume a QCA value of +83 C/W From the thermal mode in Figure 28 the LED and detector IC junction temperatures can be expressed as:
TJE = PE * ( LC //( LD + DC ) + CA + PD * ( TJD = PE * (
LC * DC + CA ) + PD * ( DC //( LD + LC ) + CA ) + T A LC + DC + LD
LC * DC + CA ) + T A LC + DC + LD
Inserting the values for QLC and QDC shown in Figure 28 gives: TJE = PE*(+256 C/W + QCA)+ PD*(+57 C/W + QCA) + TA TJD = PE*(+57 C/W + QCA)+ PD*(+111 C/W + QCA) + TA For example, given PE = 45 mW, PO = 250 mW, TA = +70 C and QCA= +83 C/W: TJE = PE*(+339 C/W + PD*(+140 C/W +TA = 45 mW*+339 C/W + 250 mW*+140 C/W + +70 C = +120 C TJD = PE*(+140 C/W + PD*+194 C/W +TA = 45 mW*+140 C/W + 250 mW*+194 C/W + +70 C = +125 C TJE and TJD should be limited to +125 C based on the board layout and part placement (QCA) specific to the application.
TJE = LED junction temperature TJD = detector IC junction temperature TC = case temperature measured at the center of the package bottom QLC = LED-to-case thermal resistance QLD = LED-to-detector thermal resistance QDC = detector-to-case thermal resistance QCA = case-to-ambient thermal resistance *Q CA will depend on the board design and the placement of the part.
15
LED Drive Circuit Considerations for Ultra High CMR Performance Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 29. The HCPL3180 improves CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins 5-8 as shown in Figure 30. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off ) during common mode transients. For example, the recommended application circuit (Figure 25), can achieve 10 kV/us CMR while minimizing component complexity. Techniques to keep the LED in the proper state are discussed in the next two sections.
Figure 29. Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers.
Figure 30. Optocoupler Input to Output Capacitance Model for Shielded Optocouplers.
Vcc= 20V
Figure 31. Equivalent Circuit for Figure 25 During Common Mode Transient.
Figure 32. Not Recommended Open Collector Drive Circuit.
Figure 33. Recommended LED Drive Circuit for Ultra-High CMR
16
CMR with the LED On (CMRH) A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by over-driving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of 10 mA provides adequate margin over the maximum IFLH of 8 mA to achieve 10 kV/us CMR. CMR with the LED Off (CMRL) A high CMR LED drive circuit must keep the LED off (VF VF(OFF)) during common mode transients. For example, during a -dVCM/dt transient in Figure 31, the current flowing through CLEDP also flows through the RSAT and VSAT of the logic gate. As long as the low state voltage developed across the logic gate is less than VF(OFF) the LED will remain off and no common mode failure will occur. The open collector drive circuit, shown in Figure 32, cannot keep the LED off during a +dVCM/dt transient, since all the current flowing through CLEDN must be supplied by the LED, and it is not recommended for applications requiring ultra high CMRL performance. Figure 33 is an alternative drive circuit, which like the recommended application circuit (Figure 25), does achieve ultra high CMR performance by shunting the LED in the off state. Under Voltage Lockout Feature The HCPL-3180 contains an under voltage lockout (UVLO) feature that is designed to protect the IGBT under fault conditions which cause the HCPL-3180 supply voltage (equivalent to the fully charged IGBT gate voltage) to drop below a level necessary to keep the IGBT in a low resistance state. When the HCPL-3180 output is 17
in the high state and the supply voltage drops below the HCPL3180 UVLO- threshold (typ 7.5 V) the optocoupler output will go into the low state. When the HCPL-3180 output is in the low state and the supply voltage rises above the HCPL-3180 VUVLO+ threshold (typ 8.5 V) the optocoupler output will go into the high state (assume LED is "ON").
IPM Dead Time and Propagation Delay Specifications The HCPL-3180 includes a Propagation Delay Difference (PDD) specification intended to help designers minimize "dead time" in their power invertor designs. Dead time is the time during which the high and low side power transistors are off. Any overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices from the high voltage to the low-voltage motor rails.
20 18 Vo - OUTPUT VOLTAGE - V 16 14 12 10 8 6 4 2 0 0 5 10 15 20 (VCC-VEE) - SUPPLY VOLTAGE - V
Figure 34. Under Voltage Lock Out
Figure 35. Minimum LED Skew for Zero Dead Time
To minimize dead time in a given design, the turn on of LED2 should be delayed (relative to the turn off of LED1) so that under worst-case conditions, transistor Q1 has just turned off when transistor Q2 turns on, as shown in Figure 35. The amount of delay necessary to achieve this condition is equal to the maximum value of the propagation delay difference specification, PDDMAX, which is specified to be 90 ns over the operating temperature range of -40 C to +100 C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specification as shown in Figure 36. The maximum dead time for the HCPL-3180 is 180 ns (= 90 ns-(90 ns)) over the operating temperature range of -40 C to +100 C. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs.
Figure 36. Waveforms for Dead Time
18
www.agilent.com/ semiconductors
For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (916) 788-6763 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6756 2394 India, Australia, New Zealand: (+65) 6755 1939 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (+65) 6755 1989 Singapore, Malaysia, Vietnam, Thailand, Philippines, Indonesia: (+65) 6755 2044 Taiwan: (+65) 6755 1843 Data subject to change. Copyright (c) 2003 Agilent Technologies, Inc. August 11, 2003 5988-9921EN

▲Up To Search▲

Price & Availability of HCPL3180

	To Download HCPL3180 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .